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Advanced Micro Devices 



Linear and Interface 
Data Book 



Copyright © 1979 by Advanced Micro Devices, Inc. 



Advanced Micro Devices cannot assume responsibility for use of any circuitry described other than circuitry entirely 

embodied in an Advanced Micro Devices' product. 




ALPHA NUMERIC INDEX 
FUNCTIONAL INDEX 
SELECTION GUIDES 
INDUSTRY CROSS REFERENCE 
DICE POLICY 
ORDERING INFORMATION 
MIL-M-3851 0/MIL-STD-883 



1 




COMPARATORS 



DATA CONVERSION PRODUCTS 



LINE DRIVERS/RECEIVERS 



MOS MEMORY AND MICROPROCESSOR INTERFACE 




OPERATIONAL AMPLIFIERS 




SPECIAL FUNCTIONS 




VOLTAGE REGULATORS 



PACKAGE OUTLINES 
GLOSSARY 

AMD FIELD SALES OFFICES, SALES REPRESENTATIVES, 
DISTRIBUTOR LOCATIONS 



Section I 

Numeric Index 1-1 

Functional Index 1-6 

Selection Guides 1-10 

Industry Cross-Reference 1-14 

Dice Policy 1-22 

Ordering Information 1-23 

MIL-M-38510/MIL-STD-883 1-26 



NUMERIC INDEX 



Product 

Am0026 

Am0056 

AmDAC-08 

Am101 

Ami 01 A 

Am 102 

Ami 05 

Ami 06 

Ami 07 

Ami 08 

Am108A 

Am110 

Ami 11 

Ami 12 

Am118 

Am119 

Ami 24 

Am124A 

Ami 39 

Am139A 

Am 1408 

SSS1408A 

Ami 458 

Ami 48 

Ami 488 

Ami 489 

Am1489A 

Ami 49 

Ami 500 

Ami 501 

Ami 508 

SSS1508A 

LF155 

LF155A 

Ami 558 

LF156 

LF156A 

LF157 

LF157A 

Am 1692 

LF198 

Am201 

Am201A 

Am202 

Am205 

Am206 

Am207 

Am208 

Am208A 

Am210 

LH2101A 



Description Page 

5MHz Two-Phase MOS Clock Driver 5-1 

5MHz Two-Phase MOS Clock Driver 5-7 

8-Bit High-Speed Multiplying D/A Converter 3-1 

Operational Amplifier 6-1 

Operational Amplifier 6-5 

Voltage Follower 6-10 

Voltage Regulator 8-1 

Voltage Comparator/Buffer 2-1 

Frequency Compensated Operational Amplifier 6-14 

Operational Amplifier 6-18 

Operational Amplifier 6-18 

Voltage Follower 6-22 

Precision Voltage Comparator 2-5 

Compensated High-Performance Operational Amplifier 6-26 

High-Speed Operational Amplifier 6-30 

Dual Voltage Comparator 2-9 

Quad Operational Amplifier 6-36 

Quad Operational Amplifier 6-36 

Low Offset Voltage Quad Comparator 2-13 

Low Offset Voltage Quad Comparator 2-13 

8-Bit Multiplying D/A Converter 3-14 

8-Bit Multiplying D/A Converter 3-14 

Dual Frequency Compensated Operational Amplifier 6-95 

Quad 741 Operational Amplifier 6-41 

Quad RS-232C Line Driver 4-1 

Quad RS-232C Line Receiver 4-4 

Quad RS-232C Line Receiver 4-4 

Quad 741 Operational Amplifier 6-41 

Dual Precision Voltage Comparator 2-31 

Dual Operational Amplifier 6-90 

8-Bit Multiplying D/A Converter 3-14 

8-Bit Multiplying D/A Converter 3-14 

JFET Input Operational Amplifier 6-43 

JFET Input Operational Amplifier 6-43 

Dual Frequency Compensated Operational Amplifier 6-95 

JFET Input Operational Amplifier 6-43 

JFET Input Operational Amplifier 6-43 

JFET Input Operational Amplifier 6-43 

JFET Input Operational Amplifier 6-43 

Three-State Differential Line Drivers 4-8 

Monolithic Sample and Hold Circuits 3-7 

Operational Amplifier 6-1 

Operational Amplifier 6-5 

Voltage Follower 6-10 

Voltage Regulator 8-1 

Voltage Comparator/Buffer 2-1 

Frequency Compensated Operational Amplifier 6-14 

Operational Amplifier 6-18 

Operational Amplifier 6-18 

Voltage Follower 6-22 

Dual Operational Amplifier 6-99 



□ 



1-1 



NUMERIC INDEX (Cont.) 



Product Description Page 

Am211 Precision Voltage Comparator 2-5 

LH21 1 1 Dual Precision Voltage Comparator 2-35 

Am212 Compensated. High-Performance Operational Amplifier 6-26 

Am216 Compensated, High-Performance Operational Amplifier 6-51 

Am216A Compensated, High Performance Operational Amplifier 6-51 

Am218 High-Speed Operational Amplifier 6-30 

Am219 Dual Voltage Comparator 2-9 

LH2201A Dual Operational Amplifier 6-99 

LH221 1 Dual Precision Voltage Comparator 2-35 

Am224 Quad Operational Amplifier 6-36 

Am224A Quad Operational Amplifier 6-36 

LH2301A Dual Operational Amplifier 6-99 

LH2311 Dual Precision Voltage Comparator 2-35 

Am239 Low Offset Voltage Quad Comparator 2-13 

Am239A Low Offset Voltage Quad Comparator 2-13 

Am248 Quad 741 Operational Amplifier 6-41 

Am249 Quad 741 Operational Amplifier 6-41 

Am2502 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am25L02 Low-Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am2503 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am25L03 Low-Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am2504 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am25L04 Low-Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am25LS240 Octal Buffer; Inverting, Three-State 4-1 3 

Am25LS241 Octal Buffer; Non-Inverting, Three-State 4-17 

Am25LS242 Quad Three-State Transceiver 4-21 

Am25LS243 Quad Three-State Transceiver 4-21 

Am25LS244 Octal Buffer Non-Inverting, Three-State 4-17 

LF255 JFET Input Operational Amplifier 6-43 

LF255A JFET Input Operational Amplifier 6-43 

LF256 JFET Input Operational Amplifier 6-43 

LF256A JFET Input Operational Amplifier 6-43 

LF257 JFET Input Operational Amplifier 6-43 

LF257A JFET Input Operational Amplifier 6-43 

Am26S10 Quad Bus Transceiver 4-57 

Am26S11 Quad Bus Transceiver 4-57 

Am26S12 Quad Bus Transceiver 4-62 

Am26S12A Quad Bus Transceiver 4-62 

Am2614 Quad Single-Ended Line Driver 4-67 

Am2615 Dual Line Receiver 4-72 

Am2616 Quad MIL-188C and RS-232C Line Driver 4-78 

Am2617 Quad RS-232C Line Receiver 4-82 

Am26LS29 Quad Three-State Single Ended RS-423 Line Driver 4-26 

Am26LS30 Dual Differential RS-422 Party Line/Quad Single Ended 

RS-423 Line Driver 4-30 

Am26LS31 Quad RS-422 High Speed Differential Line Driver 4-36 

Am26LS32 Quad RS-422 and RS-423 Differential Line Receiver 4-40 

Am26LS33 Quad Differential Line Receiver 4-40 

Am2905 Quad Two-Input OC Bus Transceiver with Three- State Receiver 4-86 

Am2906 Quad Two-Input OC Bus Transceiver with Parity 4-92 



1-2 



NUMERIC INDEX (Cont.) 



Product Description Page 

Am2907 Quad Bus Transceiver with Interface Logic 4-98 

Am2908 Quad Bus Transceiver with Interface Logic 4-98 

Am2915A Quad Three-State Bus Transceiver with Interface Logic 4-107 

Am2916A Quad Three-State Bus Transceiver with Interface Logic 4-113 

Am2917A Quad Three-State Bus Transceiver with Interface Logic 4-119 

LF298 Monolithic Sample and Hold Circuits 3-7 

Am301 Operational Amplifier 6-1 

Am301A Operational Amplifier 6-5 

Am302 Voltage Follower 6-10 

Am305 Voltage Regulator 8-1 

Am305A Voltage Regulator 8-1 

Am306 Voltage Comparator/Buffer 2-1 

Am307 Frequency Compensated Operational Amplifier 6-14 

Am308 Operational Amplifier 6-18 

Am308A Operational Amplifier 6-18 

Am310 Voltage Follower 6-22 

Am311 Precision Voltage Comparator 2-5 

Am312 Compensated, High-Performance Operational Amplifier 6-26 

Am316 Compensated, High-Performance Operational Amplifier 6-51 

Am316A Compensated, High-Performance Operational Amplifier 6-51 

Am318 High-Speed Operational Amplifier 6-30 

Am319 Dual Voltage Comparator 2-9 

Am3212 8-Bit Input/Output Port 4-125 

Am3216 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am3226 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am324 Quad Operational Amplifier 6-36 

Am324A Quad Operational Amplifier 6-36 

Am339 Low Offset Voltage Quad Comparator 2-13 

Am339A Low Offset Voltage Quad Comparator 2-13 

Am3448A IEEE-488 Quad Bidirectional Transceiver 4-137 

Am348 Quad 741 Operational Amplifier 6-41 

Am349 Quad 741 Operational Amplifier 6-41 

LF355 JFET Input Operational Amplifier 6-43 

LF355A JFET Input Operational Amplifier 6-43 

LF356 JFET Input Operational Amplifier 6-43 

LF356A JFET Input Operational Amplifier 6-43 

LF357 JFET Input Operational Amplifier 6-43 

LF357A JFET Input Operational Amplifier 6-43 

Am3692 Three-State Differential Line Drivers 4-8 

LF398 Monolithic Sample and Hold Circuits 3-7 

Am54LS240 Octal Buffer; Inverting, Three-State 4-13 

Am54S240 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am54LS241 Octal Buffer; Non-Inverting, Three-State 4-17 

Am54S241 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am54LS242 Quad Three-State Bus Transceiver 4-21 

Am54S242 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am54LS243 Quad Three-State Bus Transceiver 4-21 

Am54S243 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am54LS244 Octal Buffer, Non-Inverting, Three-State 4-17 

Am54S244 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am55107B Dual Line Receiver 4-147 



1-3 



NUMERIC INDEX (Cont.) 



Product Description Page 

Am55108B Dual Line Receiver 4-147 

Am55109 Dual Line Receiver 4-153 

Am55110 Dual Line Driver 4-153 

Am592 Differential Video Amplifier 7-1 

Am6070 Companding D-to-A Converter for Control Systems 3-28 

Am6071 Companding D-to-A Converter for Control Systems 3-40 

Am6072 Companding D-to-A Converter for PCM Communication Systems 3-52 

Am6073 Companding D-to-A Converter for PCM Communication Systems 3-64 

Am6080 Microprocessor System Compatible 8-Bit High-Speed 

Multiplying D/A Converter 3-76 

Am6081 Microprocessor System Compatible 8-Bit High-Speed 

Multiplying D/A Converter 3-84 

Am685 Voltage Comparator 2-19 

Am686 Voltage Comparator 2-27 

Am687 Dual Voltage Comparator 2-29 

Am715 High-Speed Operational Amplifier 6-55 

Am715C High-Speed Operational Amplifier 6-55 

Am71LS95 Three-State Octal Buffers 4-159 

Am71LS96 Three-State Octal Buffers 4-159 

Am71LS97 Three-State Octal Buffers 4-159 

Am71LS98 Three-State Octal Buffers 4-159 

Am723 Voltage Regulator 8-5 

Am723C Voltage Regulator 8-5 

Am725 Instrumentation Operational Amplifier 6-59 

SSS725 High-Performance Operational Amplifier 6-64 

Am725C Instrumentation Operational Amplifier 6-59 

Am7303B Octal Three-State Inverting Bidirectional Transceiver 4-163 

Am7304B Octal Three-State Bidirectional Transceiver 4-168 

Am733 Differential Video Amplifier 7-4 

Am733C Differential Video Amplifier 7-4 

Am741 Frequency-Compensated Operational Amplifier 6-70 

SSS741 Frequency-Compensated Operational Amplifier 6-64 

Am741A Frequency-Compensated Operational Amplifier 6-70 

Am74LS240 Octal Buffer; Inverting, Three-State 4-13 

Am74S240 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am74LS241 Octal Buffer; Non-Inverting, Three-State 4-17 

Am74S241 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am74LS242 Quad Three-State Bus Transceiver 4-21 

Am74S242 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am74LS243 Quad Three-State Bus Transceiver 4-21 

Am74S243 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am74LS244 Octal Buffer, Non-Inverting, Three-State 4-17 

Am74S244 Octal Buffer/Line Driver/Line Receiver with Three-State Outputs 4-142 

Am747 Dual Frequency-Compensated Operational Amplifier 6-77 

SSS747 Dual Frequency-Compensated Operational Amplifier 6-64 

Am747A Dual Frequency-Compensated Operational Amplifier 6-77 

Am748 Operational Amplifier 6-84 

Am748C Operational Amplifier 6-84 

Am75107B Dual Line Receiver 4-147 

Am75108B Dual Line Receiver 4-147 

Am75109 Dual Line Receiver 4-153 



1-4 



NUMERIC INDEX (Cont.) 



Product 

Am75110 

Am7820 

Am7820A 

Am7830 

Am7831 

Am7832 

Am7838 

Am81LS95 

Am81 LS96 

Am81 LS97 

Am81LS98 

Am8212 

Am8216 

Am8224 

Am8226 

Am8228 

Am8238 

Am8T26 

Am8T26A 

Am8T28 

Am8303B 

Am8304B 

Am8820 

Am8820A 

Am8830 

Am8831 

Am8832 

Am8838 

Am9614 

Am9615 

Am9616 

Am9617 



Description Page 

Dual Line Driver 4-153 

Dual Differential Line Receiver 4-173 

Dual Differential Line Receiver 4-173 

Dual Differential Line Driver 4-178 

Three-State Line Driver 4-182 

Three-State Line Driver 4-182 

Quad Unified Bus Transceiver 4-188 

Three-State Octal Buffers 4-159 

Three-State Octal Buffers 4-159 

Three-State Octal Buffers 4-159 

Three-State Octal Buffers 4-159 

8-Bit Input-Output Port 4-125 

4-Bit Parallel Bidirectional Bus Driver 4-132 

Clock Generator and Driver 5-13 

4-Bit Parallel Bidirectional Bus 4-132 

System Controller and Bus Driver 5-20 

System Controller and Bus Driver 5-20 

Schottky Three-State Quad Bus Driver/Receiver 4-190 

Schottky Three-State Quad Bus Driver/Receiver 4-195 

Schottky Three-State Quad Bus Driver/Receiver 4-195 

Octal Three-State Inverting Bidirectional Transceiver 4-163 

Octal Three-State Bidirectional Transceiver 4-168 

Dual Differential Line Receiver 4-173 

Dual Differential Line Receiver 4-173 

Dual Differential Line Driver 4-178 

Three-State Line Driver 4-182 

Three-State Line Driver 4-182 

Quad Unified Bus Transceiver 4-188 

Differential Line Driver 4-200 

Dual Differential Line Receiver 4-72 

Triple EIA RS-232C/MIL-STD-188C Line Driver 4-205 

RS-232C Line Receiver 4-209 



1-5 



FUNCTIONAL INDEX 



Section 1 

Numeric Index 1-1 

Functional Index 1-6 

Selection Guides 1-10 

Industry Cross-Reference 1-14 

Dice Policy 1-22 

Ordering Information 1-23 

MIL-M-38510/MIL-STD-883 1-26 

Comparators - Section II 

Ami 06/206/306 Voltage Comparator/Buffer 2-1 

Ami 11/21 1/311 Precision Voltage Comparator 2-5 

Ami 1 9/21 9/319 Dual Voltage Comparator 2-9 

Ami 39/239/339 Low Offset Voltage Quad Comparator 2-13 

Am139A/239A/339A Low Offset Voltage Quad Comparator 2-13 

Am685 Voltage Comparator 2-19 

Am686 Voltage Comparator 2-27 

Am687/687A Dual Voltage Comparator 2-29 

Ami 500 Dual Precision Voltage Comparator 2-31 

LH21 1 1/221 1/231 1 Dual Precision Voltage Comparator 2-35 

Application Notes 

A New High-Speed Comparator - The Am685 2-39 

Am685/Am686/Am687 - Designing with High-Speed Comparators 2-48 

Data Conversion Products - Section III 

AmDAC-08 8-Bit High-Speed Multiplying D/A Converter 3-1 

LF198 Monolithic Sample and Hold Circuits 3-7 

LF298 Monolithic Sample and Hold Circuits 3-7 

LF398 Monolithic Sample and Hold Circuits 3-7 

Ami 508/1 408 8-Bit Multiplying D/A Converter 3-14 

SSS1508A/1408A 8-Bit Multiplying D/A Converter 3-14 

Am2502 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am2503 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am2504 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am25L02 Low Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am25L03 Low Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am25L04 Low Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am6070 Companding D-to-A Converter for Control Systems 3-28 

Am6071 Companding D-to-A Converter for Control Systems 3-40 

Am6072 Companding D-to-A Converter for PCM Communication Systems 3-52 

Am6073 Companding D-to-A Converter for PCM Communication Systems 3-64 

Am6080 Microprocessor System Compatible 8-Bit High-Speed Multiplying 

D/A Converter 3-76 

Am6081 Microprocessor System Compatible 8-Bit High-Speed Multiplying 

D/A Converter 3-84 

Application Notes 

Companding DAC 3-96 

Line Drivers/Receivers - Section IV 

Am 1488 Quad RS-232C Line Driver 4-1 

Am 1489 Quad RS-232C Line Receiver 4-4 

Am1489A Quad RS-232C Line Receiver 4-4 

Ami 692/3692 Three-State Differential Line Drivers 4-8 



1-6 



FUNCTIONAL INDEX (Cont.) 



Line Drivers/Receivers - Section IV (Cont.) 

Am25LS240 Octal Buffer; Inverting, Three-State 4-13 

Am25LS241 Octal Buffer; Non-Inverting, Three-State 4-17 

Am25LS242 Quad Three-State Bus Transceiver 4-21 

Am25LS243 Quad Three-State Bus Transceiver 4-21 

Am25LS244 Octal Buffer, Non-Inverting, Three-State 4-17 

Am26LS29 Quad Three-State Single-Ended RS-423 Line Driver 4-26 

Am26LS30 Dual Differential RS-422 Party Line/Quad Single-Ended 

RS-423 Line Driver 4-30 

Am26LS31 Quad RS-422 High-Speed Differential Line Driver 4-36 

Am26LS32 Quad RS-422 and RS-423 Differential Line Receiver 4-40 

Am26LS33 Quad Differential Line Receiver 4-40 

Am26S10 Quad Bus Transceiver 4-57 

Am26S1 1 Quad Bus Transceiver 4-57 

Am26S12 Quad Bus Transceiver 4-62 

Am26S12A Quad Bus Transceiver 4-62 

Am2614 Quad Single-Ended Line Driver 4-67 

Am2615 Dual Differential Line Receiver 4-72 

Am2616 Quad MIL-188C and RS-232C Line Driver 4-78 

Am2617 Quad RS-232C Line Receiver 4-82 

Am2905 Quad Two-Input OC Bus Transceiver with Three-State Receiver 4-86 

Am2906 Quad Two-Input OC Bus Transceiver with Parity 4-92 

Am2907 Quad Bus Transceiver with Interface Logic 4-98 

Am2908 Quad Bus Transceiver with Interface Logic 4-98 

Am2915A Quad Three-State Bus Transceiver with Interface Logic 4-107 

Am2916A Quad Three-State Bus Transceiver with Interface Logic 4-113 

Am2917A Quad Three-State Bus Transceiver with Interface Logic 4-119 

Am3212 8-Bit Input/Output Port 4-125 

Am3216 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am3226 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am3448A IEEE-488 Quad Bidirectional Transceiver 4-137 

Am54LS/74LS240 Octal Buffer; Inverting, Three-State 4-13 

Am54LS/74LS241 Octal Buffer; Non-Inverting, Three-State 4-17 

Am54LS/74LS242 Quad Three-State Bus Transceiver 4-21 

Am54LS/74LS243 Quad Three-State Bus Transceiver 4-21 

Am54LS/74LS244 Octal Buffer; Non-Inverting, Three-State 4-17 

Am54S/74S240 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am54S/74S241 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am54S/74S242 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am54S/74S243 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am54S/74S244 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am55/75107B Dual Line Receiver 4-147 

Am55/75108B Dual Line Receiver 4-147 

Am55/75109 Dual Line Driver 4-153 

Am55/75110 Dual Line Driver 4-153 

Am71LS/81LS95 Three-State Octal Buffers 4-159 

Am71 LS/81 LS96 Three-State Octal Buffers 4-159 

Am71 LS/81 LS97 Three-State Octal Buffers 4-159 

Am71 LS/81 LS98 Three-State Octal Buffers 4-159 

Am73/8303B Octal Three-State Inverting Bidirectional Transceiver 4-163 



1-7 



Am73/83U4B UCiai I nretj-oiaie diuii boliui iai hoiovohoi 

Am78/8820 Dual Differential Line Receiver 4-173 

Am78/8820A Dual Differential Line Receiver 4-173 

Am78/8830 Dual Differential Line Driver 4-178 

Am78/8831 Three-State Line Driver 4-182 

Am78/8832 Three-State Line Driver .' 4-182 

Am78/8838 Quad Unified Bus Transceiver 4-188 

Am8T26 Schottky Three-State Quad Bus Driver/Receiver 4-190 

Am8T26A Schottky Three-State Quad Bus Driver/Receiver 4-195 

Am8T28 Schottky Three-State Quad Bus Driver/Receiver 4-195 

Am8212 8-Bit Input/Output Port 4-125 

Am8216 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am8226 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am9614 Differential Line Driver 4-200 

Am9615 Dual Differential Line Receiver 4-72 

Am9616 Triple EIA RS-232C/MIL-STD-188C Line Driver 4-205 

Am9617 RS-232C Line Receiver 4-209 

Application Notes 

Use of the Am26LS29, 30, 31 and 32 Quad Driver/Receiver 

Family in EIA-422 and 423 Applications 4-45 

MOS Memory and Microprocessor Interface — Section V 

Am0026/0026C 5MHz Two-Phase MOS Clock Driver 5-1 

Am0056/0056C 5MHz Two-Phase MOS Clock Driver 5-7 

Am8224 Clock Generator and Driver 5-13 

Am8228 System Controller and Bus Driver 5-20 

Am8238 System Controller and Bus Driver 5-20 

Operational Amplifiers - Section VI 

Am101/201/301 Operational Amplifier 6-1 

Ami 01 A/201 A/301 A Operational Amplifier 6-5 

Ami 02/202/302 Voltage Follower 6-10 

Am107/207/307 Frequency Compensated Operational Amplifier 6-14 

Am 1 08/208/308 Operational Amplifier 6-18 

Am108A/208A/308A Operational Amplifier 6-18 

Ami 10/210/310 Voltage Follower 6-22 

Ami 12/212/312 Compensated, High-Performance Operational Amplifier 6-26 

Ami 18/218/318 High-Speed Operational Amplifier 6-30 

Ami 24/224/324 Quad Operational Amplifier 6-36 

Am124A/224A/324A Quad Operational Amplifier 6-36 

Ami 48/248/348 Quad 741 Operational Amplifier 6-41 

Ami 49/249/349 Quad 741 Operational Amplifier 6-41 

LF1 55/255/355 Monolithic JFET Input Operational Amplifier 6-43 

LF1 55A/255A/355A Monolithic JFET Input Operational Amplifier 6-43 

LF1 56/256/356 Monolithic JFET Input Operational Amplifier 6-43 

LF1 56A/256A/356A Monolithic JFET Input Operational Amplifier 6-43 

LF1 57/257/357 Monolithic JFET Input Operational Amplifier 6-43 

LF157A/257A/357A Monolithic JFET Input Operational Amplifier 6-43 

Am216/316 Compensated, High-Performance Operational Amplifier 6-51 

Am216A/316A Compensated, High-Performance Operational Amplifier 6-51 

Am715/715C High-Speed Operational Amplifier 6-55 

Am725/725C Instrumentation Operational Amplifier 6-59 

SSS725/725B/725E High-Performance Operational Amplifier 6-64 



1-8 



FUNCTIONAL INDEX (Cont.) 



Operational Amplifiers - Section VI (Cont.) 

Am741/741 A/741 C/741E Frequency-Compensated Operational Amplifier 6-70 

SSS741/741C High-Performance Operational Amplifier 6-64 

Am747/747A/747C/747E Dual Frequency-Compensated Operational Amplifier 6-77 

SSS747/747C Dual 741 Operational Amplifier 6-64 

Am748/748C Operational Amplifier 6-84 

Ami 501 Dual Operational Amplifier 6-90 

Ami 558/1 458 Dual Frequency-Compensated Operational Amplifier 6-95 

LH2101A/LH2201A/ 

LH2301A Dual Operational Amplifier 6-99 

Special Functions - Section VII 

Am592 Differential Video Amplifier 7-1 

Am733/733C Differential Video Amplifier 7-4 

Voltage Regulators - Section VIII 

Am105/205/305/305A Voltage Regulator 8-1 

Am723/723C Voltage Regulator 8-5 

Section IX 

Package Outlines 9-1 

Glossary 9-5 

AMD Field Sales Offices, Sales Representatives, Distributor Locations 9-10 



1-9 



I 



SELECTION GUIDE 



OPERATIONAL AMPLIFIERS 



UNCOMPENSATED 




Page No 




LM101 


6-1 


General Purpose, 500nA lg, 5mV Vos 


LM748 


6-84 


General Purpose, 500nA lg, 5mV Vos 


LM101A 


6-5 


Improved General Purpose, 75nA lg, 
2mV Vos 


AM1501 


6-90 


Dual Improved General Purpose, 75nA 
l B , 2m V Vos 






LH2101A 


6-99 


Dual Improved General Purpose, 75nA 
l B , 2mV Vos 


725 


6-59 


Instrumentation, 100nA l B , 1mV Vos, 
5.0V/°C TCVIO 


SSS725 


6-64 


Improved Instrumentation, 80nA lg, 
.5mV Vos, 1.0V/°C TCVIO 


LM108 


6-18 


Low Input Current Precision, 2nA lg, 
2mV Vos, 0.2nA IOS 


LM108A 


6-18 


Low Input Current and Offset Voltage 
Precision, 2nA lg, 0.5mV Vos, 0.2nA 
IOS, 5/iV/°C TCVIO 


715 


6-55 


High Speed, 15V/usec slew rate, 750nA 
lg, 5m V Vos 


INTERNALLY COMPENSATED 


741 


6-70 


General Purpose, 500nA lg, 5mV Vos 


741A.E 


6-70 


Improved General Purpose, 80nA lg, 
3mV Vos, 30nA Iqs. 50 H V/VPSRR 


SSS741 


6-64 


High Performance, 50nA lg, 2mV Vos 


747 


6-77 


Dual General Purpose, 500nA lg, 5mV 
Vos 


747A.E 


6-77 


Dual Improved General Purpose, 80nA 
lg, 3mV Vos, 30nA Iqs. 50uV/VPSRR 


SSS747 


6-64 


Dual High Performance, 50nA lg, 2mV 
Vos 


AM1558 


6-95 


Dual General Purpose, 500nA lg, 5mV 
Vos 


LM124 


6-36 


Quad General Purpose, 1 50nA lg, 5mV 


LM124A 


6-36 


Vos, Single or Dual Supply, 3 to 30V, 
1 mW/op amp at +5V 


LM148 


6-41 


Quad 741, 500nA lg, 5mV Vos 


LM149 


6-41 


Quad Decompensated, 500nA lg, 5m V 
Vos A V (min.l = 5 


LM107 


6-14 


Improved General Purpose, 75nA lg, 
2mV Vos 


LM112 


6-26 


Low Input Current Precision, 2nA lg, 
2m V Vos 


LM216 


6-51 


Very Low Input Current Precision, 
150pA lg, 10mV Vos 


LM216A 


6-51 


Very Low Input Current Precision, 50pA 
lg, 3m V Vos 


LM118 


6-30 


High Speed, 50V/usec slew rate, 4mV 
Vos, 250nA lg 


LF155 


6-43 


FET Input General Purpose, 5mV Vos, 
20pA Iqs. 100pA lg 


LF155A 


6-43 


FET Input General Purpose, 2mV Vos, 
5 M V/°C TC V-io, 10pA Iqs. SOpA lg 


LF156 


6-43 


FET Input Wideband, 5mV Vos, 20pA 
lOS. 100pA lg, 7.5V/usec SR 


LF156A 


6-43 


FET Input Wideband, 2mV Vos, 5juV/°C 
TC V 10 , 10pA Iqs. 50pA lg, 10V/ 
Msec SR 


LF157 


6-43 


FET Input Wideband Decompensated, 
5mV Vos, 20pA l S- 100pA lg, 30V/ 
Msec SR (Ay = 5) 


LF157A 


6-43 


FET Input Wideband Decompensated, 
2mV Vos, 5mV/°C TC Vi , 10pA I S. 
50pA lg, 40V/ M sec SR (A v = 5) 



VOLTAGE FOLLOWERS 

Page No. 



LM102 


6-10 


Low Input Current, High Speed, 10nA 






l B , 5m V Vos, 20V/ M sec slew rate, 10%l 






Rin 


LM110 


6-22 


Improved Low Input Current, High 






Speed, 3nA lg,4mV Vos, 20V/Msec slew 






rate, 10 10 IJ Rin 



VOLTAGE COMPARATORS 

Page No. 



LM111 


2-5 


General Purpose, 100nA lg, 3mV Vos, 
250ns Response Time, 50V and 50mA 
Output 


LH2111 


2-35 


Dual General Purpose, 100nA lg, 3mV 
Vos, 250ns Response Time, 50V and 
50mA Output 


AMI 500 


2-31 


Dual General Purpose, 100nA lg, 3mV 
Vos, 250ns Response Time, 50V and 
50mA Output 


LM106 


2-1 


High Speed, 20uA lg, 2mV Vos, 40ns 
Response Time, 24V and 100mA Output 


LM119 


2-9 


Dual General Purpose, 500nA lg, 4mV 
Vos, 80ns Response Time, 35V and 25mA 
Output, +5 or +1 5V Supply 


LM139 


2-13 


Quad General Purpose, 100nA lg, 2mV 


LM139A 


2-13 


Vos, Single or Dual Supply 2 to 36V, 
1mW/comp. at +5V 


AM685 


2-19 


Very Fast ECL Output, 10mA lg, 2m V 
Vos, 6.5ns Response Time 


AM686 


2-27 


Very Fast TTL Output, 10uA lg, 2mV 
Vos, 12ns Response Time 


AM687 


2-29 


Dual Very Fast ECL Output, 10uA lg, 
2mV Vos, 6.5ns Response Time 


VOLTAGE REGULATORS 




Page No. 


723 


8-5 


General Purpose, 2-37V Output, 0.15% 
load reg., 50V input, 150mA Output 


LM105 


8-1 


General Purpose, 4.5-40V Output, 0.05% 
load reg., 50V input, 12mA Output 


DATA CONVERSION PRODUCTS 




Page No. 


AM 1508 


3-14 


8-Bit Multiplying D-to-A Converter, Ac- 
curacy 0.19%, Settling Time 300nsec typ. 


SSS1508A 


3-14 


8-Bit Multiplying D-to-A Converter, Ac- 
curacy 0.1%, Settling Time 1 35nsec 


DAC-08 


3-1 


8-Bit High-Speed Multiplying D/A Converter 


AM6070 


3-28 


Companding D-to-A Converter for Control 
Systems 


AM6071 


3-40 


Companding D-to-A Converter for Control 
Systems 


AM6072 


3-52 


Companding D-to-A Converter for PCM 
Communication Systems 


AM6073 


3-64 


Companding D-to-A Converter for PCM 
Communication Systems 


AM6080 


3-76 


Microprocessor System Compatible 8-Bit 
High-Speed Multiplying D/A Converter 


AM6081 


3-84 


Microprocessor System Compatible 8-Bit 
High-Speed Multiplying D/A Converter 


LF198, 


3-7 


Monolithic Sample and Hold Circuits 


298, 398 






AM2502, 


3-18 


8-Bit/12-Bit Successive Approximation 


03, 04 




Registers 



1-10 



LINE DRIVERS 



SELECTION 



GUIDE (Cont.) 

LINE RECEIVERS 



DUAL DIFFERENTIAL 



75109 



75110 



8830 



8831 



8832 



9614 



9621 



Open collector differential outputs 
typical current 6mA, inhibit controls 
12mA output current version of 
Am75109 

Designed for single 5.0V supply 
operation 

Dual differential device which may also 

be used as a quad single-ended driver. 

Three-state output. 

Similar to 8831 but no V cc clamp 

diodes 

5 volt supply driver with complementary 
outputs 

200mA transient capability with 130fl 
back matching resistor 



Use With 

751 07B 
751 08B 
751 07B 
751 08B 
7820 or 
7820A 
9615 or 
2615 

9615 or 

2615 

9615 

9620 



DIFFERENTIAL EIA RS-422, 
FEDERAL STD 1020 



26LS31 
26LS30 



Quad, high-speed, low output skew 
Dual, high output CMR 



26LS32 or 
26LS33 



SINGLE ENDED 

2614 I High-speed quad driver for multi-channel, 
common ground operation. 



2615 



SINGLE ENDED, EIA RS-232-C 

1488 Quad EIA RS-232C driver (14 pins) 



2616 



9616 



Quad 16-pin driver for EIA RS-232C, 
CCITT V.24 and MIL-188C interface 
Triple EIA RS-232C driver (14 pins) 



1489/ 
1489A 

2617 

9617 



SINGLE ENDED, EIA RS-423, FEDERAL STD 1030 

26LS29 I Quad, three-state | 26LS32 or 

26LS30 Quad, mode control 







BUS BUFFERS/DRIVERS 







•pd 


'OL 






(TYP) 


(MAX) 


25LS240 


Inverting octal buffer/driver with three- 


10 


48 


74LS240 


state output 


10 


24 


74S240 




4.5 


68 


81LS96 




9.0 


16 


25LS241 


Non-inverting octal buffer/driver with 


12 


48 


74LS241 


three-state output 


12 


24 


74S241 




6.0 


68 


81LS95 




12 


16 


25LS242 


Inverting buffer/driver with two quad 


10 


48 


74LS242 


data paths connected input-to-output 


10 


24 


t74S242 




4.5 


68 


25LS243 


Non-inverting buffer/driver with two 


12 


48 


74LS243 


quad data paths connected input-to- 


12 


24 


t74S243 


output 


6.0 


68 


25LS244 


Non-inverting octal buffer/driver with 


12 


48 


74LS244 


three-state output and two inverting 


12 


24 


74S244 


enables 


6.0 


68 


81LS97 




12 


16 


81LS98 


Inverting octal buffer/driver with three- 


9.0 


16 




state output and two inverting enables 







DUAL DIFFERENTIAL 


Use With 


3603 


Receiver with differential input to detect 


751 10 




signals > 25mV. Three-state outputs. 




751 07B 


Totem-pole TTL output version of 


75109 or 




Am363 


751 10 


751 08B 


Open collector TTL output version of 


75109 or 




Am363 


/ Dl l u 


8820 


Designed for ±15V common mode 


8830 




using 5.0V supply 




8820A 


Higher speed, tighter spec 8820 


8830 


9615 


±15 volt common mode, 5 volt supply 


9614 




receivers with uncommitted collector 






and active pull-up controls 




9620 


± 1 5 volt common mode receiver with 


9621 




direct and attenuated inputs 




QUAD DIFFERENTIAL 




26LS33 


±15 volt common mode, 5 volt supply, 


26LS31 




three-state output 




QUAD DIFFERENTIAL EIA RS-422, 




FEDERAL STD 1020 




26LS32 


±7 volt common mode, 5 volt supply, 






three-state output 




SINGLE ENDED 




2615 


Receiver for 3 volt single-ended TTL 


2614 




level data 




SINGLE ENDED, EIA RS-232-C 




1489 


Quad EIA RS-232C receiver with input 


1488 




threshold hysteresis 




1489A 


Higher threshold version of Ami 489 


1488 


2617 


Quad EIA RS-232 receiver specified 


2616 




over military temperature range (same 






pinout as Am1489A) 




9617 


Triple EIA RS-232 receiver with 


9616 




adjustable hysteresis 




SINGLE ENDED, EIA RS-423, 




FEDERAL STD 1030 




26LS32 


±7 volt common mode, 5 volt supply, 


26LS29 




three-state output 


26LS30 



D 



tin devei 



lopment 



1-11 



SPECIAL FUNCTIONS 



SELECTION GUIDE (Cont.) 

MOS-MICROPROCESSOR INTERFACE CIRCUITS 



TIMERS 

555 
556 


Single, Precision oscillator/timer 
Dual version 555 


MOS MEMORY 


DRIVERS 

0026 
0056 


Dual 5MHz Two-Phase MOS clock driver 
0026 with added V BB terminal 


SENSE AMP 

3604 

75207 
75208 


JFIERS 

Differential input for signals > 10mV, Three-state 
outputs 

Totem-pole TTL output 3604 

Open-collector 3604 
I _ 1 



8080A/9080A 

8212 
8216 
8224 
8226 
8228 
8238 

8303B 
8304B 



8-Bit input/output port, with storage 

4-Bit parallel bidirectional bus driver 

Clock generator and driver 

Inverting version 821 6 

System controller and bus driver 

System controller and bus driver with extended 

IOW/MEMW 

Two 8226 s in one 20 pin package 
Two 8216 s in one 20 pin package 



BUS TRANSCEIVERS 





uurpui 


Fnnrtinn 
runcHon 


nybieresis. 


Speed 

rNntp 11 

(NOie lj 


LyOmmefiis 


UUAU 













Am26S10 


100mA-O.C. 


Inverting 


No 


20ns 


bN55/75138 pin Out 


Am26S1 1 


100mA-O.C. 


Non-Inverting to bus; 
Inverting off bus 


No 


22ns 


Same as Am26S10 except non-inverting to bus 


Am26S12 


100mA-O.C. 


Inverting 


Yes-0.6V 


32ns 


Same pin out as DS78/8838 and 8T38 


Am26S12A 


100mA-O.C. 


Inverting 


Yes-1.05V 


32ns 


Wider threshold Am26S12 


Am2905 


100mA-O.C. 


Inverting 


No 


31ns 
(Note 2) 


Has 2-input multiplexer 


Am2906 


100mA-O.C. 


Inverting 


No 


31ns 
(Note 2) 




Has 2-input multiplexer and parity 


Am2907 


100mA-O.C. 


Inverting 


No 


31ns 
(Note 2) 


Includes parity, 2.0V receiver V TH 


Am2908 


lOOmA-O.C. 


Inverting 


No 


31ns 
(Note 2) 


Includes parity, 1 ,5V receiver V TH 


Am2915A 


48mA/3-St. 


Inverting 


No 


31ns 
(Note 2) 


Has 2-input multiplexer 


Am2916A 


48rrW3-St. 


Inverting 


No 


31ns 
(Note 2) 


Has 2-input multiplexer and parity 


Am2917A 


48mA/3-St. 


Inverting 


No 


31ns 
(Note 2) 


Includes parity 


Am3216 


50mA/3-St. 


Non-Inverting 


No 


34ns 


Same as 8216 except different A.C. loading spec 


Am3226 


50mA/3-St. 


Inverting 


No 


30ns 


Same as 8216 except different A.C. loading spec 


Am3448A 


48mA/3-St.-O.C. 


Non-Inverting 


Yes 


32ns 


IEEE 488 compatible 


Am78/8838 


50mA-O.C. 


Inverting 


No 


38ns 


Same pin out and function as Am26S12A and 8T38 


Am8T26A 


48mA/3-St. 


Inverting 


No 


19ns 


Vqh MOS compatible 


Am8T28 


48mA/3-St. 


Non-Inverting 


No 


25ns 


V h MOS compatible 


Am8216 


50mA/3-St. 


Non-Inverting 


No 


34ns 


Similar to 8T28 


Am8226 


50mA/3-St. 


Non-Inverting 


No 


30ns 


Similar to 8T26A 


OCTAL 












Am8303B 


48mA/3-St. 


Inverting 


No 


14ns 


Same as two 8226 s in one 20 pin package 


Am8304B 


48mA/3-St. 


Non-Inverting 


No 


24ns 


Same as two 8216 s in one 20 pin package 



Notes: 1 . Typical delay at 28°C for input to bus plus receiver to output. 

2. Bus enable to bus plus bus to receiver output. All parts include register or driver plus receiver with latch. 



1-12 



SELECTION GUIDE (Cont.) 

MONOSTABLES (ONE SHOTS) 





Device No. 


Description 


Dual 


Retrig- 
gerable 


Reset 
Table 


Initial 
Accuracy 

% 


Min. 
Output 
t insl 


Pulse Width 
Variation (%) 
Temp. V cc 


Power 
Dissipation 
(mW tvD ) 


No. 
Package 
Leads 


Am2600 




t pw = 55ns to with guaranteed < \% 
chanqs over temperature range 


X 


X 


X 


±10 


45 


±0.5 


±1.5 


95 


14 


Am2602 




tpw = 55ns to with guaranteed < \% 
change over temperature range 


X 


X 


X 


±10 


45 


±0.5 


±1.5 


175 


16 


Am26L02 


Low-Power version 2602, t pw = 100ns to * 


X 


X 


X 


±10 


110 


±0.3 


± 1 .0 


50 


16 


Am26L123 


Low-Power version 26123, t pw = 120ns to * 


X 


X 


X 


±10 


120 


-*-0 3 


+ 1 


60 


16 


Am26S02 




High speed Schottky version 2602, t pw = 
28ns to M 


)( 


X 


x 


+ 5 


33 


±0.4 


±1.5 


240 


16 


Am26123 




tpw = 45ns to ^. with guaranteed < 1f% 
change over temperature range. Output 
stability latch improves noise immunity 


X 


X 


X 


±10 


45 


±0.5 


±0.5 


230 


16 


Am54/74123 


Same as 26123, except no output latch, 
no Atp w guarantee 


X 


X 


X 


±10 


45 


±2.7 


±1.0 


230 


16 


Am54/74221 


Schmitt-trigger input 


X 




X 


±7.0 


30 


±0.3 


±0.3 


130 


16 


Am9600 




Same as 2600. except no At pw guarantee 




X 


X 


±10 


50 


±1.5 


±1.5 


95 


14 


Am9601 




Non-resettable version of 9600, t pw = 55ns 

to « 




X 




±10 


45 


±2.7 


±1.0 


95 


14 


Am9602 




Same as 2602, except t pw = 60ns to », no 
At pw guarantee 


X 


X 


X 


±10 


50 


±1.5 


±1.5 


175 


16 


Am96L02 




Same as 26L02, except t pw guaranteed 
<1.6<Sf change over temperature range 


X 


X 


X 


±10 


110 


±0.3 


±0.5 


50 


16 



1-13 



INDUSTRY CROSS REFERENCE 



AMD* 


Fairchild 


Intel 


Motorola 


National 


Signetics 


Texas 
Instruments 



Manufacturer Identification Cross Reference 



AM ^ 



, or None 



None M.MC | DM, PS, LM ; 



SN 



Temperature Range Cross Reference 



Commercial 


C 


C 




14, 34, 86 


3, 86, 88 


NE, N 


72, 74, 75 


Military 


M 


M 


M 


1 5, 35, 96 


1,96,78 


SE, S 


52, 54, 55 



Package Cross Reference 



Hermetic DIP 


D 


D 


C, D 


L 


D 


F, I 


J 


Molded DIP 


P 


P 


P 


P 2 


N 


A, B 


N 


Mini-Molded DIP 


T 


T 




Pi 


N 


V 


P 


Flat Pack 


F 


F 




F 


F, W 


W. Q 


H, U, Z, W 


TO-5 Type Can 


H 


H 




G, R 


H 


DB, K, T 


L 


TO-8 Type Can 


G 






H 


G 







'The original manufacturers' part number and package code are used for second source devices. 



9614 



FAIRCHILD 

D 



FAIRCHILD (Cont.) 

556 D 



Device 




1 c 1 1 lptr 1 d [U 1 1? 


Type 


Type 


RsnQB 




AMD 


AMD 


Fairchild 


Direct 


Functional 




Replacement 


Replacement 


/nA101D 


LM101D 




/xA101H 


LM101H 




/U.A101AD 


LM101AD 




MA101AF 


LM101AF 




M A101AH 


LM101AH 




/iA102H 


LM102H 




/iA105H 


LM105H 




M107H 


LM107H 




/M108AH 


LM108AH 




M108H 


LM108H 




mAHOH 


LM110H 




/xA111H 


LM111H 




AA139D 


LM139D 




,*A1458H 


AM1458H 




JU.A1558H 


AM1558H 




/U.A201D 


LM201D 




,u.A201 H 


LM201H 




^A201AD 


LM201AD 




/iA201 AF 


LM201AF 




JU.A201AH 


LM201AH 




AtA207H 


LM207H 




/xA208H 


LM208H 




MA208AH 


LM208AH 




^A301AD 


LM301AD 




AiA301AH 


LM301AH 




/xA301 AN 


LM301AN 




/xA302H 


LM302H 




>xA305H 


LM305H 




HA305AH 


LM305AH 




MA307H 


LM307H 




MA308H 


LM308H 




/U.A308AH 


LM308AH 




fiA310H 


LM310H 




M A31 1 H 


LM311H 





Mfg.'s 
Ident. 



Device 
Type 



M 

L 



Type 



Temperature 
Range 





AMD 


AMD 


Fairchild 


Direct 


Functional 




Replacement 


Replacement 


MA31 1 P 


LM311N 




/xA339D 


LM339D 




^A339P 


LM339N 




/U.A715DC 


715DC 




/U.A715DM 


715DM 




(U.A715HC 


715HC 




/U.A715HM 


715HM 




/tA723DC 


723DC 




M.A723DM 


723DM 




^A723HC 


723HC 




ju.A723HM 


723HM 




M.A725HC 


725HC 




ju,A725HM 


725HM 




,u.A725PC 


725CN 




/iA733DC 


733DC 




ju.A733DM 


733DM 




,uA733FM 


733FM 




(ixA733HC 


733HC 




JU.A733HM 


733HM 




ju.A741 DC 


741 DC 




MA741 DM 


741 DM 




(U.A741 FM 


741 FM 




(U.A741HC 


741 HC 




/iA741 HM 


741 HM 




/U.A741 ADM 


741 ADM 




/xA741 AFM 


741 AFM 




fiA741 AHM 


741 AHM 




^A741 EDC 


741 EDC 




/xA741 EHC 


741 EHC 




/xA747DC 


747DC 




/xA747DM 


747DM 




AiA747HC 


747HC 




(U.A747HM 


747HM 




,xA747PC 


747PC 





1-14 



FAIRCHILD (Cont.) 



FAIRCHILD (Cont.) 







AMD 


AMD 


Fairchild 


Direct 


Functional 






Replacement 


Replacement 


//A747ADM 


7/17AnM 
/4/ AUM 




^A7 


47AHM 


/ 4/Anivl 




lxA7 


47EDC 


/ 4 / cuu 




fiA7 


47EHC 


747FHP 
/ 4/ cnij 




liM 


48DC 


/ 40UO 




MA7 


48DM 


/ 40UIVI 




fxA7 


48FM 


748FM 

/ 'tor ivi 




/xA7 


48HC 


/ tOrHj 




/J.A7 


48HM 


7AOUM 

/ ton ivi 




AtA748PC 


748PC 




AiA760DC 




HIVIOOOUO 


/tA760DM 




MIVIOOOUIVI 


uA760HC 

J_c/o / \J\Jl 1 




rtiviooono 


AtA760HM 




AMbobnlvl 


/X A775DM 


LMloyU 




ju.A775DC 


LMoOaU 




u.A7Ti PC 


1 hAQOQM 
LMooyiN 




5412TDM 


CMC/H oo 1 

blNb41 £jj 




541 ?TFM 


blNb41 2oW 




DO 1 U / MU IVI 


bNbbl U/bJ 




kki n7RnM 


bNbbl 07BJ 




cci H7AFM 

jj 1 U / r\\ IVI 


bN5b107bW 




OO 1 U/Drlvl 


bNbbl U7BW 




SRI ORADM 


bNbbl UobJ 




I uonr ivl 


bNbbl UobW 




551 flffRnM 


bN55108BJ 




551 DftRFM 


bNbbl UobW 




551 fiQDM 


bNbbl Liyj 




■J\J 1 U3l IVI 


bNboi uyw 




jj i i \j vj rvi 


bNbbl 1 UJ 




551 10FM 


bNbbl 1 UW 




5520DM 


bNbb2UJ 




5521 DM 

JJl 1 Lri/IW 


bNob21 J 




OOtOH-L/IVI 


CKtr COO >l 1 

bNbb234J 




55234FM 


bNob2o4W 




552T5DM 


SN55235J 




55235FM 


PKirr OO CIA/ 

bN55235W 




J JcJUL/IVI 


bNbb238J 




55238FM 


bNb5238W 






OMCCOOO 1 

bNbb^oyj 




55239FM 


bNbb2oyw 




5524DM 


CMCC *~i A 1 

bNbb*:4J 




5525DM 


CMCCoc | 

bNbb^bJ 




55325DM 


bNbbo^ioJ 




55325FM 


bNobo^bW 




741 23 DC 


CM7/IH Oo 1 

bN74123J 




74123PC 


SN74123N 




75107ADC 


CM7C1A7D 1 
oN /bl U/bJ 




75107APC 


bN75107BN 




75107BDC 


OM7C 1 A~7Q I 

bN /bl U/bJ 




75107BPC 


bN75107BN 




75108ADC 


OM7C H fiOD I 

bN /bl UobJ 




75108APC 


bN75108BN 




75108BDC 


SN75108BJ 




75108BPC 


SN75108BN 




75109DC 


SN75109J 




75109PC 


SN75109N 




75110DC 


SN75110J 




75110PC 


SN75110N 







AMD 


AMD 


Fairchild 


Direct 


Functional 




Replacement 


Replacement 


youuub 


ybuuuu 




youuuivi 


y ouuuivi 




ybUUrlvl 


ybUUrM 




yoUUrL- 


ybuuru 




you i 


ybui uu 




you i uivi 


ybu i uivi 




you i riyi 


ybUl rlvl 




you 1 r o 


you 1 r o 




ybu^uo 


you^uo 




youuuivi 


you^uivi 




you^rivi 


youtr (VI 




you^ru 


ybu^ro 




yoLU<iuo 


ybLU^uo 




yoLU^uivi 


ybLU^UM 




oci nocK/i 
yoLU<irM 


ybLU<irtVI 




yoLU^rL- 


ybLU^rU 




yobu2uu 




AM26b02UL/ 


ybbU^rL- 






961400 


961 4U0 




ybi 4UM 


9bl 4UM 




9o1 4rM 


961 4FM 




9614PG 


961 4PC 




961 5DC 


961 5DC 




ybl bUWI 


9b1 bUM 




9b1 orlvl 


961 5FM 




ybl bPU 


nc A C DO 

ybl ort 




yb 1 bUU 


ybl bULi 




ybl oUM 


ybl bUM 




yb ibtuC' 


yblbbUL- 




yo I Dtrb 


yo t ocru 




yb i or ivi 


yo I OrlVI 




yb i or o 


QCH ODO 

yo i oro 




yo i / 


Qfii 7nr 
yo i / 




QC1 7DP 

ybi / rU 


Qftl 7DP 

ybi /ru 




9634PC 




A KJIOCI OOH DO 

AM26Lb31 PC 


9634DC 




AlVf26Lb31 DC 


9bo4L)lvl 




AIvi<ibLboi Uivi 


ybobrL. 




AMiibLboorC 


ybobUL- 




A KA OC I CQTHP 

AM^ibLboJUC 


ybobUM 




A lioci C3TPlhA 

A (vl b L b o o U IV) 


ybobrO 




AM^bLboUKC 


ybobuu 




AlVI^DLbOUUO 


ybobuivi 




AlvltbLboUUlVl 


OC07DP 




AM^bLbOiifrC 


OCQ7Hr^ 

ybo/uu 




A Pi j1 OC 1 COO DjO 

AMiibLbo^UC 


ybo/uivi 




A IVI CXi Lb O £1 U IVI 


QCOODP 

yboorU 




AKXO£l OOODO 

AM^bLbJ^rC 


ybooUL. 




AM^bLbOiiUC 


ybooUM 




a iioci coor\fcji 
Alvl^bLbo^Ufvl 


yb4uuu 


AM^bbl UUU 




9640UM 


AM26b10DM 




yb4UrO 


Alvl^bbl UrU 




9641 DC 


AM26S1 1 DC 




9641 DM 


AM26S1 1 DM 




9641 PC 


AM26S11PC 




9642PC 




AM26S12APC 


9642DC 




AM26S12ADC 


9642 DM 




AM26S12ADM 



1-15 



INTEL 



U 



D8228 



MOTOROLA (Cont.) 



Temperature 


Package 






Device 


Range 


Type 






Type 




AMD 






AMD 


Intel 


Direct 
Replacement 






Functional 
Replacement 


D3212 


D3212 








MD3212 


MD3212 








P3212 


P3212 








D3216 


D3216 






N8T28F 


MD3216 


MD3216 






S8T28F 


P3216 


P3216 






N8T28B 


D3226 


D3226 






N8T26F 


MD3226 


MD3226 






S8T26F 


P3226 


P3226 






N8T26B 


D8212 


D8212 








MD8212 


AM8212DM 








P8212 


AM8212PC 








D8216 


D8216 






N8T28F 


MD8216 


MD8216 






S8T28F 


P8216 


P8216 






N8T28B 


D8224 


D8224 








MD8224 


AM8224DM 








P8224 


AM8224PC 








D8226 


D8226 
MD8226 






N8T26F 
MD8226 


S8T26F 


P8226 






P8226 


N8T26B 


D8228 






D8228 


MD8228 


AM8228DM 








P8228 


AM8228PC 


















MD8238 


AM8238DM 








P8238 
D8286 


AM8238PC 
DP8304BJ 








P3287 


DP8304BN 








D8287 


DP8303BJ 








P8287 


DP8303BN 










MOTOROLA 








MC 14 








88 L 


I I 








I I 


Mfg.'s Temperature 


Device 


Package 


Ident. 


Range 


Type 


Type 




AMD 






AMD 


Motorola 


Direct 
Replacement 






Functional 
Replacement 


MC1408L6 


AM1408L6 








MC1408L7 


AM1408L7 








MC1408L8 


AM1408L8 








MC1458G 


AM1458H 








MC1488L 


MC1488L 








MC1488P 


AM1488PC 








MC1489L 


MC1489L 








MC1489P 


AM1489PC 








MC1489AL 


MC1489AL 








MC1489AP 


AM1489APC 








MC1508L8 


AM1508L8 








MC1558G 


AM1558H 








MC1723CG 


723HC 








MC1723CL 


723DC 








MC1723G 


723HM 








MC1723L 


723DM 








MC1733CG 


733HC 








MC1733CL 


733DC 











AMD 


AMD 


Motorola 


Direct 


Functional 




Replacement 


Replacement 


MC1733F 


733 FM 




MC1733G 


733HM 




MC1733L 


733DM 




MC1741CG 


741 HC 




MC1741CL 


741 DC 




MC1741F 


741 FM 




MC1741G 


741 HM 




MC1741L 


741 DM 




MC1747CG 


747HC 




MC1747CL 


747DC 




MC1747G 


747HM 




MC1747L 


747DM 




MC1748CG 


748HC 




MC1748G 


748HM 




MC26S10L 


AM26S10DC 




MC26S10P 


AM26S10PC 




MC3438L 




AM26S12ADC 


MC3438P 




AM26S12APC 


MC3443L 




AM26S10DC 


MC3443P 




AM26S10PC 


MC3448AL 


MC3448AL 




MC3448AP 


MC3448AP 




MC3456L 


NE556F 




MC3456P 


NE556A 




MC3486L 




AM26LS31 DC 


MC3486P 




AM26LS31 PC 


MC3487L 




AM26LS32DC 


MC3487P 




AM26LS32PC 


MC3556L 


SE556F 




MC55107L 


SN55107BJ 




MC55108L 


SN55108BJ 




MC55109L 


SN55109J 




MC55110L 


SN55110J 




MC5524L 


SN5524J 




MC5525L 


SN5525J 




MC55325L 


SN55325J 




MC75107L 


SN75107BJ 




MC75107P 


SN75107BN 




MC75108L 


SN75108BJ 




MC75108P 


SN75108BN 




MC75109L 


SN75109J 




MC75109P 


SN75109N 




MC75110L 


SN75110J 




MC75110P 


SN75110N 




MC8T26L 


N8T26F 




MC8T26P 


N8T26B 




MC8601 L 


9601 DC 




MC8601 P 


9601 PC 




MC8602L 


9602DC 


AM2602DC 


MC8602P 


9602PC 


AM2602PC 


MC9601L 


9601 DM 




MC9602L 


9602DM 


AM2602DM 


MLM101 AG 


LM101AH 




MLM105G 


LM105H 




MLM107G 


LM107H 




MLM110G 


LM110H 




MLM111F 


LM111F 




MLM111G 


LM111H 




MLM111L 


LM111D 




MLM201 AG 


LM210AH 




MLM205G 


LM205H 




MLM207G 


LM207H 




MLM210G 


LM210H 




MLM211G 


LM211H 





1-16 







MOTOROLA (Com.) 






NATIONAL (Cont.) 






AMD 


AMD 






AMD 


AMD 


Motorola 


Direct 


Functional 




National 


Direct 


Functional 






Replacement 


Replacement 






Replacement 


Replacement 


MLM211L 


LM211D 






DS0056CG 


DSOOooCU 




MLM301AG 


LM301AH 






DS0056CH 


DS0056CH 




MLM 


301API 


LM301 AN 






DS0056CJ 


DS0056CJ 




MLM305G 


LM305H . 






DS0056CN 


DS0056CN 




MLM307G 


LM307H 






DS0056G 


Db0056b 




MLM310G 


LM310H 






DS0056H 


Db0056H 




MLM311G 


LM311H 






DS0056J 


DS0056J 




MLM211PI 


LM311N 






DS1488J 


MC1488L 




MLM311L 


LM311D 






DS1488N 


AM1488PC 




MMH0026CG 


MH0026CH 






DS1489J 


MC1489L 




MMH 


0026CL 


MMH0026CL 






DS1489N 


AM1489L 




MMH 


0026CPI 


MH0026CN 






DS1489AJ 


MC1489AL 




MMH0026G 


MH0026H 






DS1489AN 


AM1489APC 




MMH 


0026L 


MMH0026L 






DS1691J 


AM26LS30DM 














DS1692J 


DS1692J 


















NATIONAL 




r\QQRQ1 1 

uoooy i j 








DS 78 
I I 


20 J 

I >\ 


DS3691N 
DS3692J 
DS3692N 


AM26LS30PC 

DS3692J 

DS3692J 




Mfg.'s 


Temperature Device Package 


DS3692N 


DS3692N 




Ident. 




Range Type Type 


DS7820J 


DM7820J 




National 


AMD 

Functional 
Replacement 


AMD 

Direct 
Replacement 




DS7820AJ 
DS7830J 
DS7831J 
DS7832J 


DM7820AJ 
DM7830J 
DM7831J 
DM7832J 
















WIVIJt 1 


SN54123J 






DS7835J 




S8T26F 


UIVIO^ I £G VV 


SN54123W 






DS7838J 


DS7838J 


AM26S12ADM 


UIVIO'tL I eijj 




AM26L123DM 




DS8820J 


DM8820J 








AM26L123FM 




DS8820N 


DM8820N 




DM71 LS95J 


DM71LS95J 


SN54LS241 J 




DS8820AJ 


DM8820AJ 




DM71LS96J 


DM71LS96J 


SN54LS240J 




DS8820AN 


DM8820AN 




DM71LS97J 


DM71LS97J 


SN54LS244J 




DS8830J 


DM8830J 




DM71LS98J 


DM71LS98J 


SN54LS240J 




DS8830N 


DM8830N 




DM74L123J 




AM26L123DC 




DS8831J 


DM8831J 




DM74L123N 




AM26L123PC 




DS8831N 


DM8831 N 




DM741 23 J 


SN74123J 


AM26123DC 




DS8832J 


DM8832J 




DM741 23N 


SN74123N 


AM26123PC 




DS8832N 


DM8832N 




DM81 LS95J 


DM81 LS95J 


SN74LS240J 




DS8835J 




N8T26F 


DM81LS95N 


DM81LS95N 


SN74LS240N 




DS8835N 




N8T26B 


DM81LS96J 


DM81 LS96J 


SN74LS241J 




DS8838J 


DS8838J 


AM26S12ADC 


DM81 LS96N 


DM81LS96N 


SN74LS241N 




DS8838N 


DS8838N 


AM26S12APC 


DM81LS97J 


DM81LS97J 


SN74LS241J 




DS55107J 


SN55107BJ 




DM81LS97N 


DM81LS97N 


SN74LS241N 




DS55108J 


SN55108BJ 




DM81LS98J 


DM81LS98J 


SN74LS240J 




DS55109J 


SN55109J 




DM81LS98N 


DM81LS98N 


SN74LS240N 




DS55110J 


SN55110J 




DM8601 J 


9601 DC 






DS75107J 


SN75107BJ 




DM8601 N 


9601 PC 






DS75107N 


SN75107BN 




DM8602J 


9602DC 


AM2602DC 




DS75108J 


SN75108BJ 




DM8602N 


9602PC 


AM2602PC 




DS75108N 


SN75108BN 




DM9601J 


9601 DM 






DS75109J 


SN75109J 




DM9601 W 


9601 FM 






DS75109N 


SN75109N 




DM9602J 


9602DM 


AM2602DM 




DS75110J 


SN75110J 




DM9602W 


9602FM 


AM2602FM 




DS75110N 


SN75110N 




DP7303BJ 


DP7304BJ 






LF155H 


LF155H 




DP8303BJ 


DP8303BJ 






LF155AH 


LF155AH 




DP8304BJ 


DP8304BJ 






LF156H 


LF156H 




DS0026CG 


MH0026CG 






LF156AH 


LF156AH 




DS0026CH 


MH0026CH 






LF157H 


LF157H 




DS0026CJ 


MMH0026CL 






LF157AH 


LF157AH 




DS0026CN 


MH0026CN 






LF198H 


LF198H 




DS0026F 


DS0026F 






LF255H 


LF255H 




DS0026G 


MH0026G 






LF256H 


LF256H 




DS0026H 


MH0026H 






LF257H 


LF257H 




DS0026J 


MMH0026L 






LF298H 


LF298H 





1-17 



NATIONAL (Cont.) 



NATIONAL (Cont.) 





AMD 


AMD 


National 


Direct 


Functional 




Replacement 


Replacement 


1 COCCU 

LrOOOn 


1 C-3CCU 

Lrooon 




LF355N 


LlOJJ 1 "J 




LF3SSAH 


1 F^^^AH 

LiOJJnl 1 




LrOOon 


Lrooon 






LroooiM 




LrOODnn 


i ft^rah 

LrOODnn 




LF357H 


LF357H 




LF357N 


LF357N 




1 F*3S7AH 


1 F'^ c ;7AH 




LF39RH 


1 F9QRH 




LH21Q1AD J 


1 H91 m An 

LI \C I \J 1 nU 




1 FP101 AF 


1 HP1 01 AF 

Ln£ iu inr 




LF2111D J 


LH21 1 1 D 




LH21 1 1 F 


LH21 1 1 F 




I HPP01AD I 

LI 1 C C-\J 1 rAL/, U 


I H9901 An 

L n Cc.\J I ML* 




1 H.990.1 AF 

LmllU 1 Mr 


I H9901 AF 




l_ 1 \ l—t— 1 IJ, J 


LH221 1 D 




LH221 1 F 


I H991 1 F 

\-\\£.tL i i r 




I HP^m An I 

LFlitiOU IMU, 


i H9om a n 

Lr1*i0U 1 nU 




I M901 1 n I 
Ln^O I IU, J 


i M901 1 n 
Lri£.o I i u 




i mi m n i 

L IVM U I L- . J 


i mi m n 

LIVI I U I U 




I mi m f 

L IVI I U I i 


l i vi i u l r 




I mi ni m 
l m i u i n 


i m 1 m li 

LIVI 1 Urn 




i hiii m ar i 

LIVIIUI MU, 


i Mi m a n 

LIVI I U 1 Mu 




L IVI iU IMr 


i mi m a p 

LIVI I U I Mr 




I m 1 n 1 a m 
l ivi i u iwn 


I M1 m A LI 
LIVI I U I An 




i Minor* i 

L IVI 1 \Jc\J, J 


i k a 1 non 




I mi nop 

L IVI 1 \Jc-\ 


livi i u*ir 




l ivi i \jc. n 


i MmoM 
livi i u^n 




l ivi I uor 


! M1 n^F 
l ivi i uor 




i MinciM 
l ivi i uon 


Livi I Uon 




l ivi i uor 


I MmfiP 
Livi I uor 




I MinRUI 

l ivi i uon 


i MincLi 
LM1 Uon 




i Mmvn i 

L IVI 1 U / U , J 


i Min7n 

L IVI 1 U / U 




1 Ml 07F 

L IVI lU/r 


l ivi i u / r 




1 Ml n7H 

l ivi i u i n 


I M107H 

livi i u / n 




I MmRn l 

L!VI I UOU, J 


i Mmon 
LIVI I uou 




livi i uor 


I M 1 flQF 

LM I uor 




i Mmou 
lm i uon 


I MmQU 

LM i Uon 




LIVI 1 UOMU, J 


i mi no a n 

L M I UOM U 




1 M1C1RAF 
L IVI I UOnr 


I MmRAF 
LIVI 1 UOMr 




| Ml rift A H 
L IVI 1 UOMn 


1 M1 no A LI 
LM I UOMn 




I mi 1 nn i 

LIVI I I UU, J 


i mi 1 nn 

LM I I UU 




I M1 1 AF 
l ivi i i ur 


i mi i np 
L M 1 i u r 




I M1 1DH 
l ivi i i un 


I mi 1 nw 
livi i i un 




I M1 1 1 n I 

L IVI I I I U, J 


i m 1 1 1 n 

LIVI I I I U 




I Ml 1 1 F 
livi i i i r 


I Ml 11 F 

livi i i i r 




LM1 1 1 H 


I M 1 1 1 M 

livi i i in 




i mi 1 on i 

L IVI I I tU, J 


i mi 1 on 

L M I I c. U 




LM1 12F 


I Mi 1 OF 
LIVI I \c.\ 




I Ml 1 OM 
LIVI I I c.\\ 


I M 1 1 OU-I 
LM I I 




i mi i Qn i 

L IVI 1 1 O U , 


i mi 1 an 

L M I I U 




1 Mil DC 

l ivi i i or 


I M1 1 QF 

lm l i or 




I Ml 1 QU 

l ivi i ion 


1 M1 1 Q W 
LM I I On 




t m 1 1 q n i 


I M 1 1 on 

lm 1 1 yu 




LM1 i yr 


LM1 19F 




I M1 1 QU 

LM i i yn 


LMi 1 9n 




LM124U, J 


LM124D 




LM124F 


LM124F 




LM139D, J 


LM139D 




LM139AD, J 


LM139AD 




LM139F 


LM139F 




LM139AF 


LM139AF 




LM148D 

I 1 


LM148D 







AMD 


AMD 


National 


Direct 


Functional 




Replacement 


Replacement 


i Mi4Qn 

l_ IVI 1 t3U 


I M14QP1 

LIVI I tcJU 




LM201H 


LM201H 

L 1 VI 1 I 1 




LMP01AD I 


1 MP01 AH 

LIVIOU I ML* 




1 M9D1 AF 
l \v\c.\j i Mr 


I MP01 AF 

LIVIOU I MT 




1 M9fl1 AH 

L IVI^LU I Mn 


I Mom AM 

LIVIOU I Mn 




I M?D?H 


I M9fl9H 
Livi^iu^n 




LM205H 


I M20SH 




LM206H 


I MOOfiH 

l_IVI£HJUI 1 




i Mporn i 






LM207F 


1 M?fl7F 






1 IWl?n7H 
i- ivitxj i n 




1 M?0.RAn 1 

i- IVI L.UO/A L-/ « O 


L IVIiHUOM YJ 




l_ 1 V 1 £L\J\Jr \ I 


L IVI^lUOMr 




1 MPDftAH 

L IVI^lUOrAn 


L IVIOUOMn 




1 Monon 1 

LIVIdlUOL/, <J 


i Mpfifin 

LIVI^UOU 




1 MOOftF 


l iviouor 




1 MonQH 
l ivi^uon 


l ivi^iuon 




1 ^ylo1^In i 

L IVIt 1 UU, J 


L IVI*l 1 UU 




I Momu 
Livi*i i un 


i ^^o1 nn 
livi^i i un 




i moi 1 n i 

LIVI^l I I U, J 


i moi 1 n 

LIVIil I I u 




LM21 1 F 


I MOI 1 P 

Livi*; i i r 




I MOI 1 LI 

l m^ 1 1 n 


I MOI 1 LI 

Llvltl 1 rl 




i moi on i 


i ^/l01 on 




LM21 2F 


I \AO-i OP 
LlVlf; I £V 




I MQ1 Oi-I 
L IVI^i I d.v\ 


I MOI OLI 




L IVI*; 1 OU, J 


i MoifiAn 

LM^i I OmU 




1 M91RAF 
L IV|£ I Dnr 


I M91KAF 
L IVI^i I dm r 




I MOI CAM 
l ivic i OMn 


I M91RAH 
L IVI*i I Dnn 




| Moifin 1 
L lVl£l 1 OU, J 


I KAOIRn 
LIVI^i 1 OU 




l ivi^ i or 


Livit i or 




I MOI cu 

l ivi^ i on 


Livii^ i on 




l moi on i 

L IVI^l 1 OU, J 


i \ao-\ on 

LIVl<; 1 OU 




1 M01 ftP 

l ivi*; i or 


1 M91 OP 
LIVI^i I Or 




I M91 ftM 

livi*i i on 


I M91 PM 
LIVI^l I on 




I on i 
Livi£ i yu, j 


i KAOi on 
Livi*; i yu 




I MOI QP 

livi*i i yr 


I MOI OP 

LMti yr 




I M91 QM 

l ivi*; i an 


I KAOi QM 

livi^i i yn 




I MooAn i 

LIVl£i;*+U, J 


LM^^i^f U 




1 MOQQH 1 

Livii^oyu. j 


i Mooan 
LM^oyu 




i ^>!o^QAn i 

LIVI^OaMU, J 


I Mooon 
Livi^oyu 




LIVI^M-OU 


I \AOARD 
LIVIil'fOU 




1 MOAQn 

Livici'tyu 


i Motion 
Livii;4yu 




I M^m An i 

LIVIOU 1 MU, J 


i Mo.ni An 

LIVIOU I MU 




1 M9fl1 AF 
liviou i Mr 


I M^m ap 

LIVIOU I MT 




I M9fl1 AM 
LIVIOU I Mn 


I Mo,m AM 
LIVIOU I Mn 




I M^m AM 

LIVIOU I MIN 


I M^fl1 AM 

LIVIOU I MIN 




l iviou^ir 


I M^nop 
l iviouor 




l iviou<in 


Liviouon 




l iviouor 


I Mon^F 
Liviouor 




I M^n^M 
Liviouon 


Liviouon 




i Mft.rmAH 

L IVIOUOMn 


I MOOLAH 
LIVIOUOMn 




l iviouor 


Liviouor 




Liviouon 


I MOnfiM 

Liviouon 




L IVIOU / U, J 


i Mon7n 

LIVIOU / u 




I M^n7F 

liviou / r 


I K>ion7P 
lmou / r 




I MO.n7M 

liviou / n 


1 MOn7LI 

LMOU / n 




i KJio.no An i 

LMOUOMU, 


i Mono a n 

LMoUomU 




I MOnftAP 
LIVIOUOMr 


1 MOnQAP 
LMOUOMr 




LM308AH 


LM308AH 




LM308AN 


LM308AN 




LM308D, J 


LM308D 




LM308F 


LM308F 




LM308H 


LM308H 




LM308N 


LM308N 





1-18 



NATIONAL (Cont.) 



SIGNETICS 





AMD 


AMD 


National 


Direct 


Functional 




Replacement 


Replacement 


LM310D, J 


LM310D 




LM310F 


LM310F 




LM310H 


LM310H 

F— 1 V 1 O 1 Ul 1 




LM310N 


LM310N 




LM311D, J 


LM311D 




LM311F 


LM311F 




LM311N 


LM311N 

I — ivio I i 1 1 




LM312D J 


LM312D 

LIVIO 1 C- \—* 




LM312F 


LM312F 




LM312H 


LM312H 

I— IVIO 1^1 1 




LM316AD, J 


LM316AD 

livio i unu 




LM316AF 


LM316AF 

l i vio i un i 




LM316AH 


1 M31fiAH 

LIVIO 1 \Jr \ 1 I 




LM316D, J 


LM316D 

l_ I v I I U I—/ 




LM316F 


LM316F 

1— I v 1 O 1 \J \ 




LM316H 

I— I V rO lull 


1 MT1RH 
livio iun 




LM318D, J 


l— I V I O 1 \J L> 




I M^1RF 

L_ IVIO 1 O 1 


1 M^lflF 
livio i or 




L 1 VIO 1 CJ 1 1 


L IVIO I O II 




L 1 VIO 1 O 1 N 


I M^1RM 

LIVIO 1 Ol V 




! M31QH 

l_ I V I O I I 


LIVIO I 3m 




LM319D J 

LIVIO 1 O IS , u 


LIVIO I ol_/ 




LM319N 

l_ I V I O 1 J 1 1 


LiVIO lali 




LM324D J 


I M??4D 




LM324N 


I M3P4N 

t— ! V I JC^ 1 N 




1 MT^QD 1 


LIV1O0C7L/ 




1— 1 V 1 JO rAI— f , O 


1 M^QAn 

L IvIOOcJrA \-i 




LM339N 


1 M^QN 

LlvloOol H 




LM339AN 


L 1 VUO?AI v 




1 M34RD 


1 1 VI 0"0 L/ 




1 M?4RN 

LIVIO*tOIN 


1 M^ARNl 

LIVIO*+OI > 




l— 1 VIO*T^ L/ 


LIVIOtlJL' 




1 M^4QN 


LIVIO^ol N 




LM723D, J 


723 DM 




l_ 1 VI 1 C-<J \ 1 


723 HM 






723 DC 




LM723CH 


723HC 




LM725H 


725HM 




LM725CH 

L_ IVI / 1 


725HC 




LM725CN 

1 — IVI/ tlO V_y 1 


725CN 




L M72SD 1 


725 DM 




l M72"5f;D 1 


725 DC 




1— IVI / JOU, o 


733DM 




livi / oon 


/ oon ivi 




1 — IVI / OOUL/, O 


733 DC 




i— i vi / oo*_/n 


733HC 




1 M741D I 

LIVI / *T 1 <lJ , U 


741 DM 




LM741 F 


741 FM 




LM741 H 


741 HM 




L IVI r *-r 1 vL/, U 


741 DC 




1 M741PF 
livi/ *f lor 


741 FC 




I M741PH 


741 HC 




I M747D I 

LIVI l Hf L/, J 


747DM 




LM747H 


747 HM 




LM747F 


747 FM 




1 IU17A7PH 1 


7A7nP 






{ *+/ rLy 




LIVI / *+/ LyPI 


7A7WP 




LM747CN 


747 PC 




LM478H 


748HM 




LM748CH 


748HC 




LM748CN 


748PC 




LM1458H 


AM1458H 




LM1558H 


AM1558H 





NE 



555 



Temperature 


Device 


Package 


Range 


Type 


Type 




AMD 


AMD 


Signetics 


Direct 


Functional 




Replacement 


Replacement 


LM101F 


LM101D 




LM101T 


LM101H 




LM101AF 


LM101AD 




LM101 AT 


LM101AH 




LM107F 


LM107D 




LM107T 


LM107H 




LM108F 


LM108D 




LM108T 


LM108H 




LM108AF 


LM108AD 




LM108AT 


LM108AH 




LM111F 


LM111D 




LM111T 


LM111H 




LM119H 


LM119H 




LM119D 


LM119D 




LM124F 


LM124D 




LM139F 


LM139D 




LM201T 


LM301H 




LM201AF 


LM201AD 




LM201AT 


LM201AH 




LM201AV 


LM201AN 




LM207F 


LM207D 




LM207T 


LM207H 




LM208F 


LM208D 




LM208T 


LM208H 




LM208AF 


LM208AD 




LM208AT 


LM208AH 




LM211F 


LM211D 




LM211T 


LM211H 




LM219H 


LM219H 




LM219D 


LM219D 




LM224F 


LM224D 




LM239F 


LM239D 




LM301AT 


LM301AH 




LM301AV 


LM301AN 




LM307F 


LM307D 




LM307T 


LM307H 




LM308F 


LM308D 




LM308T 


LM308H 




LM308V 


LM308N 




LM308AF 


LM308AD 




LM308AT 


LM308AH 




LM311F 


LM311D 




LM311T 


LM311H 




LM311V 


LM311N 




LM319H 


LM319H 




LM319D 


LM319D 




LM319A 


LM319N 




LM324A 


LM324N 




LM324F 


LM324D 




LM339A 


LM339N 




LM339F 


LM339D 




MC1488F 


MC1488L 




MC1489F 


MC1489L 




MU1489AF 


ft a /"* -* a on A 1 

MC1489AL 




NE529K 




AM686HC 


NE592K 


AM592HC 




N74123B 


SN74123N 




N74123F 


SN74123J 




N74221B 


SN74221N 




N74221F 


SN74221J 





1-19 



SIGNETICS (Cont.) 



TEXAS INSTRUMENTS (Cont.) 





AMD 


AMD 


Signetics 


Direct 


Functional 




Replacement 


Replacement 


N8T22A 


9601 PC 




N8T22F 


9601 DC 




N8T26B 


N8T26B 




N8T26F 


N8T26F 




N8T26AB 


N8T26AB 




N8T26AF 


N8T26AF 




N8T28B 


N8T28B 




N8T28F 


N8T28F 




N8T38B 




DS8838N 


N8T38F 




DS8838J 


N9602B 


9602PC 




N9602F 


9602DC 




SE529K 




AM686HM 


SE555T 


SE555T 




SE556F 


SE556F 




SE592A 


AM592PC 




SE592K 


AM592HM 




S541 23F 

O 0*T 1 <L O 1 


SN54123 I 

O IUt [ £.00 




S 54221 F 


SN54221 J 




S9602F 


9602DM 




S8T26F 


S8T26F 




S8T26AF 


S8T26AF 




S8T28F 


S8T28F 




S8T38F 




DS7838J 


jxA723CF 


723DC 




^A723CL 


723HC 




/n723F 


723 DM 




^A723L 


723HM 




/iA733CA 


733PC 




/J.A733CF 


733DC 




/J.A733CK 


733HC 




f*A733F 


733DM 




M A733K 


733HM 




/iA741CF 


741 DC 




/xA741CT 


741 HC 




/U.A741 F 


741 DM 




iitA741T 


741 HM 




/xA747CA 


747PC 




juA747CF 


747DC 




M A747CK 


747HC 




MA747F 


747DM 




MA747K 


747HM 




AtA748CT 


748HC 




MA748F 


748DM 




/xA748T 


748HM 

I 





TEXAS INSTRUMENTS 

SN 75 110 N 

I I I I 

Mfg.'s Temperature Device Package 

Ident. Range Type Type 





AMD 


AMD 


Texas 


Direct 


Functional 


Instruments 


Replacement 


Replacement 


SN52101AJ 


LM101AD 




SN52101AL 


LM101AH 




SN52101AZ 


LM101AF 




SN52105L 


LM105H 




SN52106FA 


LM106F 




SN52106L 


LM106H 




SN52107J 


LM107D 




SN52107L 


LM107H 





Texas 

Instruments 


AMD 

Direct 
Replacement 


AMD 
Functional 
Replacement 


SN52107Z 


LM107F 




SN52108AFA 


LM108AF 




SN52108AJA 


LM108AD 




SN52108AL 


LM108AH 




SN521 08FA 


LM108F 




SN52108JA 


LM108D 

l— I V 1 1 UUL/ 




SN52108L 

Wlivt 1 ^OOI_ 


LM108H 

1— IV 1 1 UUI 1 




QN521 1 1 FA 


LM1 1 1 F 




SN521 1 1 1 

ul ~i-JC 1 1 1 O 


LM111D 

1 — 1 VI 1 1 1 VJ 




SN521 1 1 L 

O 1 IOC 1 1 1 l_ 


LM1 1 1 H 




SN52118FA 


LM1 18F 




SN52118JA 


LM1 18D 

1— IVI 1 1 \J \J 




SN521 18L 


LM118H 




SN 52723 1 


723 DM 




SN 52723 L 


723 HM 




SN52733FA 


733FM 






/ OO \-l IVI 




QMCOTQQI 
O 1 i Ji- ' JO l_ 


/ 00 ri ivi 




OliOc/ *+ 1 l M 


741 FM 




c lN c i?741 IA 


741 DM 






741 HM 
/ 1 1 nivi 




QNRP747FA 


747 FM 




QKIR9747 I A 


747DM 




CMCO747I 


747HM 




uiuc / torn 


748FM 




^NIR?74R IA 


748 DM 




SN5P74RI 


748 HM 




Oil JtL 1 LJJ 




AM26I 123DM 

n IVIL.UL 1 CO UJ 1 V 1 


RN54I 1?1W 




AM26L123FM 

/\ 1 v 1 C-0 1 — 1 4— 1 ivi 


CI QO I 

OI'JJHLO 1 £JJ 


QMC41 oipqi 


MIVIiCOLO iconivi 


OlNOtLO ItOVV 


^W54l ^19?W 


nivi^jLO 1 ivi 


QMC41 qp4n 1 


Ol iO*tLOt.*tUiJ 


n 1 V 1 O LOt*tUL/llrl 


1 1 JtLOtt 1 <J 


Ol 1 J" l— O c~^* 1 U 


AM?5I 9?41 DM 
nivicJLOct 1 L-zivi 




CMC41 Qp4p 1 


nlVlfcJLO^H^L'IVl 


CMC41 Cp4Q 1 


^N54l *^C>4T 1 


rAIVICOl— OC*+Ol— 'IVI 


9NR4I ^944 1 

Oil JtLOttt J 


1 lO"LOc."HJ 


AMP^I c ;P44nM 

niVICOLOCT^ L-/IVI 


c lNIS4 c 5?4n 1 

1 i JtOi-"UJ 


QMS4 c i?4fl 1 
1 'UtuLtyu 




Ol lUTOt'T I u 


CMc:4Cp4-i 1 




CMCA1 pq 1 


9NR41 9^ I 
OlxOH I tioJ 


MlvlcD I tOUIVI 


OM JH I COW 


Oil J*» I tOVi 


nIVItU I COL/lvl 


SN54221 J 


SN54221 1 




OIloHcc 1 VV 


SN 54221 W 




SNI55107A I 


SN55107R I 

Ol lOO 1 \J 1 DO 




^.\I551IY7R 1 

OI1JJ 1 \J 1 DU 


SN55107R I 




SN 55 108 A J 

Ol lOO 1 UUmJ 


SN55108BJ 

oiuj 1 uuuj 




SN55108BJ 


SN55108BJ 




SN55109I 


SN55109I 

Ol 1 \J JJ 




SN551 10 1 

Ol lOO 1 1 Uvl 


SN551 10 1 

OIIO J 1 1 UJ 




SN551 14J 

Ol 1JJ 1 1 


961 4DM 

1 T^L> 1 VI 




SN561 14W 

Ol 1JJ 1 ItVK 


961 4FM 

JU 1 T-l IVI 






3D I U IVI 




Ol'lOO 1 1 O VV 


3D 1 oL/IVI 










CMCCI OPW 
OINOO 1 OcVV 






CMKCIQQ 1 
OI1Q0 1 OO J 






OIMOO I OoVV 


LHVI / 00UVV 




oiNooooyj 


ivi ivinuutOL 




Ol 1 / doKJ I r\\J 


1 lunm ah 

L.IVI0U I nU 




SN72301AL 


LM301AH 




SN72305L 


LM305H 




SN72306L 


LM306H 




SN72307J 


LM307D 




SN72307L 


LM307H 




SN72308AJA 


LM308AD 





1-20 



TEXAS INSTRUMENTS (Cont.) 



Texas 
Instruments 


AMD 

Direct 
Replacement 


AMD 

Functional 
Replacement 


OlN / tOUOML 


I MQAQ A Li 

LM0U0AM 




OlN / toUOJW 


i iiinnon 
LM0U0U 




ON / <£OUoL 


1 h AOr\QL-l 




QM7QQ1 -i 1 
OlN fdO\ \ J 


LMol 1 U 




CM70Q1 1 I 


1 hJIOi -1 1-1 

LMJIln 




CM70Q1 Q I A 
OlN/*:o lOJM 


1 RdOi on 

LM31 oU 




CM70Q1 Ql 


1 ft JIO i Ql_l 

LMo I on 




ON72723J 


723 DC 




SN 72723 L 


723 HC 




ON72733J 


733 DC 




CM70700I 

01N /2/ooL 


~?oo Ljr^ 




QNI707/M IA 


7/i -t v\r* 
1 41 UO 




OlN / dlH l L 


7/i 1 uir^ 




OM717/I7 I A 


/4/UO 




O ft 1 707 /I I 

oN 72747 L 


747 HC 




olN/2/4oJA 


1 4oUL/ 




C M707yl O 1 

olN/274oL 


748 HC 




OM7/1 1 i OO 1 

OIN/4L 12oJ 




AM26L123DC 


ON74L123N 




AM26L123PC 


oIN /4Lo l 23J 


CM7/ i H OO I 

oN74Lo123J 


AM25LS123DC 


OlN /4Lo1 2oN 


OlN /4Lo 1 2oN 


AM25LS123PC 


oN74Lo240J 


oN74l_o240J 


Aianrl 00 J r^/"> 

AM25LS240DC 


olN / 4Lo24UlN 


oN /4Lo24UN 


AM25LS240PC 


OKI7/1I OOjH 1 

OlN /4Lo24l J 


CM7^ 1 CO/ -i 1 

oin/4Lo241 J 


a ■ mr 1 oniH r™\ /■"> 

AM25LS241 DC 


O ft 1 ~7 /M OOdH Kl 

oN /4Lo241 N 


oN74LS241 N 


AM25LS241 PC 


oN74Lo242J 


oN74LS242J 


AM25LS242DC 


f' ft 1 ~7 jl 1 On jn|>l 

SN74LS242N 


SN74LS242N 


AM25LS242PC 


SN74LS243J 


SN74LS243J 


AM25LS243DC 


SN74LS243N 


SN74LS243N 


AM25LS243PC 


SN74LS244J 


SN74LS244J 


AM25LS244DC 


SN74LS244N 


SN74LS244N 


AM25LS244PC 


SN74LS424J 


D8224 




SN74LS424N 


P8224 




SN74S240J 


SN74S240J 




SN74S240N 


SN74S240N 




SN74S241J 


SN74S241J 





TEXAS INSTRUMENTS (Cont.) 



Texas 
Instruments 


AMD 

Direct 
Replacement 


AMD 

Functional 
Replacement 


OM"7 A C* 1 A A ft 1 

SN74S241 N 


C*ftl""7>IC*0*t* ft 1 

SN74S241 N 




OM"7j<0)4Hn 1 

SN74S412J 


D8212 




OKl~7 A O A 4 O 

oN74o412 


P8212 




oN 741 23 J 


OKI7 A A OO I 

oN74 123J 


A 1 in/" 1 a on 

AM26123DC 


OM"7 A A OO ft 1 

SN74123N 


Okn a a 00 ft 1 

SN74123N 


A ft AOO A OO T~\ 

AM26123PC 


SN74221J 


SN74221J 




SN74221 N 


SN74221 N 




SN 75 107 A J 


r> k t ~7 a a n "TCI 1 

SN74107BJ 




OM"?r -< 0*7 A ft 1 

SN75107AN 


SN75107BN 




SN75107BJ 


SN75107BJ 




f* ft 1 —> f -j mnk 1 

SN75107BN 


SN75107BN 




O ft 1 ~T r~ J no A 1 

SN75108AJ 


SN75108BJ 




ni 1-71- j ao A K 1 

SN75108AN 


SN75108BN 




SN752108BJ 


SN75108BJ 




SN75108BN 


SN75108BN 




SN75109J 


SN75109J 




ni i-i r . on h 1 

SN75109N 


SN75109N 




SN75110J 


SN75110J 




r»k|-7r 4 j OKI 

SN75110N 


SN75110N 




SN75114J 


961 4DC 




SN75114N 


961 4PC 




SN75115J 


961 5DC 




SN75115 


961 5PC 




SN75182J 


DM8820AJ 




SN75182N 


DM8820AN 




SN75183J 


DM8830J 




SN75183N 


DM8830N 




SN75188J 


MC1488L 




SN75188N 


AM1488PC 




SN75189J 


MC1489L 




SN75189N 


AM1489PC 




SN75189AJ 


MC1489AL 




SN75189AN 


AM1489APC 




SN75369J 


MMH0026CL 




SN75369P 


MH0026CN 





1-21 



DICE POLICY 



Advanced Micro Devices, interface and linear products are all available in dice form. 
ELECTRICAL CHARACTERISTICS 

Each die is electrically tested to the commercial or military grade DC parameters 
to guardbanded limits at 25°C to guarantee operation over the temperature 
range. 

QUALITY ASSURANCE 

All dice are 100% visually inspected to the requirements of M I L-STD-883A, 
Method 2010.2, condition B. 

All dice are glass passivated with only the bonding pads exposed to provide 
scratch protection. All dice are provided without gold backing. 

SHIPPING PACKAGES/ORDER INFORMATION 

All dice are packaged in containers with individual compartments which prevent 
damage to the die during shipping. 
Minimum order for AMD dice is 10 pes. 

SPECIAL CHIP PROCESSING 

If there is a need for additional testing or processing, contact AMD for detailed 
information. 

See following pages on ordering information for detail ordering number. 



1-22 



ORDERING INFORMATION 







ORDER NUMBER 






ORDER NUMBER 




DEVICE 




0°C to +70X 






-55X to +125X 




NUMBER 


Metal 


Hermetic 


Molded 




Metal 


Hermetic 










DIP 


DIP 


Dice 


Can 


DIP 


Flat Pak 


Die* 


Am592 


AM592HC 


AM592DC 


AM592PC 


AM592XC 


AM592HM 


AM592DM 




AM592XM 


Am685 - 


AM685HL 


MIVIOOOLU- 




AM685XL 


AM685HM 


AM685DM 




AM685XM 




AMG86HC 


MMOBOUi»i 




AM686XC 


AM686HM 


a lioMtnu 

KMOODUrvl 




AM686XM 


Am687* 




MMOo / UL 




AM687XL 




AM687DM 




AM687XM 


Am 1500 












MM 1 JUJUW 

AM1500DL 


AM1 500FM 
AM1 500FL 




Am1501 




AM1 501 DC 








AM 1 S01 DM 
MIW 1 1 WtVl 


AM1 501 FM 
















AMI 501DL 


AM1 "VjQI fi 
mm i jua i ri_ 




Am 1508 




ami Ana\ 7 

MM I **JoL/ 
MM } 








am 1 ^nm r 

MM 1 DUOLO 






Ami 558 


AM1458H 








AM1558H 








Am25 Scries 


















Am2502 




nMiijU^UL 


AM2502PC 


AM2502XC 




AM2502DM 


AM2502FM 


AM2502XM 






a iiji^^/iin^ 










MMcoUorM 


a m o t;ni y m 


Am2504 






AM2504PC 


AM2504XC 




AMnainii 

MMtoU4LIM 


AUORAACU 

«rvi£jU4r m 


AM2504XM 


Am25L02 




mM£:OLUa;ULa 




AM25L02XC 




MMilDL-U£UM 


auoci fi5PU 

nMcDLUtrM 


AM25L02XM 


Am25L03 




AM25L03DC 


AM25L03PC 


AM25L03XC 




AMibLUJUM 




AM25L03XM 


Am25L04 
Am25LS240 






A MORI f\A Of 


AM25L04XC 




aiioci rid DM 




AM25L04XM 




unci Cl/nhf 




AM25LS240XC 




MMiiOLOACtUlJM 




AM25LS240XM 


Am25LS241 




AM«;oLb241 UU 


AM2oLb.i41 KO 


AM25LS241XC 




Aijnri CTiinil 

AMa^oLo^41 UM 


AM.loL.bAi4 1 rNI 


AM25LS241 XM 


Am25LS242 




AhJOCI CO/OAr** 

AM^5Lb^42UU 


A 1JOCI C^ATO^ 

AMii5Lb^4^1-'U 


AM25LS242XC 






AMOKI MAOCll 


AM25LS242XM 


Am25LS243 




AM25LS243DC 


AM25LS243PC 


AM25LS243XC 




AMZ5Lb24 JUM 


AiJnci COaI'SCIlI 

AM^5Lb^4orM 


AM25LS243XM 


Am25LS244 




AM25LS244DC 


AM25LS244PC 


AM25LS244XC 




AM2SLS244DM 


AM25LS244FM 


AM25LS244XM 


Am26 Series 


















Am2600 




AM2600DC 


AM2600PC 


AM2600XC 




AM2600DM 


AM2600FM 


AM2600XM 


Am2602 




AM2602DC 


AM2602PC 


AM2602XC 




AM2602DM 


AM2602FM 


AM2602XM 


Am2614 




AM2614DC 


AM2614PC 


AM2614XC 




AM2614DM 


AM2614FM 


AM2614XM 


Am2615 




AM2615DC 


AM2615PC 


AM2615XC 




AM2615DM 


AM2615FM 


AM2615XM 


Am2616 




AM2616DC 


AM2616PC 


AM2616XC 




AM2616DM 


AM2616FM 


AM2616XM 


Am2617 




AM2617DC 


AM2617PC 


AM2617XC 




AM2617DM 


AM2617FM 


AM2617XM 


Am26123 




AM26123DC 


AM26123PC 


AM26123XC 




AM26123DM 


AM26123FM 


AM26123XM 


Am26LS29 




AM26LS29DC 


AM26LS29PC 


AM26LS29XC 




AM26LS29DM 


AM26LS29FM 


AM26LS29XM 


Am26LS30 




AM26LS30DC 


AM26LS30PC 


AM26LS30XC 




AM26LS30DM 


AM26LS30FM 


AM26LS30XM 


Am26LS31 




AM26LS31 DC 


AM26LS31 PC 


AM26LS31 XC 




AM26LS31 DM 


AM26LS31 FM 


AM26LS31 XM 


Am26LS32 




AM26LS32DC 


AM26LS32PC 


AM26LS32XC 




AM26LS32DM 


AM26LS32FM 


AM26LS32XM 


Am26LS33 




AM26LS33DC 


AM26LS33PC 


AM26LS33XC 




AM26LS33DM 


AajIOCI OIICM 
AMiibLOJJr-M 


AM26LS33XM 


Am26L02 




AM26L02DC 


AM26L02PC 


AM26L02XC 




ALJOA7L ninu 


AllOCI noru 

AM^bLUZrM 


AM26L02XM 


Am26L123 




AM26L123DC 


AM26L123PC 


AM26L123XC 




AM26L123DM 


AM26L123FM 


AM26L123XM 


Am26S02 




AM26S02DC 


AM26S02PC 


AM26S02XC 




AMZobOZUM 


AM<:bbU^rM 


AM26S02XM 


Am26S10 




AM26S10DC 


AM26S10PC 


AM26S10XC 




AM26S10DM 


AM26S10FM 


AM26S10XM 


Am26S1 1 




AM26S1 1 DC 


AM26S1 1 PC 


AM26S11XC 




AM26S1 1 DM 


AM26S11FM 


AM26S1 1XM 


Am26Sl2 




AM26S12DC 


AM26S12PC 


AM26S12XC 




AM26S12DM 


AM26S12FM 


AM26S12XM 


Am26S12A 




AM26S12ADC 


AM26S12APC 


AM26S12AXC 




AM26S12ADM 


AM26S12AFM 


AM26S12AXM 


Am29 Series 


















Am2905 




AM2905DC 


AM2905PC 


AM2905XC 




AM2905DM 


AM2905FM 


AM2905XM 


Am2906 




AM2906DC 


AM2906PC 


AM2906XC 




AM2906DM 


AM2906FM 


AM2906XM 


Am2907 




AM2907DC 


AM2907PC 


AM2907XC 




AM2907DM 


AM2907FM 


AM2907XM 


Am2908 




AM2908DC 


AM2908PC 


AM2908XC 




AM2908DM 


AM2908FM 


AM2908XM 


Am291 5A 




AM2915ADC 


AM2915APC 


AM2915AXC 




AM2915ADM 


AM2915AFM 


AM291 5AXM 


Am2916A 




AM2916ADC 


AM2916APC 


AM2916AXC 




AM2916ADM 


AM2916AFM 


Am2916AXM 


Am291 7A 




AM2917ADC 


AM2917APC 


AM291 7AXC 




AM2917ADM 


AM2917AFM 


AM2917AXM 


Am32XX Series 


















Am3212 




D3212 


P3212 


AM8212XC 




MD3212 






Am3216 




D3126 


P3216 


AM8212XC 




MD3216 






Am3226 




D3226 


P3226 


AM8226XC 




MD3226 






Am6070 




AMbu/OUC 


AMbU/UrO 


6070XC 




MMDU/UUM 


Am6071 




Am6072 


















Am6073 


















Am6080 




AM6080DC 


AMoUBUru 


6080XC 




AM60B0DM 






Am6081 




AM6081 DC 
AMDAC-08EQ 


bUb 1 


6081 XC 




AM6081 DM 
AMUAO-U8A(J 






DAC-08 




AMUAG-OBUU 








AMUAO-OBU 






DM, DP or DS Series 


















DS0056 (8 pin) 


DS0056CH 




DS0056CN 


AM0056CX 


DS0056H 






AM0056X 


DS0056 (12 pin) 


DS0056CG 








DS0056G 








OS0056 (14 pin) 




DS0056J 








DS0056J 






DS1 6/3692 




DS3692J 


DS3692N 






DS1692J 


DS1692W 




DM71/81LS95 




DM81LS95N 


DM81 LS95J 


AM81LS95X 




DM71LS95J 


DM71 LS95W 


AM71 LS95X 


DM71/81LS96 




DM81LS96N 


DM81 LS96J 


AM81LS96X 




DM71LS96J 


DM71LS96W 


AM71 LS96X 


nfci7i fm i cot 

UM J 1/8 1 LOS / 




DM81LS97N 


DM81 LS97J 


A lini I C0 7V 

AMH1 Los / A 




DM71LS97J 


DM71LS97W 


A U71 I CQ7 V 

AM/1 Los ' A 


DM71/81LS98 




DM81LS98N 


DM81LS98J 


AM81LS98X 




DM71 LS98J 


DM71LS98W 


AM71LS98X 


DM78/8820 




DM8820J 


DM8820N 


AM8820X 




DM 7820 J 


DM7820W 


AM7820X 


DM78/8820A 




DM8820AJ 


DMB620AN 


AM8820AX 




DM7820AJ 


DM7820AW 


AM7820AX 


DM78/8830 




DM8830J 


DM8830N 


AM8830X 




DM 7830 J 


DM7830W 


AM7830X 


DM78/ 88 31 




DM883 1J 


DM8831 N 


AM8831X 




DM783 1J 


DM7831 W 


AM7831X 


DM/B/8832 




DM 8832 J 


DM8832N 


AM8832X 




DM7832J 


DM7832W 


AM7832X 


tDM73/8303B 




DP8303BJ 


DP8303BN 


AM8303BX 




DP7303BJ 


DP7303BW 


AM7303BX 


DP73/8304B 




DP8304BJ 


DP8304BN 


AM8304BX 




DP7304BJ 


DP7304BW 


AM7304BX 


DS78/8838 




DS8838J 


DS8838N 






DS7838J 


DS7838W 





- 



1-23 



ORDERING INFORMATION (Cont.) 







nnnpR miiurfr 

UnUCn NUMDCn 






ORDER NUMBER 




DEVICE 




D C to +70°C 






-55°C to +125°C 




NUMBER 


M t I 


Hermetic Molded 




M t 1 


Hermetic 

DIP Flat Pak 






Can 


DIP DIP 


Die* 


Can 


Dice 


LH2101A 




LH2301AD 


LD301 


LH2101AD 


LH2101AF 




LM101 


LM301H 


LM301 D LM301 N 


LM101H 


LM101D LM101F 


LD101 






LM201N 




LM201H 


LM201D LM201F 




LM101A 


LM301AH 


LM301AD LM301AN 


LD301A 


LM101AH 


LM101AD LM101AF 


LD101A 






LM201 AN 




LM201AH 


LM201AD LM201AF 




LM102 


LM302H 


LM302D 


LD302 


LM102H 


LM1020 LM102F 


LO102 










LM202H 


LM202D LM202F 




LM105 


LM305H 




LD305 


LM105H 




LD105 
















LH106 


LM306H 


LM306D 


LD306 


LM106H 


LM106F 


LD106 










LM208H 


LM206F 




LM107 


LM307H 


LM307D 


LD307 


LM107H 


LM107D LM107F 


LD107 
















LM108 


LM308H 




LM308D LM308N 


LD308 


LM108H 


LM108D LM108F 


LD108 










LM208H 


LM208D LM208F 




LM108A 


LM308AH 


LM308AD LM308AN 


LD308A 


LM108AH 


LM108AD LM108AF 


LD108A 










1 IIOrlQ A L-l 






LM110 


LM310H 


LM310D LM310N 


LD310 


LM110H 


LM110D LM110F 


LD110 










LM210H 


LM210D LM210F 




LM111 


LM311H 


LM311D LM311N 


LD311 


LM111H 


LM111D LM111F 




LD111 


* 








LM211H 


LM211D LM211F 




LM112 


LM312H 


M312D 


LD312 


LM112H 


LM112D LM112F 


LD112 










LM212H 


LM212D LM212F 




LM118 


LM318H 


LM318D LM318N 


LD318 


LM118H 


LM118D LM118F 


LD118 


• 








LM218H 


LM21SD LM218F 




LM119 


LM319H 


LM319D LM319N 


LD319 


LM119H 


LM119D LM119F 


LD119 








LM219H 


LM219D LM219F 




LM124 




LM324D LM324N 


LD324 




LM1240 LM124F 


LD124 












LM224D LM224F 




LM124A 




LM324AD LM324AN 


LD324A 




LM124AD LM124AF 


LD124A 










LM224AD 


LM224AF 




LM139 




LM339D LM339N 


LD339 




LM139D LM139F 


LD139 












LM239D LM239F 




LM139A 




LM339AO LM339AN 


L0339A 




LM139AD LM139AF 


LD139A 


• 










LM239AD LM239AF 




LM148 




LM348D LM348N 


LD348 




LM148D 


L0148 










LM248D 






LM149 




LU349D LU349N 


LD349 




LM149D 


LD149 


• 










LM249D 




LF155 


LF355H 


LF355N 


LD355 


LF155H 




LD155 










LF225H 






LF155A 
• 


LF355AH 




LD355A 


LF155AH 




LD155A 


LF156 


LF356H 


LF356N 


LD356 


LF156H 




LD156 










LF256H 






LF16A 


LF356AH 




LD356A 


LF156AH 




LD156A 


LF157 


LF357H 


LF357N 


LD357 


LF157H 




LD157 










LF257H 






LF157A 
• 


LF357AH 




LD357A 


LF157AH 




LD157A 


LF198 


LF398H 




LD398 


LF198H 




LD198 










LF298H 






LM21 6 


LM316H 


LM316D 


LD316 








* 








LM216H 


LM216D LM216F 


LD216 


LM216A 


LM316AH 


LM316AD 


LD316A 
















LM216AH 


LM216AD LM216AF 


LD216A 


MC1488 




MC1488L AM1488PC 


AM1488XC 








MC1489 




MC1489L AM1489PC 


AM1489XC 








MC1489A 




MC1489AL AM1489APC 


AM1489AXC 








MC3448A 




MC3448AL MC3448APC 


AM3448X 








MH0026 (8 pin) 


MH0026CH 


MH0026CN 


AM0026CX 


MH0026H 




AM0026X 


MH0026 (12 pin) 


MH0026CG 






MH0026G 






MH0026 (14 pin) 





MMH0026CL 






MMH0026L OS0026F 





1-24 



ORDERING INFORMATION (Cont.) 







ORDER NUMBER 






ORDER NUMBER 




DEVICE 




0°C to +70X 






-55°Cto +125°C 




NUMBER 


Metal 


Hermetic 


Molded 




Metal 


Hermetic 








Can — 


DIP 


DIP 


Dice 


Can 


DIP 


Flat Pak 


Dice 


SN54/74 Series 


















SN54/74123 




SN74123J 


SN74123N 


AM74123X 




SN54123J 


SN54123W 


AM54123X 


SN54/74221 




SN74221J 


SN74221N 


ACT.74221X 




SN54221J 


SN54221W 


AM54221X 


SN54/74LS240 




SN74LS240J 


SN74LS240N 


AM74I ^94nX 




SN54LS240J 


SN54LS240W 


AM^AI ^94nV 


SN54/74LS241 




SN74LS241J 


SN74LS241N 


AM74LS241X 




SN54LS241 J 


SN54LS241W 


AM54LS241X 


SN54/74LS242 




SN74LS242J 


SN74LS242N 


AM74LS242X 




SN54LS242J 


SN54LS242W 


AM54LS242X 


SN54/74LS243 




SN74LS243J 


SN74LS243N 


AM74LS243X 




SN54LS243J 


SN54LS243W 


AM54LS243X 


SN54/74LS244 




SN74LS244J 


SN74LS244N 


AM74LS244X 




SN54LS244J 


SN54LS244W 


AM54LS244X 


SN54/74S240 




SN74S240J 


SN74S240N 


AM74S240X 




SN54S240J 




AM54S240X 


SN54/74S241 




SN74S241J 


SN74S241N 


AM74S241X 




SN54S241J 




AM54S241X 


tSN54/74S242 




SN74S242J 


SN74S242N 


A M 7 1 CO^ IV 
MM / HO*l*t£A 




SN54S242J 




AM54S242X 


SN54/ 74S243 




SN74S243J 


SN74S243N 


AM74S243X 




SN54S243J 




AM54S243X 


SN54/74S244 




SN74S244J 


SN74S244N 


MtVl 1 ^0£H**A 




SN54S244J 






SN55/75 Series 



















SN55/75107B 




SN75107BJ 


SN75107BN 


AM75107BX 




SN55107BJ 




AM55107BX 


?mi;i;/7<; mpR 

O'iDj / D 1 Uo D 




SN75108BJ 


SN75108BN 


AM 751 08 BX 




SN55108BJ 




AM551 08BX 


QKj^*^/7K 1 no 




SN75109J 


SN75109N 


AM751 09X 




SN55109J 




AM55109X 


ON 33/ (S11U 




SN75110J 


SN75110N 


AM751 1 0X 




SN55110J 




AM551 10X 


715 


715HC 


715DC 




715XC 


715HM 


715DM 




715XM 


723 


723HC 


723DC 


723PC 


723 XC 


723HM 


723DM 




723XM 


SSS725 


SSS725CJ 


SSS725CP 






SSS725J 


SSS725P 






733 


733HC 


733DC 




733XC 


733 HM 


733DM 


733FM 


733XM 


741 


741HC 


741 DC 


741 XC 


741 HM 


741 DM 


741 FM 


741 XM 




741 A 


741 EHC 


741 EDC 






741AHM 


741 ADM 


741AFM 




SSS741 


SSS741 CJ 








SSS741J 








747 


747HC 






747XC 


747HM 


747DM 




747XM 


747A 


747EHC 


747EDC 






747AHM 


7 At A r^a J 

/ 4 / MUM 






SSS747 


SSS747CK 


aba /A/Lr 






SSS747K 


SSS747P 


SSS747M 




748 


748HC 


748DC 


748PC 
748 


748XC 


748HM 


748DM 


748FM 


748XM 


8XXX Series 


















8T26 




N8T26F 


N8T26B 


AM8T26X 




S8T26F 




AM8T26X 






rio I £OAr 


KIOTOft A □ 
NO I <:OMB 


AM8T26AX 




S8T26AF 




AM8T26AX 


8T28 




N6T28F 


N8T28B 


AM8T28X 




S8T28F 




AM8T28X 


8212 








AM8212XC 










8216 




Dfl216 


P8216 


AM8216XC 




MMo<; i bUM 






8224 




DB224 


M IVi o £ c. r* \j 


AM8224XC 




At,AttOOAr\\» 






Am8224-4 


















8226 








AM8226XC 




MMOitDLJiVi 






8228 




D6228 


AM8228PC 


AM8228XC 




AM8226DM 






8238 




D8238 


AM8238PC 


AM8238XC 




AM8238DM 






Am8238-4 




AM8238-4DC 


AM8238-4PC 












96 Series 

9600 




9600DC 


9600PC 


AM9600XC 




9600DM 


9600FM 


AM9600XM 


9601 




9601 DC 


9601 PC 


AM9601XC 




9601 DM 


9601 FM 


AM9601XM 


9602 




9602DC 


9602PC 


AM9602XC 




9602DM 


9602FM 


AM9602XM 


9614 




961 4DC 


9614PC 


AM9614XC 




9614DM 


961 4FM 


AM9614XM 


9615 




9615DC 


961 5PC 


AM9615XC 




961 5DM 


961 5FM 


AM961 5XM 


9616 




961 6DC 


961 6PC 


AM9616XC 




961 6DM 






9617 




961 7DC 


961 7PC 


AM9617XC 




961 7DM 




AM9617XM 


96L02 




96L02DC 


96L02PC 


AM96L02XC 




96L02DM 


96L02FM 


AM96L02XM 



1-25 



PRODUCT ASSURANCE 
MIL-M-38510 • MIL-STD-883 



The product assurance program at Advanced Micro Devices defines manufacturing flow, establishes standards and controls, and 
confirms the product quality at critical points. Standardization under this program assures that all products meet military and 
government agency specifications for reliable ground applications. Further screening for users desiring flight hardware and other 
higher reliability classes is simplified because starting product meets all initial requirements for high-reliability parts. 

The quality standards and screening methods of this program are equally valuable for commercial parts where equipment must 
perform reliably with minimum field service. 

Two military documents provide the foundation for this program. They are: 



MIL-M-38510- General Specification for Microcircuits 
MIL-STD-883 - Test Methods and Procedures for Microelectronics 



MIL-M-38510 describes design, processing and assembly workmanship guidelines for military and space-grade integrated 
circuits. All circuits manufactured by Advanced Micro Devices for full temperature range (-55°C to +125°C) operation meet these 
quality requirements of MIL-M-38510. 

MIL-STD-883 defines detail testing and inspection methods for integrated circuits. Three of the methods are quality and processing 
standards directly related to product assurance: 

Test Method 2010 defines the visual inspection of integrated circuits before sealing. By confirming fabrication and assembly 
quality, inspection to this standard assures the user of reliable circuits in long-term field applications. Standard inspection at 
Advanced Micro Devices includes all the requirements of the latest revision of Method 2010, condition B. 

Test Method 5004 defines three reliability classes of parts. All must receive certain basic inspection, preconditioning and 
screening stresses. The classes are: 

Class C - Used where replacement can be readily accomplished. Screening steps are given in the AMD processing flow 
chart. 

Class B - Used where maintenance is difficult or expensive and where reliability is vital. Devices are upgraded from Class 
C to Class B by 160-hour burn-in at 125°C followed by more extensive electrical measurements. All other screening 
requirements are the same. 

Class S - Used where replacement is extremely difficult and reliability is imperative. Class S screening selects extra 
reliability parts by expanded visual and X-ray inspection, further burn-in, and tighter sampling inspection. 



All hermetically sealed integrated circuits (military and commercial) manufactured by Advanced Micro Devices are screened to 
MIL-STD-883, Class C. Molded integrated circuits receive Class C screening except that centrifuge and hermeticity steps are 
omitted. 



Optional extended processing to MIL-STD-883, Class B is available for all AMD integrated circuits. Parts procured to this screening 
are marked with a "-B" following the standard part number, except that linear 100, 200 or 300 series are suffixed "/883B". 

I 

Test Method 5005 defines qualification and quality conformance procedures. Subgroups, tests and quality levels are 
given for Group A (electrical), Group B (mechanical quality related to the user's assembly environment), Group C (die 
related tests) and Group D (package related tests). Group A tests are always performed; Group B, C and D may be 
specified by the user. 

1-26 



MANUFACTURING, SCREENING AND INSPECTION 
FOR 

INTEGRATED CIRCUITS 



All integrated circuits are screened to MIL-STD-883, Method 5004, Class C; quality conformance inspection where 
required is performed to Class B quality levels on either Class B or Class C product. 

All full-temperature-range (-55°C to +125°C) circuits are manufactured to the workmanship requirements of MIL-M- 
38510. 

The flow chart identifies processing steps as they relate to MIL-STD-883 and MIL-M-38510. 



HERMETIC PACKAGE 
PROCESS 



STANDARD PROCESSING 
CLASS C 
Steps 1 Through 25 



MOLDED PACKAGE 
PROCESS 



INSPECTION 

Purchased or fabricated starting materials are inspected for conformance 
to specified requirements. Inspection follows written procedures, and 
records are analyzed for supplier quality negotiations. 

WAFER FABRICATION 

Repeated masking, etching and diffusion processes produce finished dice 
in wafer form. 

IN-PROCESS INSPECTION 

Each wafer is inspected prior to irreversible process steps. 

FINISHED WAFER INSPECTION 

Sample wafers from each finished diffusion lot are inspected to confirm 
lot quality before release for test and assembly. 



WAFER ELECTRICAL TEST 

Electrical probe test of every die. A computer-controlled system measures 
static and dynamic parameters and identifies dice that do not meet 
electrical requirements. 

DIE SEPARATION 

Wafers are separated into individual dice and electrical rejects are removed. 

VISUAL INSPECTION 

Separated dice are inspected and selected at high magnification. 

QUALITY INSPECTION 

Decisions at the 100% inspection are reviewed through periodic random 
sampling, confirming product quality and revealing any need for operator 
retraining. 



DIE ATTACH 



1-27 







11 



12 



o 



13 



QUALITY INSPECTION 

Strength of die attachment, position of die and visual quality of eutectic 
wetting are confirmed periodically by inspecting random samples and 
push-testing the attached dice. 



WIRE BOND 

Hermetic: Aluminum wires, ultrasonic bonding. 
Molded: Gold wires, thermocompression bonding. 

QUALITY INSPECTION 

Weld strength, bond size and position, wire dress and general workmanship 
are confirmed periodically by comparing random samples with assembly 
instructions and quality standards. Bond strength is plotted on statistical 
control charts, providing early warning of process drifts. 

INTERNAL VISUAL INSPECTION 

Assembled but unsealed units are individually inspected at low and high 
power. 

QUALITY STANDARDS: 

All devices - Ml L-STD-883, Method 2010, Condition B (latest revision). 
Full temperature devices - MIL-M-38510, Para. 3.7 for workmanship (re- 
bonding limits). 



14 



15a 



15b 



16 



17 



— □ 



QUALITY INSPECTION 



Decisions at the 100% inspection are reviewed through periodic random 
sampling, providing confirmation of product quality and revealing any 
need for operator retraining. 

FINAL SEAL 

(Hermetic devices) 

ENCAPSULATE 

(Molded Devices) 
HIGH TEMPERATURE STORAGE 

Ml L-STD-883, Method 1008, Cond. C: 150°C, 24 hr 

TEMPERATURE CYCLE 

MIL-STD-883, Method 1010, Cond. C: -65°C, +150°C, 10 cycles 



18 



19 



20 



CENTRIFUGE 

MIL-STD-883, Method 2001, Cond. E: 30,000 G 

SEAL (HERMETICITY) TEST 

MIL-STD-883, Method 1014, Cond. AorB: Fine Leak 
MIL-STD-883, Method 1014, Cond. C2: Gross Leak 

ELECTRICAL TEST 

MIL-STD-883, Method 5004, Para. 3.1.12: Static, dynamic, functional 
tests at 25° C or in certain products at the most critical extreme tempera- 
ture to assure accuracy of device selection. 



o 



1-28 



21 



22 



23 



24 



25 



o 



QUALITY GROUP A ELECTRICAL TEST (TABLE I) 

MIL-STD-883, Method 5005. See the table below. Quality levels 
as defined for Class B are applied to both Class B and Class C 
parts. Proven correlations supported by periodic reconfirma- 
tion may be used for some parameters. 

MARK, INSPECT. PACK FOR SHIPMENT 



QUALITY INSPECTION, PRE-SHIPMENT 

Confirmation of marking, physical quality, and product identity. 

QUALITY INSPECTION FOR SHIPMENT RELEASE 

Confirmation of product type, count, package. 
Confirmation of completion of all process requirements. 
Confirmation of required documentation. 

SHIP TO CUSTOMER 

This AMD standard product meets screening requirements of 
MIL-STD-883, Class C. 



o 



GROUP A ELECTRICAL TESTS 
From MIL-STD-883, Method 5005. Table I 





Subgroups 


LTPD 


Initial 




(Note 11 


Sample Size 


Subgroup 1 — 


Static tests at 25° C 


5 


45 


Subgroup 2 — 


Static tests at maximum rated operating temperature 


7 


32 


Subgroup 3 — 


Static tests at minimum rated operating temperature 


7 


32 


Subgroup 4 — 


Dynamic tests at 25° C — Linear devices 


5 


45 


Subgroup 5 — 


Dynamic tests at maximum rated operating temperature - Linear devices 


7 


32 


Subgroup 6 — 


Dynamic tests at minimum rated operating temperature — Linear devices 


7 


32 


Subgroup 7 — 


Functional tests at 25°C 


5 


45 


Subgroup 8 — 


Functional tests at maximum and minimum rated operating temperatures 


10 


22 


Subgroup 9 - 


Switching tests at 25°C — Digital devices 


7 


32 


Subgroup 10 


- Switching tests at maximum rated operating temperature — Digital devices (Note 2) 


10 


10 


Subgroup 11 


- Switching tests at minimum rated operating temperature — Digital devices (Note 2) 


10 


10 



1. Sampling plans are based on LTPD tables of MIL-M-38510. The smaller initial sample size, based on zero rejects allowed, has been chosen 
unless otherwise indicated. If necessary, the sample size will be increased once to the quantity corresponding to an acceptance number 
of 2. The minimum reject number in all cases is 3. 

2. These subgroups are usually performed during initial device characterization only. 



1-29 



OPTIONAL EXTENDED PROCESSING 
CLASS B 
Steps 101 Through 110 



Advanced Micro Devices offers several extended processing options to meet customer 
high-reliability requirements. These are defined in AMD document 00-003. The flow chart 
below outlines Option B, a 160-hr burn in. Military temperature range devices processed to 
this flow (in the left column) meet the screening requirements of MIL-STD-883, Class B. 



MILITARY RANGE 
HERMETIC PACKAGES 



COMMERCIAL RANGE 

HERMETIC OR 
MOLDED PACKAGES 



101 



102 



103 



104 



105 



106 



BEGINNING MATERIAL 

Standard product taken after completion of step 20 (electrical test) 

BURN IN 

MIL-STD-883, Method 1015: 160 hr, 125°C, or time-temperature equiva- 
lents as allowed by Method 1015. 

FINAL ELECTRICAL TEST 

MIL-STD-883, Method 5004. 

Military: Testing subgroups as defined for Class B. Static and functional 
at 3 temperatures, dynamic or switching at room temperature. 
Commercial: Repeat step 20. 

QUALITY GROUP A ELECTRICAL SAMPLE (TABLE I) 

MIL-STD-883, Method 5005 and Table I. Quality levels as defined for 
Class B. Temperature correlations may be used on commercial prod- 
ucts. 

QUALITY CONFORMANCE TESTS, GROUPS B, C, AND D 

MIL-STD-883, Method 5005. Sample life and environmental tests if re- 
quired by purchase order. Further information on specifying this is given 
in AMD document 00-003. 

DATA PREPARATION AND REVIEW 



107 



108 



109 



110 



6 



MARK, INSPECT, PACK FOR SHIPMENT 

Standard AMD parts with this burn-in option are marked with "-B" after 
the part number, except that linear 100, 200 or 300 series are suffixed 
"/883B". 

QUALITY INSPECTION, PRE-SHIPMENT 

Confirmation of marking, physical quality, and product identity. 

QUALITY INSPECTION FOR SHIPMENT RELEASE 

Final review of shipment against order. 

SHIP TO CUSTOMER 

Military temperature range parts meet screening requirements of MIL- 
STD-883, Class B. 



o 



1-30 



OTHER OPTIONS 



Document 00-003, "Extended Processing Options", further defines Option B as well as other 
screening or sampling options available or special order. Available options are listed here for 
reference. 



Option Description Effect 



A 


Modified Class A screen 
(Similar to Class S screening) 


Provides space-grade product, fol- 
lowing most Class S requirements 
of MIL-STD-883, Method 5004. 


B 


160-hr operating burn in 


UDQrades a Dart from Class C 
to Class B. 


X 


Radiographic inspection (X-ray) 


Related to Option A. Provides 
limited internal inspection of 
sealed parts. 


S 


Scanning Electron Microscope 
(SEM) metal inspection 


Sample inspection of metal 
coverage of die. 


V 


Preseal visual inspection to 
MIL-STD-883, Method 2010, 
Cond. A 


More stringent visual inspection 
of assemblies and die surfaces 
prior to seal. 


P 


Particle impact noise (PIN) 
screen with ultrasonic detection. 


Detects loose particles of 
approximately 0.5 mil size or larger, 
which could affect reliability in 
zero-G or high vibration applications. 


Q 


Quality conformance inspection 
(Group B, C and D life and 
environmental tests) 


Samples from the lot are stressed 
and tested per Method 5005. 
The customer's order must state 
which groups are required. 
Group B destroys 16 devices; 
Group C, 92 devices; Group D, 
60 devices. 



Document 15-010 Rev. E, Jan. 1, 1978 



1-31 




ALPHA NUMERIC INDEX 
FUNCTIONAL INDEX 
SELECTION GUIDES 
INDUSTRY CROSS REFERENCE 
DICE POLICY 
ORDERING INFORMATION 
510/MIL-STD-883 




COMPARATORS 



1 



2 




DATA CONVERSION PRODUCTS 



3 




LINE DRIVERS/RECEIVERS 



4 




MOS MEMORY AND MICROPROCESSOR INTERFACE 



5 




OPERATIONAL AMPLIFIERS 



6 

T 




SPECIAL FUNCTIONS 




VOLTAGE REGULATORS 





PACKAGE OUTLINES 
GLOSSARY 

AMD FIELD SALES OFFICES, SALES REPRESENTATIVES, 
DISTRIBUTOR LOCATIONS 



Comparators - Section II 

Ami 06/206/306 Voltage Comparator/Buffer 2-1 

Ami 11/21 1/311 Precision Voltage Comparator 2-5 

Ami 19/219/319 Dual Voltage Comparator 2-9 

Ami 39/239/339 Low Offset Voltage Quad Comparator 2-13 

Ami 39 A/239 A/339A Low Offset Voltage Quad Comparator 2-13 

Am685 Voltage Comparator 2-19 

Am686 Voltage Comparator 2-27 

Am687/687A Dual Voltage Comparator 2-29 

Ami 500 Dual Precision Voltage Comparator 2-31 

LH21 1 1/221 1/231 1 Dual Precision Voltage Comparator 2-35 

Application Notes 

A New High-Speed Comparator - The Am685 2-39 

Am685/Am686/Am687 - Designing with High-Speed Comparators 2-48 



■ 



Am106/206/306 

Voltage Comparator/Buffer 



Distinctive Characteristics 

• Functionally, electrically, and pin-for-pin equivalent 
to the National LM 106/206/306 

• Drives RTL, DTL orTTL directly 

• Output can switch voltages up to 24 V @ 100 mA 

• Fan-out of 10 with DTL or TTL 



100% reliability assurance testing in compliance with 
MIL STD 883. 

Electrically tested and optically inspected die for 

assemblers of hybrid products. 

Available in metal can and hermetic flat package. 



FUNCTIONAL DESCRIPTION 

The Am106/206/306 are high-speed voltage comparators/ 
buffers designed to be used in applications where high ac- 
curacy and fast response times are required. The device is 
useful as a pulse-height discriminator, relay or lamp driver 
or a line receiver. 



DIAGRAM 



WON - INV , 
INPUT 



INVERT 
INPUT 




APPLICATION 



Level Detector With Hysteresis 




Upper and Lower Trip Points: 



V,„ = V„, 



V IT = V., 



R; [V„ K 



R 2 + Rj 

and 

R 2 [Vom,N-V ref ] 



VREF 



R 2 + R, 
Hysteresis = V H = V UT - V LT 

R ; l v o max * v o min ! 
R,+ R 3 





ORDERING INFORMATION 




Part 
Number 


Package 
Type 


Temperature 
Range 


Order 
Number 


Am306 


Metal Can 
Dice 


0°Cto +70°C 
0°C to +70°C 


LM306H 
LD306 


Am206 


Metal Can 


-25°C to +85°C 


LM206H 


Am 106 


Metal Can 
Flat Pak 


-55°Cto+125°C 
-55°C to +125°C 
-55°Cto+125°C 


LM106H 
LMI06F 
LD106 



CONNECTION DIAGRAMS 
Top Views 



Flat Package 



Metal Can 



MOM INVERTING- 
INPUT L. 
INVERTING INPUT C 





Note: Pin 6 connected 
to bottom of package. 



LIC-075 

Note: Pin 4 connected to case. 



2-1 



Ami 06/206/306 
MAXIMUM RATINGS 



Positive Supply Voltage 


15 V 


Negative Supply Voltage 


-15 V 


Output Voltage 


24 V 


Output to Negative Supply Voltage 


30 V 


Differential Input Voltage 


±5 V 


Input Voltage 


±7 V 


Power Dissipation (Note 1) 


ouu mvv 


Output Short Circuit Duration 


1 sec 


Operating Temperature Range 




Ami 06 


-55°C to +125°C 


Am206 


-25°Cto +85°C 


Am306 


0°C to +70°C 


Storage Temperature Range 


-65°Cto+150°C 


Lead Temperature (soldering, 60 sec) 


300°C 



ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise specified) (Note2) 

Ami 06 

Am306 Am206 



Parameter (see definitions) 


Conditions 


Min 


Typ 


Max 


Min 


Typ 


Max 


Units 


Input Offset Voltage 


Note 3 




1.6 


5.0 




0.5 


2.0 


mV 


Input Offset Current 


Note 3 




1.8 


5.0 




0.7 


3.0 


mA 


Input Bias Current 






16 


25 


10 20 


mA 


Voltage Gain 




40 


40 


V/mV 


Response Time 


Note 4 




30 


40 




30 


40 


ns 


Saturation Voltage 


V IN < -5 mV, l sink = 100 mA 




0.8 


2.0 




1.0 


1.5 


V 


Output Leakage Current 


V IN > 5 mV, 8 V < V 0UT < 24 V 




0.02 


2.0 




0.02 


1.0 


/•A 


The Following Specifications Apply Over The Operating Temperature Ranges 


Input Offset Voltage 


Note 3 


6.5 


3.0 


mV 


Average Temperature Coefficient 
of Input Offset Voltage 


T A ( m ;n) ^ "1"a — TA{max| 




5.0 


20 




3.0 


10 


P V/°C 


Input Offset Current 


"'"a = ^Almax] 

Note 3, T A = T A(rain| 




0.6 
2.4 


5.0 
7.5 




0.25 
1.8 


3.0 
7.0 


pA 
„A 


Average Temperature Coefficient 
of Input Offset Current 


25°C < T A < T A|max) 
T A|min) < T A < 25°C 




15 
24 


50 
100 




5.0 
15 


25 
75 


nA/°C 
nA/°C 


Input Bias Current 




40 


45 


,,A 


Input Voltage Range 


-7 V > V" > -12 V 


±5.0 


±5.0 


V 


Differential Input Voltage Range 




±5.0 


±5.0 


V 


Saturation Voltage 


V IN < -5 mV, \ M = 50 mA 


1.0 


1.0 


V 


Saturation Voltage 


V, N <-5mV, U<16mA 


0.4 


0.4 


V 


Positive Output Level 


V IN > 5 mV, l OUT = 400 M A 


2.5 




5.5 


2.5 




5.5 


V 


Output Leakage Current 


V, N > 5 mV, 8 V < V OUT < 24 V 


100 


100 


„A 


Strobe Current 


V.,, :t! = 0.4V 




1.7 


3.3 




1.7 


3.3 


mA 


Strobe ON Voltage 




0.9 


1.4 




0.9 


1.4 




V 


Strobe OFF Voltage 


U<16mA 




1.4 


2.5 




1.4 


2.5 


V 


Positive Supply Current 


V IN = -5mV 




5.5 


10 




5.5 


10 


mA 


Negative Supply Current 






1.5 


3.6 




1.5 


3.6 




mA 



Note 1: Derate metal can package at 6.8 mW/°C for operation at ambient temperatures above 60°C; derate flat package at 5.4 mW/°C for operation at ambient tempera- 
tures above 40°C. 

Note 2: These specifications apply tor -3 V > V > - 12 V, V + = 12 V and Ta = 25°C unless otherwise specified. 

Note 3: The offset voltages, offset currents, and bias currents given are the maximum values required to drive the output from the minimum output level up to the maxi- 
mum output level. Thus, these parameters actually define an error band and take into account the worst-case effects of voltage gain and input impedance. 
Note 4: The response time specified (see definitions) is for a 100 mV input step with 5 mV overdrive. 



2-2 



Ami 06/206/306 



PERFORMANCE CURVES 



-50 

-100 



Response Time For 
Various Input Overdrives 











[ 




V + = +12V_ 
V" = -6V 














-2n 


V 
V 
V 














i.bm 




■ - 








































: 



































































- 
























- 


— 























































































20 40 60 80 100 120 
TIME - ns 



Transfer Function 




-0.3-0.2 -0.1 0.1 0.2 0.3 0.4 
INPUT VOLTAGE - tnV 



Response Time For 
Various input Overdrives 




20 40 60 80 100 120 
TIME - ns 



Voltage Gain 



Power Consumption 



Positive Output Level 














































S 
















f 














































V 


















V 


= +1 


2V 












V" = -6V 













-75 -50 -25 25 50 75 100 125 
TEMPERATURE — C 



Saturation Voltage 







roc 
















"A 




















.- 


+12V 












-3V>V">-12V 




'l = 






V| N - 


-5 n 


V 




50 mA 




































ib mA 












Omt 












i — 

























































\ 


= -A 




































/ + = 


12V 












V |N = +5 mV 

1 1 



-75 -50 -25 25 50 75 100 125 
TEMPERATURE - "C 



Positive Supply Current 



-75 -50 - 25 25 50 75 100 125 
TEMPERATURE - 'C 



-75 -50 -25 25 50 75 100 125 
TEMPERATURE - C 




+10 *12 
POSITIVE SUPPLY VOLTAGE - V 



Transconductance 




Short Circuit Output Current 



Negative Supply Current 



3 2 1 0-1-2-3-4 -5 
INPUT VOLTAGE - mV 




-75 -50 -25 25 50 75 100 125 
JUNCTION TEMPERATURE - "C 









Mill 


T A - -55-C 
- T A - 25 Cl^5 












Ta-o"':^" 
















\ 






















































r A -70"c'/ 
















T A - 12b (J 

Mli 

















-3 -6 -9 -12 -15 

NEGATIVE SUPPLY VOLTAGE - V 



2-3 



Ami 06/206/306 



ADDITIONAL APPLICATIONS 



Level Detector and Lamp Driver 





Relay Driver 



LIC-078 

Adjustable Threshold Line Receiver 




[NPUTO VW 




•Optional for response time control 




2-4 



Am111/211/311 

Precision Voltage Comparator 



Distinctive Characteristics 

• The Ami 1 1/21 1/31 1 are functionally, electrically, 
and pin-for-pin equivalent to the National 

LM 111/211/311 

• Output Drive - 50V and 50mA 

• Input Bias Current — 150nA max. 

• Input Offset Voltage — 4m V max. 

• Differential Input Voltage Range - ±30V 



• 100% reliability assurance testing in compliance with 
MIL-STD-883 

• Electrically tested and optically inspected die for as- 
semblers of hybrid products 

• Mixing privileges for obtaining price discounts. Refer 
to price list. 

• Available in Metal Can, Hermetic Dual-ln-Line or 
hermetic Flat Packages 



FUNCTIONAL DESCRIPTION 

The Ami 1 1 /21 1/31 1 are voltage comparators featuring low 
input currents, high differential and common mode voltage 
ranges, wide supply voltage range, and outputs compatible 
with all bipolar and MOS circuitry. The inputs and outputs 
can be isolated from system ground, and the output can drive 
loads refered to ground or either supply. Strobing and offset 
balancing are available and the outputs can be wire ORed. 



FUNCTIONAL DIAGRAM 



COLLECTOR 
OUTPUT 



NON-INVERTING 
INPUT 




EMITTER 
BALANCE BALANCE/ OUTPUT 
STROBE 







CONNECTION DIAGRAM 
Top View 
Dual-ln-Line 
Ami 11/21 1/311 



CONNECTION DIAGRAM 
Top View 
Flat Package 
Ami 11/21 1/311 




NC C 

EMITTER OUTPUT Q 
NON-lNVERTINGi INPUT 

INVERTING INPUT Q 
NC C 

v- [ 

BALANCE | 



Pin 6 is connected to bottom of package. 



EMITTER OUTPUT C 
NON-INVERTING' INPUT C 
INVERTING INPUT C 
NCC 




COLLECTOR OUTPUT 



BALANCE/STROBE 
BALANCE 



Pin 5 is connected to bottom of package. 



Part 
Number 



ORDERING INFORMATION 

Package Temperature 
Type Range 



Order 
Number 



Am311 


TO-99 
Hermetic DIP 
Mini-DIP 
Dice 


0°C to +70°C 
0°C to +70°C 
0°C to +70°C 
0°Cto +70°C 


LM311H 
LM311D 
LM311N 
LD311 


Am211 


TO-99 
Hermetic DIP 


-25°C to +85°C 
-25°C to +85°C 


LM21 1H 
LM211D 


Ami 11 


TO-99 
Hermetic DIP 
Flat Pak 
Dice 


-55°Cto +125°C 
-55°Cto + 125° C 
-55°Cto +125°C 
-55°Cto +125°C 


LM111H 
LM111D 
LM111F 
LD111 



CONNECTION DIAGRAM 
Top View 
Metal Can 
Am111/211/311 



EMITTER OUTPUT 




Pin 4 is connected to case. 



2-5 



■— 'Aswrntirt * soy 



Am311 


40V 


Voltage from Emitter Output to V~ 


30V 


Voltage between Inputs 


±30V 


Voltage from Inputs to V - 


+30V, -0V 


Voltage from Inputs to V + 


-30V 


Power Dissipation (Note 1) 


500mW 


Output Short Circuit Duration 


1 sec 


Operating Temperature Range 




Am111 


-55°Cto+125°C 


Am211 


-25°Cto +85°C 


Am311 


0°C to +70°C 


Storage Temperature Range 


-65°Cto+150°C 


Lead Temperature (soldering, 10 sec) 


300°C 



ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise specified) (Note 2) 

Am111 

Am311 Am211 

Parameters (see definitions) Test Conditions Min. Typ. Max. Min. Typ. Max. Units 



Input Offset Voltage (Note 3) 






2.0 


7.5 




0.7 


3.0 


mV 


Input Offset Current (Note 3) 






6.0 


50.0 




4.0 


10.0 


nA 


Input Bias Current (Note 3) 






100 


250 




60 


100 


nA 


Response Time (Note 4) 


R|_ - 500 SI to +5 V, V E = 




200 






200 




ns 


Supply Current 

Positive (Note 5) 






3.9 


7.5 




3.9 


6.0 


mA 


Negative (Note 5) 






2.6 


5.0 




2.G 


4.5 


m A 


Voltage Gain 






200 






200 




V/mV 


Saturation Voltage 


V|N < -5 mV, lc ■ 50 mA 










0.75 


1.5 


Volts 


V||\| < -10 mV, lc = 50 mA 




0.75 


1.5 








Volts 


Output Leakage Current 


V|N > +5 mV, Vc to Vr£ = 50 V 










0.2 


10.0 


nA 


V| N > +10 mV, Vc to Vg = 40 V 




0.2 


50.0 








nA 


The Following Specifications Apply Over The Operating Temperature Ranges 


Input Offset Voltage (Note 3) 








10.0 






4.0 


mV 


Input Offset Current (Note 3) 








70.0 






20.0 


nA 


Input Bias Current (Note 3) 








300 






150 


nA 


Saturation Voltage 


V| |sj < -6 mV, lc = 8 mA 










0.23 


0.40 


Volts 


V| N < -10 mV, l C = 8 mA 




0.23 


0.40 








Volts 


Output Leakage Current 


V| N >+6mV,V C toV E = 50V 










0.1 


0.5 


MA 


Input Voltage Range 




±13 


±14 




±13 


■ 14 




Volts 


Supply Current 

Positive (Note 5) 


T A = 125°C 


1 








2.7 


4.5 


mA 


Negative (Note S) 










1.8 


3.5 


mA 



Notes: 1 . For the Amlll/211/311, derate Metal Can package at G.8mW/°C for operation at ambient temperatures above 75" C, the Dual In- Line at 9mW/"C 
for operation at ambient temperatures above 95°C, and the Flat Packages at 5.4mW/°C for operation at ambient temperatures above 57°C. 

2. Unless otherwise specified, these specifications apply for V + = + 15V, V— = —15V, Vg = —15V, and R |_ at collector output = 7.5ki2 to +15V. 

3. The offset voltage, offset current and bias current given are the maximum values required to drive the collector output to within 1 V of the supplies 
with a 7.5kft load. These parameters define an error band and take into account the worst case effects of voltage gain and input impedance. 

4. The response time specified (see definitions) is for a 100mV input step with 5m V overdrive. 



2-6 



Ami 11/21 1/311 



PERFORMANCE CURVES 



Input Bias Current 



Input Offset Current 



Offset Error 




Common -Mode Limits 



I - , 

o 4.5 

o * 
a 

g 0.4 
£ 

8 02 



RE 


FERRED TO SUPPLY 


VOLTAC 


ES 




- Amman 












- Am311 
































































> 















































































































i I I 








W- 




- A 










mm/211 














mail 


































































SED 
















-NC 































































































-55 -35 -15 5 25 45 65 85 105 125 
TEMPERATURE-'C 



Transfer Function 



50 

> 

< 

O 30 



I I 

COLLECTOR, 




\ V ++ = 50V 


OUTPU 


T 




~~ '"AmlH/211 


n 


L* 1 














— 


























\ 


■"-40V 
Arn31 1 






























EM 

OL 
"~ R L 


TTE 
TPU 

= 60 


R 


r 












oa 


















\ 


r A =25-c- 










'1 














10k 100k 1M 

INPUT RESISTANCE-n 



Response Time For 
Various Input Overdrives 



— 20mV 
5mV„ 
























= ±15V_ 


2 












T A 


-25'C 














1. 1 




















r 





























































-35 -15 5 25 45 65 85 105 125 
TEMPERATUHE-'C 



DIFFERENTIAL INPUT VOLTAGE - mV 



Response Time For 
Various Input Overdrives 



Response Time For 
Various Input Overdrives 





Response Time For 
Various Input Overdrives 




Supply Current 



Supply Current 



Leakage Current 



i I 

Ami 11/21 1/311 
POSITIVE SUPPLY 
OUTPUT LOW^. 




















NEGATIV 


E SUPPLY 






P0 
OU 


SITIVE 
TPUT 


1 1 

SUPPLY 
HIGH | 














25-C 



SUPPLY VOLTAGE -V 




-55 -35 -15 5 25 45 65 85 105 125 
TEMPERATURE-"C 




45 65 85 105 125 
TEMPERATURE- e C 



Ami 11/21 1/311 



APPLICATIONS 



Offset Balancing 



Increasing Input 
Stage Current* 





Strobing 



Strobing OFF both 
Input and Output Stages** 



o + 





2N2222 ~}—0 TL^ n „ r 
STROBE 



> Ikfl 



'Increases input bias current and common mode slew rate by a factor of 3. 
"Typical input current = 50pA with inputs strobed OFF. 



Metallization and Pad Layout 




48 x 65 Mils 



2-8 



Am119/219/319 

Dual Comparator 



Distinctive Characteristics 

• The Ami 19/219/319 are functionally, electrically, 
and pin-for-pin equivalent to the National LM119/ 
219/319. 

• Two independent comparators. 

• Operates from single 5V supply. 

• Output drive - 35V and 25mA. 

• Input bias current - 1/uA max. (1.2/iA for Am319) 

• Response time 80ns typical at ±15V. 



Minimum fan out of 2 each side. 

Inputs and outputs isolated from system ground. 

High common mode slew rate. 

100% reliability assurance testing in compliance with 
MIL-STD-883. 

Electrically tested and optically inspected die for 
assemblers of hybrid products. 
Available in Metal Can, Hermetic Dual-ln-Line, Herme- 
tic Flatpack or Molded DIP packages. 



FUNCTIONAL DESCRIPTION 

The Am119/219/319 are dual high-speed voltage comparators 
designed to operate over a wide range of voltage supplies down 
to a single 5V supply and ground. They have higher gain and 
lower input bias currents than devices such as the ^A710. The 
uncommitted collector of the output stage facilitates RTL, 
DTL and TTL interfacing, and driving lamps and relays at 
currents up to 25mA. The device is specified for operation 
from power supplies up to +15V and features faster response 
than the Ami 11 at the expense of higher power dissipation. 

The Ami 19 performance is specified over the temperature 
range — 55°C to 125°C, the Am219 performance is specified 
over the temperature range — 25° C to 85°C and the Am319 
performance is specified over the temperature range 0°C 
to 70° C. 



FUNCTIONAL DIAGRAM 
(One Comparator) 




NON-INVERTING 



CONNECTION DIAGRAM 
Top View 
Dual In-Line 



CONNECTION DIAGRAM 
Top View 
Flat Package 



c 
c 

GND 1 Q 
+ INPUT 1 Q 
-INPUT 2 Q 

»-C 

OUTPUT 2 Q 



^2 OUTPUT 1 

□ v. 

^ — INPUT 1 
^ + INPUT 2 

□ GND 2 



OUTPUT 1C 
GND 1 C 
+ INPUT 1 C 
- INPUT 1 C 



3*1 rs 



] —INPUT 2 
T + INPUT 2 
3 GND 2 
3 OUTPUT 2 



Pin 6 connected to bottom of package. 



Pin 5 connected to bottom of package. 



ORDERING INFORMATION 



Part 
Number 


Package 
Type 


Temperature 
Range 


Order 
Number 


Am319 


TO-99 
DIP 
Molded DIP 
Dice 


0°C to +70°C 
0°C to +70° C 
0°C to +70°C 
0°C to +70°C 


LM319H 
LM319D 
LM319N 
LD319 


Am219 


TO-99 
DIP 
Flat Pak 


-25°C to +85°C 
-25°C to +85°C 
-25°C to +85°C 


LM219H 
LM219D 
LM219F 


Am119 


TO-99 

DIP 
Flat Pak 
Dice 


-55°C to +I25°C 
-55° C to +125°C 
-55°Cto+125°C 
-55°Cto+125°C 


LMM9H 
LM119D 
LM119F 
LD119 



CONNECTION DIAGRAM 
Top View 
Metal Can 




Pin 5 connected to case. 



2-9 



Ami 19/21 9/31 9 






MAXIMUM RATINGS (Above which the useful life may be impaired) 






Voltage from V+ to V~ 




36 V 


Voltage from Collector Output to V" 




36 V 


Voltage from Ground to V + 




18V 


Voltage from Ground to V - 




25 V 


Differential Input Voltage 




±5.0V 


Input Voltage (Note 1) 




+ 15V 


Power Dissipation (Note 2) 




500 mW 


Output Short Circuit Duration 




10s 


Operating Temperature Range 
Am119 




-55°Cto+125°C 


Am219 




-25°C to +85°C 


Am319 




0°C to +70° C 


Storage Temperature Range 




-65°Cto+150°C 


Lead Temperature (soldering, 10 sec) 




300° C 



ELECTRICAL CHARACTERISTICS (T A = 25°C, Unless Otherwise Noted) (Note 3) 

„ Am319 
Parameters 



Am119/219 



!See definitions) 




Conditions 




Min. 


Typ. 


Max. 


Min. 


Tvp. 


Max. 


Units 


Input Offset Voltage (Note 4) 


R S <S 5k 




2.0 


8.0 




0.7 


4.0 


mV 


Input Offset Current INote 4) 






80 


200 




30 


75 


nA 


Input Bias Current 






250 


1000 




150 


500 


nA 


Response Time (Note 5) 






80 






80 




ns 




Positive 


V+ = 5.0V, V- = 




4.3 






4.3 






Supply Current 


V S = +15V 




8.0 


12.5 




8.0 


11.5 


mA 




Negative 


V S = ±15V 




3.0 


5.0 




3.0 


4.5 




Voltage Gain 




8.0 


40 




10 


40 






Saturation Voltage 


V in < -5.0mV, l c - 25mA 










0.75 


1.5 


Volts 


V in < -10mV, l c = 25mA 




0.75 


1.5 








Output Leakage Current 


V in > +5.0mV, V C to V E = 35V 










0.2 


2.0 


MA 


V in > +10mV, V C to V E = 35V 




0.2 


10 








The Following Specifications Apply Over The Operating Temperature Ranges 


Input Offset Voltage (Note 4) 


R s «5k 






10 






7.0 


mV 


Input Offset Current (Note 4) 








300 






100 


nA 


Input Bias Current 








1200 






1000 


nA 






V in < -8.0mV, l c = 3.2mA 


T A 3»0°C 










0.23 


0.4 




Saturation Voltage 




T A < 0°C 












0.6 


Volts 






V in < -12mV, l c = 3.2mA 




0.3 


0.4 










Output Leakage Current 


V in > +8.0mV, V C to V E = 35 V 










1.0 


10 


uA 


Input Voltage Range 


V s = i15V 




.-13 




♦13 




Volts 


V+ = 5.0V, V-=0 





1.0 





3.0 


1.0 




3.0 



Notes: 1 . For supply voltages less than ± 1 5V the absolute maximum rating is equal to the supply voltage. 

2. Derate Metal Can package at 6.8mW/°C for operation at ambient temperatures above 75°C, the Dual-ln-Une at 9mW/°C for operation at tempera- 
tures above 95°C, and the Flat Package at 5.4mW/°C for operation at temperatures above 57°C. 

3. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single 5V supply up to ± 15V supplies. 

4. The offset voltages and offset currents given are the maximum values required to drive the output within 1 volt of either supply with a 1mA load. 
Thus, these parameters define an error band and take into account the worst case effects of voltage gain and input impedance. 

5. The response time specified is for a 1 00m V input step with 5mV overdrive. 



2-10 



Ami 19/21 9/31 9 



TYPICAL PERFORMANCE CURVES 



Input Currents 



Common Mode Limits 



Transfer Function 



250 
200 
150 
100 
50 
















«±1 


5 V 












\ 


















S 










•si 

































9 






1 OFFSET 



i -35 -15 5 25 45 65 85 105 125 
TEMPERATURE — D C 




-65 -35 -15 5 25 45 65 85 105 125 
TEMPERATURE — °C 




-1.0 -0.6 -0.2 0.2 0.6 1.0 
DIFFERENTIAL INPUT VOLTAGE - V 



Response Time for 
Various Input Overdrives 




50 100 150 200 250 300 350 
TIME - ns 



Response Time for 
Various Input Overdrives 



1 




i 




1 




V 










= ±15V 






y 


5.0 n 




R[_ = 50012 
V ++ = 5.0V 


















u 




L 








2.0r 


iV 









































































60 100 150 200 250 300 350 
TIME - ns 



Input Characteristics 



V S -115V 














T 




25° 




















+- 

4- 










h 










4 










4- 










4 










1 










I 






MAXIMUM 
-DIFFERENTIAL 
INPUT 




1 


















VOLT/ 

1 1 - 


KGE 










































: 





















-10 -6 -2 2 6 10 
DIFFERENTIAL INPUT VOLTAGE - V 



Response Time for 
Various Input Overdrives 




50 100 150 200 250 300 350 
TIME - ns 



Response Time for 
Various Input Overdrives 




50 100 150 200 250 300 350 
TIME — ns 



Output Saturation Voltage 
IT 




0.2 0.4 0.6 0.8 1.0 
OUTPUT VOLTAGE - V 



Supply Current 





-25 


"C 




































f 














f 






_PPL_ 

































5 10 15 

SUPPLY VOLTAGE - V 



| POSITIVE SUPPLY, V s = ±15V 

TThh+4 



Supply Current 



^ i i r 

Am319 

I I I I 



.POSITIVE SUPPLY, 
V 9 + = 5.0V, Vc _ = 



ttt 



—NEGATIVE SUPPLY, V s = ±15V — 



-55 -35 -15 5 25 45 65 85 105 125 
TEMPERATURE — °C 



Output Limiting Characteristics 



















SHOR 
CURF 


TCIR 
ENT 


:uit 




























POWE 
DISSI 


R 

PATIO 


<t 














25"C 



0.6 



5 10 15 

OUTPUT VOLTAGE — V 



0.4 O 
0.2 * 




2-11 



Ami 19/21 9/31 9 



APPLICATIONS 

Relay Driver Window Detector 



INPUTS 




LIC-096 



Metallization and Pad Layout 




2-12 



Am139/239/339 • Am139A/239A/339A 



Low Offset Voltage Quad Comparators 



— 



— 



Distinctive Characteristics 


• 


Low input bias current — 35nA 


• Four high precision comparators 


• 


Low input offset current — 3.0nA and offset 


• Reduced VOS drift over temperature 




voltage — 2.0mV 


• Eliminates need for dual supplies 


• 


Input common-mode voltage range includes ground 


• Allows sensing near ground 


• 


Differential input voltage range equal to the power 


• Wide single supply voltage range or dual supplies 




supply voltage 


2.0V DC to 36V DC 


• 


Low output saturation voltage 



±1.0V DC to ±18V DC 
Very low supply current drain (0.8mA)— independent 
of supply voltage ( 1 .OmW/comparator) makes 
comparators suitable for battery operation. 



1.0mV at 5.0tiA 

60mV at 1.0mA 
Output voltage compatible with 
MOS and CMOS logic systems 



TTL, DTL, ECL, 



FUNCTIONAL DESCRIPTION 

The Am 139. Am239, Am339, Am339A, Am239A and 
Am339A quad comparators are functionally, electrically and 
pin-for-pin equivalent to the National LM139, LM239, LM339, 
LM339A, LM239A and LM339A. This series of precision 
comparators consists of four independent voltage comparators 
which were specifically designed to operate from a single power 
supply over a wide range of voltages. Operation from 
split power supplies is also possible and the low power supply 
current drain is independent of the magnitude of the power 
supply voltage. These comparators have a unique characteristic 



in that the input common-mode voltage range includes ground 
even though operated from a single power supply voltage. 

Application areas include limit comparators, simple analog to 
digital converters; pulse, squarewave and time delay generators; 
wide range VCO; MOS clock timers; multivibrators and high 
voltage digital logic gates. The Am139/A series was designed 
to directly interface with TTL and CMOS. When operated from 
both plus and minus power supplies, the Am139/A will di- 
rectly interface with MOS logic — where the lower power drain 
of the Am139/A is a distinct advantage over standard com- 
parators. 



ORDERING INFORMATION 



Part 



Package 



Temperature 



Order 



Number 


Type 


Range 


Number 


Am339 


DIP 
Molded DIP 
Dice 


0°C to 70° C 
0°C to 70° C 
0° C to 70° C 


LM339D 
LM339N 
LD339 


Am239 


DIP 


-25°C to +85°C 


LM239D 


Am 139 


DIP 
Flat Pack 
Dice 


-55°Cto+125°C 
-55°Cto+125°C 
-55°Cto+125°C 


LM139D 
LM139F 
LD139 


Am339A 


DIP 
Molded DIP 
Dice 


0°C to 70°C 
0°C to 70° C 
0°C to 70° C 


LM339AD 
LM339AN 
LD339A 


Am239A 


DIP 


-25° C to +85° C 


LM239AD 


Am139A 


DIP 
Flat Pack 
Dice 


-55°Cto+125°C 
-55° C to +125°C 
-55°Cto+125°C 


LM139AD 
LM139AF 
LD139A 



SCHEMATIC DIAGRAM 



INPUT 






3 

INPUT 


^ — \c 


• 1 

^6 



CONNECTION DIAGRAM 
Top View 



OUTPUT 2 C - 
OUTPUT 1 \2 

»'C 

INPUT 1 - Q 
INPUT 1+ Q 
INPUT 2— Q 
INPUT 2+ £ -j 



1J 



2 OUTPUT 3 
"2 OUTPUT 4 
2 GND 
^7 I] INPUT 4+ 
12 INPUT 4- 



2 INPUT 3 



Note: Pin 1 is marked for orientation. 



2-13 



Ami 39/239/339 • Ami 39A/239A/339A 



»uiLo a g — n.j vpc ^ r ^>" "DC uperating lemperature Kange 







Am 339/A 


0°C to +70° C 


Power Dissipation (Note 1) 




Am 239/A 


-25°C to +85°C 


Ceramic Dip 


900 mW 


Am 139/ A 


-55°C to +125°C 


Plastic Dip 


570 mW 


Storage Temperature Range 


-65° C to +150°C 


Flat Pack 


800 mW 


Lead Temperature (Soldering, 10 seconds) 


300° C 



ELECTRICAL CHARACTERISTICS 

(V + = +5.0V D C> (Note 4) 

Parameters Test Conditions 



Am239 
Am339 



Am 139 



Am239A 
Am339A 



Am139A 



Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units 



Input Offset Voltage 


T A = +25°C (Note 9) 




12.0 


±5.0 




•2.0 


±5.0 




±1.0 


±2.0 




±1.0 


±2.0 


mV DC 


Input Bias Current (Note 5) 


+ ) or ) with Output in 
Linear Range, T/\ - +25°C 




25 


250 




25 


100 




25 


250 




25 


100 


nA DC 


Input Offset Current 


>IN(+) - 'lN(-), T A " +25°C 




±5.0 


±50 




•3.0 


±25 




±5.0 


±50 




±3.0 


±25 


nA DC 


Input Common-Mode Voltage 
Range (Note 6) 


T A - +25° C 







V + -1.5 







V + -1.5 







V+-1.5 







V + -1.5 


vdc 


Supply Current 


R[_ - ■» on all Comparators 
T A - +25° C 




0.8 


2.0 




o.a 


2.0 




0.8 


2.0 




0.8 


2.0 


mAoc 


Voltage Gain 


Rt_ > 15kn, T A = +25°C, 
V + - 15 Vqq (To Support 
Large V Swing) 




200 






200 




50 


200 




50 


200 




V/mV 


Large Signal Response Time 


V|M = TTL Logic Swing, Vref = 
+1.4V DC ,VR L =5.0V DC , R L » 
5.1kfi and T A - +25°C 




300 







300 






300 






300 




ns 


Response Time (Note 7) 


Vr l - 5.0 V DC and R L = 5.1 kS2 
T A - +25° C 




1.3 






1.3 






1.3 






1.3 




ws 


Output Sink Current 


V|N(-)» + 1.0V Dc .V| NW -0. 
and V„ < +1.5 V DC . T A - +25° C 


6.0 


16 




6.0 


16 




6.0 


16 




6.0 


16 




mA DC 


Saturation Voltage 


V| N (_) > +1.0V DC ,V| N | +) -0, 
and Ijjnk < 4.0 mA, T A = +25°C 




250 


400 




250 


400 




250 


400 




250 


400 


mV DC 


Output Leakage Current 


V| N ( + |>+1.0V DC ,V| N |_)>0 
and V o = 5.0V DC ,T A = +25°C 




0.1 






0.1 






0.1 






0.1 




nADC 


Input Offset Voltage 


(Note9l 






9.0 






9.0 






4.0 






4.0 


mV DC 


Input Offset Current 


l|N(+l - '|M< ( 






1150 






±100 






■ 150 






±100 


nADC 


Input Bias Current 


'lNt+) or !|N(— ) witn Output in 
Linear Range 






400 






300 






400 






300 


nA DC 


Input Common-Mode Voltage 
Range 









V+-2.0 







V + -2.0 







V+-2.0 







V+-2.0 


VDC 


Saturation Voltage 


V| N( _| > +1.0 V 0C , V| N(+ ) - 
and l s j n k < 4.0 mA 






700 






700 






700 






700 


mV DC 


Output Leakage Current 


V| N(+) :»+1.0V Dc . V| NM «0 
and V o -30V DC 






1.0 






1.0 






1.0 






1.0 


mAqc 


Differential Input Voltage 
(Note 8) 


Keep all V| N - S » V oc (or V- if 
used) 






36 






36 






V + 






v + 


VOC 



For high temperature operation, the Am339/A must be derated based on a +125 C maximum junction temperature and a thermal resistance 
of +175 C/W which applies for the device soldered in a printed circuit board, operating in a still air ambient. The Am239/A and Am139/A must 
be derated based on a + 150° C maximum junction temperature. The low bias dissipation and the ON-OFF characteristic of the outputs keeps the 
chip dissipation very small (Pd < 100 mW), provided the output transistors are allowed to saturate. 

Short circuits from the output to V + can cause excessive heating and eventual destruction. The maximum output current is approximately 20 mA 
independent of the magnitude of V + . 

This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the 
input PNP transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN 
parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the comparators to go to the V + voltage level 
(or to ground for a large overdrive) for the time duration that an input is driven negative. This is. not destructive and normal outputs states will 
re-establish when the input voltage, which was negative, again returns to a value greater than —0.3 V DC . 

These specifications apply for V + = +5.0 V DC and -55°C < T A < + 125°C, unless otherwise stated. With the Am239/A all temperature specifica- 
tions are limited to — 25° C < T A < +85° C and the Am339/A temperature specifications are limited to 0°C < T A < + 70°C. 

The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of 
the output so no loading change exists on the reference or input lines. 

The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V, The upper end of the 
common-mode voltage range is V + -1.5 V, but either or both inputs can go to +30 Vrjrj without damage. 

The response time specified is for a 100mV input step with 5.0m V overdrive. 300ns can be achieved with larger overdrive signals, see typical 
performance characteristics section. 

If the voltage applied to any input exceeds V + , all four comparator outputs will go to the high voltage level. The low input voltage state must not 
be less than —0.3 V DC (or 0.3 V DC below the magnitude of the negative power supply, if used). 

At output switch point, V Q = 1.4V DC , R s = 0U with V+ from 5.0 V DC ; and over the full input common mode range (0 V DC to V + -1.5V DC ). 



2-14 



Ami 39/239/339 • Am 139 A/239 A/339 A 



TYPICAL PERFORMANCE CHARACTERISTICS 



Supply Current 



Input Current 



Output Saturation Voltage 




10 20 30 

V* - SUPPLY VOLTAGE - V DC 








! 1 1 

OUT OF 












SATUR 


AT 1 L 


H 










L_ T A 


■ 125°C 












1 1 














\ 


























A 




Ta 




5 C 

























V+ - SUPPLY VOLTAGE - V DC 



0.01 0.1 1.0 10 K 

l - OUTPUT SINK CURRENT - mA 



Response Time for 
Various Input Overdrives 
Negative Transition 



Response Time for 
Various Input Overdrives 
Positive Transition 




INPUT OVERDRIVE = lOOmV 



T A -25-C 




APPLICATION HINTS 

The Am139/A is a high gain, wide bandwidth device; which like 
most comparators, can easily oscillate if the output lead is in- 
advertently allowed to capacitively couple to the inputs via stray 
capacitance. The oscillation shows up only during the output 
voltage transition intervals as the comparator changes states. 
Power supply bypassing is not required to solve this problem. 
Standard PC board-layout is helpful as it reduces stray input-out- 
put coupling. Lowering the input resistors to <10kfZ reduces the 
feedback signal levels and finally, adding even a small amount 
(1 to 10 mV) of positive feedback (hysteresis) causes such a rapid 
transition that oscillations due to stray feedback are not possible. 
Simply socketing the l/C card attaching resistors to the pins will 
cause input-output oscillations during the small transition in- 
tervals unless hysteresis is used. If the input signal is a pulse 
waveform, with relatively fast rise and fall times, hysteresis is not 
required. 

All pins of any unused comparators should be grounded. 

The bias network of the Am139/A establishes a drain current 
which is independent of the magnitude of the power supply volt- 
age over the range of from 2Vqc to 30 Vpc- 



It is not normally necessary to use a bypass 
power supply line. 



the 



The differential input voltage may be larger than V + without 
damaging the device. Protection should be provided to prevent 
the input voltages from going negative more than — 0.3Vqc 
(at 25° C). An input clamp diode and input resistor can be used 
as shown in the applications section. 

The output of the Am139/A is the uncommitted collector of a 
grounded-emitter NPN output transistor. Several collectors can 
be tied together to provide an output OR'ing function. An output 
"pull-up" resistor can be connected to any available power 
supply voltage within the permitted supply voltage range and there 
is no restriction on this voltage due to the magnitude of the volt- 
age which is applied to the V + terminal of the Am139/A pack- 
age. The output can also be used as a simple SPST switch to 
ground (when a "pull-up" resistor is not used). The amount of 
current which the output device can sink is limited by the drive 
available (which is independent of V + ) and the (3 of this device. 
When the maximum current limit is reached (approximately 
16 mA), the output transistor will come out of saturation and the 
output voltage will rise very rapidly. The output saturation voltage 
is limited by the approximately 60i2 r sat of the output transistor. 
The low offset voltage of the output transistor (1 mV) allows the 
output to clamp very nearly to ground level for small load 
currents. 



2-15 



Ami 39/239/339 • Am139A/239A/339A 



TYPICAL APPLICATIONS 

(V+ = 5.0V DC ) 



r 



iookn 
o — Wv- 



lOOkfi 




100k.fi 



;jit 

f = 100kHz 

-o v 



lookn 




1 



CRYSTAL 
200kP. > ,= TQOkHz 



;jin_ 



-o v 



Squarewave Oscillator 



Crystal Controlled Oscillator 



FREQUENCY 
CONTROL 
VOLTAGE 
INPUT 




V + = 30V DC 

+250mV < V c < +50V DC 
700H2 < f_ < 100kHz 



/w 



Two-Decade High-Frequency VCO 




Non-Inverting Comparator 

Basic Comparator with Hysteresis Inverting Comparator with Hysteresis 




LIC-107 



•Or logic gate without pull-up resistor. 



Comparing Input Voltages 

of Opposite Polarity Output Strobing 



2-16 



Ami 



• Am139A/239A/339A 



TYPICAL APPLICATIONS (Cont.) 

<V + = 5.0V DC ) 




-o v 




1/4 DM54XX 




Basic Comparator 



Driving TTL 



12 | 



Driving CMOS 




(V+ = 15V DC ) 



HIGH O WV— 



IN I W. ' 



- 2 R s 
V REF LOW O Wv- 





| ALL DIODES 
| 1N914 

I 
I 



VOUT = A • B • C 



Limit Comparator 



Large Fan-In AND Gate 



100pF I00ki2 
*° O 1| 9 — WV- 



► 1.0M 10kH< 



5.1kii> >4.3kn 



1| — » — VA — •- 

'IN I I 

1N914 y\ <^ 



— ^100k 




-O«o 



l«9"V 200 n < 




1-OM 



One-Shot Multivibrator 



Remote Temperature Sensing 



2-17 



Ami 39/239/339' 



TYPICAL APPLICATIONS (Cont.) 

(V+= 15V DC ) 



M.OM <1.0M 



MOM < 560kn 



100kli 

+v )N o VvV 



+4.0 V 100kS2^ 





f 



40ns >-| 




-ov 



One-Shot Multivibrator with Input Lock Out 



r 



1.0M 

+ 15VO Wv- 



j— ^W- 




'°jf\ 6 °'" n_ o 



* For large ratios 

of Ri/Ft2< D 1 can 
be omitted. 



Iv + 
15kS2 
— wv 



n_ 



h o — \^v- 



— VA— 




-OV 



Pulse Generator 



Bi-Stable Multivibrator 



2-18 



Am685 

Voltage Comparator 



Distinctive Characteristics: 

• 6.5ns MAXIMUM PROPAGATION DELAY AT 5mV 
OVERDRIVE 

• 3.0ns Latch setup time 

• Complementary ECL outputs 

• 5012 line driving capability 



100% reliability assurance testing in compliance with 
MIL-STD-883 

Electrically and optically inspected dice for assemblers 
of hybrid products 

Available in metal can and hermetic dual-in-line 
packages 



FUNCTIONAL DESCRIPTION 

The Am685 is a fast voltage comparator manufactured with an 
advanced bipolar NPN, Schottky diode high-frequency process that 
makes possible very short propagation delays (6.5 ns) without 
sacrificing the excellent matching characteristics hitherto associated 
only with slow, high-performance linear IC's. The circuit has differ- 
ential analog inputs and complementary logic outputs compatible 
with most forms of ECL. The output current capability is adequate 
for driving terminated 50S^ transmission lines. The low input offset 
and high resolution make this comparator especially suitable for 
high-speed precision analog-to-digital processing. 

A latch function is provided to allow the comparator to be used in a 
sample-hold mode. If the Latch Enable input is HIGH, the com- 
parator functions normally. When the Latch Enable is driven LOW, 
the comparator outputs are locked in their existing logical states. 
If the latch function is not used, the Latch Enable must be con- 
nected to ground. 



FUNCTIONAL DIAGRAM 



INVERTING ^ 

INPUT 




LATCH ENABLE 



The outputs are open emitters, therefore external pull- 
down resistors are required. These resistors may be in 
the range of 50-200n connected to -2.0 V, or 200— 
2000U connected to -5.2 V. 



CIRCUIT DIAGRAM 




LATCH 
ENABLE 



OUTPUT OUTPUT 





ORDERING INFORMATION 




Part 
Number 


Package 
Type 


Temperature 
Range 


Order 
Number 


Am685 


Metal Can 
DIP 


-30°C to +85°C 
-30°Cto +85°C 


Am685H L 
Am685DL 


Am685 


Metal Can 
DIP 


-55°Cto +125°C 
-55°Cto+125°C 


Am685HM 
Am685DM 



Am685 



Dice 
Dice 



-30°C to +85° C 
-55° C to +125°C 



Am685XL 
Am685XM 



Metal Can 



CONNECTION DIAGRAMS 
Top Views 



Dual-ln-Line 





: On metal package, pin 5 is connected to case. 
On DIP. pin 8 is connected to case. 



2-19 



Am685 

MAXIMUM RATINGS (Above which the useful life may be impa 



Positive Supply Voltage 




+7 V 


Negative Supply Voltage 




-7 V 


Input Voltage 




±4V 


Differential Input Voltage 




±6V 


Output Current 




30 mA 


Power Dissipation (Note 2) 




500 mW 



i red ) 



Operating Temperature Range 


Am685-L 


-30°Cto +85°C 


Am685-M 


-55°Cto+125°C 


Storage Temperature Range 


-65°Cto+150°C 


Lead Temperature (Soldering, 60 Sec.) 


300° C 


Minimum Operating Voltage (V + to V - ) 


9.7V 



ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGES (Unless Otherwise Specified) 
DC Characteristics 



Am685-L 



Am685-M 



Symbol 


Parameter (see definitions) 


Conditions (Note 3) 


Min. 


Max. 


Min. 


Max. 


Units 


v s 


Input Offset Voltage 


R S < 100 f!, T A = 25°C 
R S < 100 n 


-2.0 
-2.5 


+2.0 
+2.5 


-2.0 
-3.0 


+2.0 
+3.0 


mV 
mV 


AVqs/AT 


Average Temperature Coefficient 
of Input Offset Voltage 


RS < 100 f! 


-10 


+10 


-10 


+10 


uV/°C 


'OS 


Input Offset Current 


T A =25°C 


-1.0 
-1.3 


+1.0 
+1.3 


-1.0 
-1.6 


+1 .0 
+1.6 


MA 
MA 


"B 


Input Bias Current 


T A = 25° C 




10 
13 




10 
16 


ma 
ma 


"in 


Input Resistance 


T A = 25° C 


6.0 




6.0 




kfi 


C|N 


Input Capacitance 


T A = 25° C 




3.0 




3.0 


pF 


V C M 


Input Voltage Range 




-3.3 


+3.3 


-3.3 


+3.3 


V 


CMRR 


Common Mode Rejection Ratio 


R S < 1 00 n, -3.3 < V CM < +3.3 V 


80 




80 




dB 


SVRR 


Supply Voltage Rejection Ratio 


R s «100n, AV S =±5% 


70 




70 




dB 






T A = 25°C 


-0.960 


-0.810 


-0.960 


-0.810 


V 


V H 


Output HIGH Voltage 


T A = T A(min.) 


-1 .060 


-0.890 


-1.100 


-0.920 


V 






Ta = T A(max ) 


-0.890 


-0.700 


-0.850 


-0.620 


V 






T A = 25° C 


-1 .850 


-1.650 


-1.850 


-1 .650 


V 


vol 


Output LOW Voltage 


T A - T A(min ) 


-1 .890 


-1 .675 


-1 .91 


-1.690 


V 






Ta = T A (max.) 


-1 .825 


-1.625 


-1 .810 


-1.575 


V 


i+ 


Positive Supply Current 






22 




22 


mA 




Negative Supply Current 






26 




26 


mA 


p DISS 


Power Dissipation 






300 




300 


mW 



Switching Characteristics (V in = lOOmV, V od = 5mV) 



tpd+ 


Input to Output HIGH 


TAImin.) <T A <25°C 
T A = T A(max.) 


4.5 
5.0 


6.5 
9.5 


4.5 
5.5 


6.5 
12 


ns 
ns 


tpd- 


Input to Output LOW 


TAImin.) < T A < 25°C 
Ta =T A ( max ) 


4.5 
5.0 


6.5 
9.5 


4.5 
5.5 


6.5 
12 


ns 
ns 


tpd+(E) 


Latch Enable to Output HIGH 
(Note 4) 


TAImin.) < T A < 25°C 
T A = T A(max.) 


4.5 
5.0 


6.5 
9.b 


4.5 
5.5 


6.5 
12 


ns 
ns 


tpd-IE) 


Latch Enable to Output LOW 
(Note 4) 


T A (min.)<T A <25"C 
T A = T A(max.) 


4.5 
5.0 


6.5 
9.5 


4.5 
5.5 


6.5 
12 


ns 
ns 


«s 


Minimum Set-up Time (Note 4) 


TAImin.) < T A < 25°C 
T A = T A(max.) 




3.0 
4.0 




3.0 
6.0 


ns 
ns 


th 


Minimum Hold Time (Note 4) 


T A(min) < T A < T A ( max .) 




1.0 




1.0 


ns 


tpwtE) 


Minimum Latch Enable Pulse Width 
(Note 4) 


TAImin.) < T A < 25°C 
Ta ' T A ( max | 




3.0 
4.0 




3.0 
5.0 


ns 
ns 



NOTES: 2: For the metal can package, derate at 6.8 m«l/*C for operation at ambient temperatures above +100°C; for the dual-in-line package, derate at 
9 mW/°C for op.r.»ion at .mbi.n, tomp.ratur.s .bovi +105° C. 
3: Unless otherwise specified V + - 6.0V, V" = -5.2V, V T - -2.0V, and R L - 50Ii; all switching characteristics are for a 100 mV Input step with 
5 mV overdrive. The specifications given for V os , l os , l B , CMRR, SVRR, t pd+ and t pd _ apply over the full V CM range and for ±5% supply 
voltages. The Am685 is designed to meet the specifications given in the table after thermal equilibrium has been established with a transverse 
air flow of 500 LFPM or greater. 

4: Owing to the difficult and critical nature of switching measurements involving the latch, these parameters can not be tested in production. 
Engineering data indicates that at least 95% of the units will meet the specifications given. 



2-20 



Am685 



TIMING DIAGRAM 



KEY TO TIMING DIAGRAM 




m 
m 



MUST BE 
STEADY 



MAY CHANGE 
FROM H TO L 



DON'T CARE; 
ANY CHANGE 
PERMITTED 



WILL BE 
CHANGING 
FROM H TO L 



WILL BE 
CHANGING 
FROM L TO H 



CHANGING; 

STATE 

UNKNOWN 



Figure 1 

The set-up and hold times are a measure of the time required for an input 
signal to propagate through the first stage of the comparator to reach the 
latching circuitry. Input signal changes occurring before t s will be detected 
and held; those occurring after t n will not be detected. Changes between 
t s and t n may or may not be detected. 



l pd+ 



tpd- 



*pd+<E) 



DEFINITION OF TERMS p diss 

Vqs INPUT OFFSET VOLTAGE - That voltage which must be 
applied between the two input terminals through two equal 
resistances to obtain zero voltage between the two outputs. 

avqs/at average temperature coefficient of input off- 
set VOLTAGE — The ratio of the change in input offset 
voltage over the operating temperature range to the temperature 
range. 

Iqs INPUT OFFSET CURRENT - The difference between the 
currents into the two input terminals when there is zero voltage 
between the two outputs. 

I B INPUT BIAS CURRENT -The averageof the two input currents. 

R| N INPUT RESISTANCE - The resistance looking into either input 

terminal with the other grounded. 

C|n INPUT CAPACITANCE - The capacitance looking into either 

input terminal with the other grounded. 

V CM INPUT VOLTAGE RANGE - The range of voltages on the 

input terminals for which the offset and propagation delay ,s 
specifications apply. 

CMRR COMMON MODE REJECTION RATIO - The ratio of the input 
voltage range to the peak-to-peak change in input offset voltage 
over this range. *h 

SVRR SUPPLY VOLTAGE REJECTION RATIO - The ratio of the 
change in input offset voltage to the change in power supply 
voltages producing it. *pw(E) 

V 0H OUTPUT HIGH VOLTAGE - The logic HIGH output voltage 
with an external pull-down resistor returned to a negative supply. 

Vql OUTPUT LOW VOLTAGE - The logic LOW output voltage 
with an external pull-down resistor returned to a negative supply. 

1+ POSITIVE SUPPLY CURRENT - The current required from the 

positive supply to operate the comparator. 

I- NEGATIVE SUPPLY CURRENT - The current required from 

the negative supply to operate the comparator. 



POWER DISSIPATION - The power dissipated by the com- 
parator with both outputs terminated in to -2.0V. 



SWITCHING TERMS (refer to Fig. 1 ) 



INPUT TO OUTPUT HIGH DELAY - The propagation delay 
measured from the time the input signal crosses the input offset 
voltage to the 50% point of an output LOW to HIGH transition. 

INPUT TO OUTPUT LOW DELAY - The propagation delay 
measured from the time the input signal crosses the input offset 
voltage to the 50% point of an output HIGH to LOW transition. 

LATCH ENABLE TO OUTPUT HIGH DELAY - The propaga- 
tion delay measured from the 50% point of the Latch Enable 
signal LOW to HIGH transition to the 50% point of an output 
LOW to HIGH transition. 

LATCH ENABLE TO OUTPUT LOW DELAY - The propaga- 
tion delay measured from the 50% point of the Latch Enable 
signal LOW to HIGH transition to the 50% point of an output 
HIGH to LOW transition. 

MINIMUM SET-UP TIME - The minimum time before the 
negative transition of the Latch Enable signal that an input 
signal change must be present in order to be acquired and held 
at the outputs. 

MINIMUM HOLD TIME — The minimum time after the negative 
transition of the Latch Enable signal that the input signal must 
remain unchanged in order to be acquired and held at the outputs. 

MINIMUM LATCH ENABLE PULSE WIDTH - The minimum 
time that the Latch Enable signal must be HIGH in order to 
acquire and hold an input signal change. 



OTHER SYMBOLS 



Rs 
v s 
v+ 
v- 



Ambient temperature 
Input source resistance 
Supply voltages 
Positive supply voltage 
Negative supply voltage 



Vy Output load terminating voltage 
R|_ Output load resistance 
Vjn Input pulse amplitude 
V oc j Input overdrive 
f Frequency 



2-21 



Am685 



MEASUREMENT OF PROPAGATION DELAY 

A voltage comparator must be able to respond to input signal levels ranging from a few millivolts to several volts, ideally with little 
variation in propagation delay. The most difficult condition is where the comparator has been driven hard into one state by a large signal, 
and the next input signal is just barely enough to make it switch to the other state. This forces the input stage of the circuit to swing 
from a full off (or on) state to a point somewhere near the center of its linear range, thus exercising both its large- and small-signal 
responses. If the comparator is fast for this condition, it should be as fast or faster for almost any other condition. The unofficial 
industry standard input signal is a 100nnV step with an overdrive of 5mV {the overdrive is the voltage in excess of that needed to bring 
the output to the center of its dynamic range)."The 100mV is more than enough to fully turn on tbe input stage, but not so large to make 
measurement a problem. Large pulses would require exceptionally good control on waveform purity, since only a few tenths of a 
percent of overshoot or ripple would be enough to affect the value of the overdrive and, for sensitive comparators, result in false 
switching. The propagation delay is measured from the time the input signal crosses the input threshold voltage (i.e., the offset voltage) 
to the 50% point of either output. This definition ensures that each unit is measured under equal conditions, and also makes the 
measurement relatively independent of the input rise and fall times. 




The test circuit of Figure 2 provides a means of automatically nulling out the offset voltage and applying the overdrive. With SI in the 
"NULL" position, the feedback loop around the Am685 via the two operational amplifiers corrects for the offset of the circuit including 
any dc shift in the ground level of the input signal. When switched to "TEST", the offset is held on the storage capacitor of the Am21 6A 
and the overdrive is added at the Am216A non-inverting input. The duty cycle of the signal is made low so that the presence of the input 
pulse during nulling will not disturb the offset. A solid ground plane is used for the test jig, and capacitors bypass the supply voltages. 
All power and signal leads are kept as short as possible. The Am685 input and output run directly into the 50£2 inputs of the sampling 
scope via equal lengths of 50£2 coaxial cable. For the conditions shown in the figure, t pc j+ is measured at the Q output and t pc) _ at the 
Q output. If it is desired to measure the opposite output polarities, the polarities of the input signal and overdrive must be reversed. 

THERMAL CONSIDERATIONS 

To achieve the high speed of the Am685, a certain amount of power must be dissipated as heat. This increases the temperature of the 
die relative to the ambient temperature. In order to be compatible with ECL III and ECL 1 0,000, which normally use air flow as a means 
of package cooling, the Am685 characteristics are specified when the device has an air flow across the package of 500 linear feet per 
minute or greater. Thus, even though different ECL circuits on a printed circuit board may have different power dissipations, all will have 
the same input and output levels, etc., provided each sees the same air flow and air temperature. This eases design, since the only change 
in characteristics between devices is due to the increase in ambient temperature of the air passing over the devices. If the Am685 is oper- 
ated without air flow, the change in electrical characteristics due to the increased die temperature must be taken into account. 

INTERCONNECTION TECHNIQUES 

All high-speed ECL circuits require that special precautions be taken for optimum system performance. The Am685 is particularly 
critical because it features very high gain (60dB) at very high frequencies (100MHz). A ground plane must be provided for a good, low 
inductance, ground current return path. The impedance at the inputs should be as low as possible and lead lengths as short as practical. 
It is preferable to solder the device directly to the printed circuit board instead of using a socket. Open wiring on the outputs should be 
limited to less than one inch, since severe ringing occurs beyond this length. For longer lengths, the printed-circuit interconnections be- 
comp microstrip transmission lines when backed up by a ground plane, with a characteristic impedance of 50 to 1 50S7. Reflections will 
occur unless the line is terminated in its characteristic impedance. The termination resistors normally go to -2.0V, but a Thevenin 
equivalent to V" can be used at some increase in power. Best results are usually obtained with the terminating resistor at the end of the 
driven line. The lower impedance lines are more suitable for driving capacitive loads. The supply voltages should be well decoupled with 
RF capacitors connected to the ground plane as close to the device supply pins as possible. 



2-22 



Am685 



PERFORMANCE CURVES 

(Unless otherwise specified, standard conditions for all curves are T/^ = 25° C, V + = 6.0V, V~ = -5.2V, 
Vj = -2.0V, R|_ = 50J2, and switching characteristics are for V, n = 100mV, V ot j = 5mV.) 



Response 
for Various 
Input Overdrives 









--20 


OUTPUT 












HIV 








10m 




f fl 

1/ 




v 








y i 

7 2.5mV 




























NON-INV 























































Response 
for Various 
Input Overdrives 



Q OUTPUT 




1 1 


I 1 




1/ 




NON INV 




111 1 




INPUT 














y 


it 


mV 




1 
















20 mV 

































in — 

















-0.8 
-0.9 
-1.0 



Response 
for Various 
Input Signal Levels 




6 8 10 12 14 16 18 
TIME - ns 



Propagation Delays 
as a Function of 
Input Overdrive 




Response 
for Various 
Load Resistances 



F 
\ 




jon Y 

-2.0V 












/ 




















































200 a 

-2.0 V 





Propagation Delays 
as a Function of 
Temperature 




-56 -35 -15 5 25 45 65 85 105 1 
TEMPERATURE - C 

Response 
for Various 
Load Resistances 



R l = 200 
V T - -5. 


1 I 






\- 




























/ 






1 R l- 

-U-V T 


. soon 

= -5 2V 















Propagation Delay 
as a Function of 
Input Signal Level 




±lmV ±10mV 1.1V ±1.0V ±10V 
INPUT VOLTAGE 

Propagation Delays 
as a Function of 
Load Resistance 



6 ' 2 4 
TIME— ns 



100 200 300 400 500 
LOAD RESISTANCE -Si 



Propagation Delays 
as a Function of 
Negative Supply Voltage 



-4.6 -4.8 -5.0 -5.2 -5.4 -5 6 
NEGATIVE SUPPLY VOLTAGE 



Propagation Delays 
as a Function of 
Common Mode Voltage 



'pd- 



































J 















Output Rise and Fall Times 
as a Function of 
Temperature 















10 


9 


> 










































RIS 


: 1 llVlt 

k 




s 








































< 


















t 

LLT 


HE 

























COMMON MODE VOLTAGE - 



-55 -35 -15 5 25 45 65 85 105 125 
TEMPERATURE - "C 



2-23 



Am685 



PERFORMANCE CURVES (Cont.) 

(Unless otherwise specified, standard conditions for all curves are = 25° C, V + = 6.0V, V - = -5.2V, 
Vy = -2.0V, R|_ ■ 50fi, and switching characteristics are for Vj n = 100mV, V oc | = 5mV.) 



Set-up Time as a 
Function of Temperature 































































= 2. 


imV 

TlV- 
















— 5 
10 


,- A , ■ 






























































20 mV 





-55 -35 -15 5 25 45 65 85 105 125 
TEMPERATURE — °C 



Set-up Time as a 
Function of Input Overdrive 




5 10 
OVERDRIVE-mV 



Common Mode Pulse Response 



s o 

8> 

































) 












1 














































— 










































A 














\/ 








/ 










V 

























20 40 60 80 1 00 
TIME— ns 



Min. Latch Enable 
Pulse Width as a 
Function of Temperature 





























































\ 




2.5 

—5 


nv- 


y 




























































0t 


I 






20 mV 



-35 -16 5 25 45 65 85 105 125 
TEMPE RATURE— 



Min. Latch Enable Pulse 
Width as a Function of 
Input Overdrive 



























































A - 125 C 

A - 85* C 

r A =25*c 


































l A --M-C 













Response to 
100 MHz Sine Wave 




OVERDRIVE-mV 



8 10 12 14 16 18 20 
TIME— ns 



Voltage Gain 
as a Function of 
Temperature 



2400 
2200 
2000 
1 1800 


f 




IM 


























































"s 














V0LTA( 


































N 


















800 





















-55-35-16 5 25 45 65 85 105 125 
TEMPERATURE— U C 



Voltage Gain 
as a Function of 
Negative Supply Voltage 




-4.6 -4.8 -5.0 -5.2 -5.4 -5.6 -5.8 
NEGATIVE SUPPLY VOLTAG E— V 



Voltage Gain 
as a Function of 
Frequency 




10 100 
FREQUENCY-MHz 



Common Mode Limits 
as a Function of 
Temperature 



















p 


■SIT 


vF 








F 


:,Mi 


r 
























































N 


GA 


nvF 


CO 




N M 




l i r,- 


IT 



































-55 -35 -15 5 25 45 65 85 105 125 
TEMPERATURE— °C 



Negative Common Mode 
Limit as a Function of 
Negative Supply Voltage 




-4.8 -5.0 
NEGATIVE SUPPL> 



-5.4 -5.6 -5.8 
VOLTAGE-V 



Positive Common Mode Limit 
as a Function of 
Positive Supply Voltage 




5.6 5.8 6.0 6.2 6.4 66 
POSITIVE SUPPLY VOLTAGE-V 



2-24 



PERFORMANCE CURVES (Com.) 

(Unless otherwise specified, standard conditions for all curves are = 25° C, V + - 6.0V, V ■ -5.2V, 
V T = -2.0V, R[_ = 50«, and switching characteristics are for V in - 1 00m V, V od = 5mV.) 



Am685 



Output Levels as a 
Function of Temperature 



£ 4 















































)H 




































































V 

















































-55-35-15 5 25 45 65 85 105 125 
TEMPERATURE— °C 



Output Levels As A Function 
Of Negative Supply Voltage 





























































v 




























































- 




































V 


OL 



















































































3 -4.8 -5.0 -5.2 -5.4 -5.6 -5.8 
NEGATIVE SUPPLY VOLTAGE— V 



Output Levels As A 
Function Of DC Loading 































/ 










DH 










N 


v 






t 








/ 2G 


on 








o 














1 












LUAU LIIMbb 

FOR V T = -2.0V 








i 











































8 12 16 20 24 28 32 
LOAD CURRENT -mA 



Supply Currents 
As A Function Of 
Temperature 




-55 -35-15 5 25 45 

TEMPERATURE— °C 



65 85 105 125 



Supply Currents 
As A Function Of 
Negative Supply Voltage 




-4.6 -4.8 -5.0 -5.2 -5.4 -5.6 -5.8 
NEGATIVE SUPPLY VOLTAGE-V 



Supply Currents 
As A Function Of 
Positive Supply Voltage 







5.4 5.6 5.8 6.0 6.2 6.4 6.6 
POSITIVE SUPPLY VOLTAGE— V 



Input Bias Current 
As A Function Of 
Temperature 




-35-15 5 25 45 65 85 105 126 
TEMPERATUR E— °C 



Input Bias Current 
As A Function Of 
Negative Supply Voltage 



-4.6 -4.8 -5.0 -5.2 -5.4 -5.6 -! 
NEGATIVE SUPPLY VOLTAGE-V 



Input Bias Current 
As A Function Of 
Common Mode Voltage 




COMMON MODE VOLTAGE— V 



Input Resistance 
As A Function Of 
Temperature 




Input Resistance 
As A Function Of 
DC Differential Input Voltage 




-150 -100 -50 50 100 150 
DC DIFFERENTIAL INPUT VOLTAGE— mV 



Input Current 
As A Function Of 
Differential Input Voltage 




-150 -100 -50 50 100 150 
DIFFERENTIAL INPUT VOLTAGE— (nV 



2-25 



Am685 




LIC-128 



High-Speed Sampling 




Metallization and Pad Layout 

32 x 54 Mils 



I -I 1 



•L" 



— Q OUTPUT 
— Q OUTPUT 



2-26 



Am686 

Voltage Comparator 



Distinctive Characteristics 

• 12ns MAXIMUM PROPAGATION DELAY AT 5mV 
OVERDRIVE 

• Complementary Schottky TTL outputs 

• Fanout of 5 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 



Electrically and optically inspected dice for assemblers 
of hybrid products. 

Available in metal can and hermetic dual-in-line 
packages. 



FUNCTIONAL DESCRIPTION 

The Am686 is a fast voltage comparator manufactured with an 
advanced bipolar NPN, Schottky diode high-frequency process that 
makes possible very short propagation delays without sacrificing 
the excellent matching characteristics hitherto associated only with 
slow, high-performance linear ICs. The circuit has differential analog 
inputs and complementary logic outputs compatible with Schottky 
TTL. The output current capability is adequate for driving 5 
standard Schottky inputs. The low input offset and high resolution 
make this comparator especially suitable for high-speed precision 
analog-to-digital processing. 

A latch function is provided to allow the comparator to be used in a 
sample-hold mode. If the Latch Enable input is LOW, the com- 
parator functions normally. When the Latch Enable is driven HIGH, 
the comparator outputs are locked in their existing logical states. 
If the latch function is not used, the Latch Enab'le may be left open 
or connected to ground. 



Metallization and Pad Layout 




46 X 53 Mils 



CIRCUIT DIAGRAM 




ORDERING INFORMATION 



Part 
Number 


Package 
Type 


Temperature 
Range 


Order 
Number 


Am686 


Metal Can 


0°C to 70°C 


Am686HC 


DIP 


0°C to 70°C 


Am686DC 


Am 686 


Metal Can 


-55°Cto+125°C 


Am686HM 


DIP 


-55°Cto+125°C 


Am686DM 


Am686 


Dice 
Dice 


0°C to 70°C 
-55°C to+125°C 


Am686XC 
Am686XM 



CONNECTION DIAGRAMS 
Top Views 

Metal Can Dual-ln-Line 




•[l IS □ NC 

V* £ 3 | — □ B OUTPUT 

*PUT C -M-/^^ 12 ID GROUND 



□ 



Note 1 : On metal package, pin 5 is connected to case. 
On DIP, pin 6 is connected to case. 



2-27 



Negative Supply Voltage 



Input Voltage 


±4V 


Differential Input Voltage 


±6V 


Power Dissipation (Note 2) 


600mW 


Lead Temperature (Soldering, 60 sec.) 


300° C 


Storage Temperature Range 


-65°Cto+150°C 



Am686-M 



-55 Cto+125"C 



Operating Supply Voltage Range 
Am686-C V + = 



+5.0V +5%, V- = -6.0V ±5% 



Am686-M 



V + = +5.0V +10%, V- = -6.0V ±10% 



Minimum Operating Voltage (V + toV~) 



9.7V 



ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGES (Unless Otherwise Specified) 
DC Characteristics 



C. L.„ 1 

5>ymbol 


Parameter 


isunuiiions \iMoie 0/ 


Amooo-L, 


AmooD-m 


Units 


v 0S 


Input Offset Voltage 




H5 ^ lUUli, 1 A - 2D O 

r s < loon 


3.0 
3.5 


2.0 
3.0 


m\/ MAY 

mV MAX. 


AV 0S /AT 


HVKF dyt; 1 cl I ipcl dLUIc ^/Ucl I I L. 1 1: J 1 L 

of Input Offset Voltage 


R s < 100J2 


10 


10 


mvAc MAX. 


'OS 


Input Offset Current 


25°C < T A < T A ( max .) 
T A - T A (min.) 


1.0 
1.3 


1.0 
1.6 


(lA MAX. 
,iA MAX. 


IB 


Input Bias Current 


25°C < T A < T A (max .) 
T A = T A (min.) 


10 

13 


10 
16 


M A MAX. 
,iA MAX. 


V C M 


Input Voltage Range 




+2.7, -3.3 


+2.7, -3.3 


V MIN. 


CMRR 


Common Mode Rejection Ratio 


RS < 10012, -3.3V <S V c m < +2.7 V 


80 


SO 


dB MIN. 


SVRR 


Supply Voltage Rejection Ratio 


R S < 10012 


70 


70 


dB MIN. 


V H 


Output HIGH voltage 


l|_ = -1.0mA, Vs = Vs (min.) 


2.7 


2.5 


V MIN. 


vol 


Output LOW Voltage 


I L = 10mA, V S = V S (max.) 


0.5 


0.5 


V MAX. 


i+ 


Positive Supply Current 




42 


40 


mA MAX. 


i~ 


Negative Supply Current 




34 


32 


mA MAX. 


P DISS 


Power Dissipation 




415 


400 


mW MAX. 


Switching Characteristics (V + = +5.0V, V - = 


-6.0V, Vj n = 100mV, V d = 5.0mV, Cl = 15pF) (Note 4) 




*pd+ 


Propagation Delay, 
Input to Output HIGH 


T A (min.) < T A < 25°C 
T A " T A (max.) 


12 
15 


12 
15 


ns MAX. 
ns MAX. 


«pd- 


Propagation Delay, 
Input to Output LOW 


TA(min.)<T A «S25°C 
T A = T A (m ax .) 


12 

15 


12 
15 


ns MAX. 
ns MAX. 


At pd 


Difference in Propagation Delay 
between Outputs 


T A - 25°C 


2.0 


2.0 


ns MAX. 



Notes: 2. For the metal can package, derate at 6.8mW/°C for operation at ambient temperatures above +95°C; foi the dual-in-line package, derate at 
9mW/°C for operation at ambient temperatures above 115°C. 

3. Unless otherwise specified, V + = +5.0V, V~ = -6.0V and the Latch Enable input is at V OL . The switching characteristics are for a.100mV 
input step with 5.0mV overdrive. 

4. The outputs of the Am686 are unstable when biased into their linear range. In order to prevent oscillation, the rate-of-change of the input signal 
as it passes through the threshold of the comparator must be at least 1 V/^s. For slower input signals, a small amount of external positive feedback 
may be applied around the comparator to give a few millivolts of hysteresis. 



Propagation Delays as a 
Function of Input Overdrive 

















; L . 15 P f 














Vin 


-- lOOmV 














t pd* 

•pd- 
















fa - 125°C II 


















70"cjl 






































? 












2 


>"C 

I 






















! Mil 















10 100 
OVERDRIVE — mV 



PERFORMANCE CURVES 



Propagation Delays as a 
Function of Temperature 





= 15pF 














V 


- lOOmV 












'pd- 






V od = 2.5mV 






u 
















-10mV - 












\ 
















































iU n 


/ — J 

I 


00 1 




I 









-55 -35-15 5 25 45 65 85 105 125 
TEMPERATURE — °C 



Output Rise and Fall Times 
as a Function of Temperature 



1 

C L - 15pF 














10 


t-90% 








































J!>fc TIM 


















k 


















FAL 





































-55 -35-15 5 25 45 65 85 105 125 
TEMPERATURE - °C 



2-28 



Am687-Am687A 

Dual Voltage Comparators 



Distinctive Characteristics 

• 8.0ns MAXIMUM PROPAGATION DELAY AT 5mV 
OVERDRIVE 

• Complementary ECL outputs 

• bQ£l line driving capability 



• 100% reliability assurance testing in compliance with 
MIL-STD-883. 

• Electrically and optically inspected dice for assemblers 
of hybrid products. 

• Available in the hermetic dual-in-line package. 



FUNCTIONAL DESCRIPTION 

The Am687 and Am687A are fast dual voltage comparators con- 
structed on a single silicon chip with an advanced high-frequency 
process. The circuits feature very short propagation delays as well 
as excellent matching characteristics. Each comparator has differ- 
ential analog inputs and complementary logic outputs compatible- 
with most forms of ECL. The output current capability is adequate 
for driving terminated 50fi transmission lines. The low input offsets 
and short delays make these comparators especially suitable for 
high-speed precision analog-to-digital processing. 

The comparators are similar to the Am685 high-speed comparator 
but have been designed to operate from a 5V positive supply 
(instead of 6V), dissipating less power than two Am685's. Separate 
latch functions are provided to allow each comparator to be inde- 
pendently used in a sample-hold mode. The Latch Enable inputs 
are intended to be driven from the complementary outputs of a 
standard ECL gate. If LE is HIGH and LE is LOW, the comparator 
functions normally. When. LE is driven LOW and LE is driven HIGH, 
the comparator outputs are locked in their existing logical states. If 
the latch function is not used, LE must be connected to ground. 



FUNCTIONAL DIAGRAM 



NON- 
INVERTING 
INPUT 



NON- 
INVERTING 
INPUT 




LATCH ENABLE 



LIC-134 

The outputs are open emitters; therefore external pull-down resistors 
are required. These resistors may be in the range of 50-200H 
connected to -2.0V, or 200-2000fi connected to -5.2V. 



CIRCUIT DIAGRAM (Each Comparator) 



NON-INVERTING 
INPUT 
INVERTING 
INPUT 




Q OUTPUT 
Q OUTPUT 



ORDERING INFORMATION 



Part 


Package 


Temperature 


Order 


Number 


Type 


Range 


Number 


Am687A 


DIP 


-30°C to +85°C 


AM687ADL 


Am687A 


DIP 


-55°C to +125°C 


AM687ADM 


Am687 


DIP 


-30°Cto +85°C 


AM687DL 


Am687 


DIP 


-55°C to +125°C 


AM687DM 


Am687 


Dice 


-30°C to +85° C 


AM687XL 


Am687 


Dice 


-5S°C to +125°C 


AM687XM 



METALLIZATION AND 
PAD LAYOUT 




DIE SIZE 0.056" X 0.056" 



CONNECTION DIAGRAM 
Top View 



OUTPUT I— 

3 r 

OUTPUT I— 
GND Q 



~i Q 

—I OUTPU 



.-c.rr rf 

XV. i- ZJ 11° 



J INPUT 

1NON INV. 
INPUT 



LIC-136 

Note: Pin 1 is marked for orientation. 



2-29 



Am687/687A 



MAXIMUM RATINGS (Above which the useful life may be impaired) 



Positive Supply Voltage 


47 V 


Operating Temperature Range 




Negative Supply Voltage 


-7 V 


Am687-L, Am687A-L 


-30°Cto +85° C 


Input Voltage 


±4 V 


Am687-M, Am687A-M 


-55°Cto+125°C 


Differential Input Voltage 


±6 V 


Storage Temperature Range 


-65° C to +150°C 


Output Current 


30 mA 


Lead Temperature (Soldering, 60 Sec.) 


300° C 


Power Dissipation (Note 2) 


600 mW 


Minimum Operating Voltage (V + to V - ) 


9.7V 



ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGES (Unless otherwise specified) 

Am687A-L Am687A-M 



DC Characteristics Am687-L Am687-M 



Symbol 


Parameter 


Conditions (Note 3) 


Min. 


Max. 


Min. 


Max. 


Units 


Vos 


Input Offset Voltage 


R s < 100 0, T A = 25°C 

R s < i oo n 


-3.0 
-3.5 


+3.0 
+3.5 


-2.0 
-3.0 


+2.0 
+3.0 


mV 
mV 


" " OS' n ■ 


Average Temperature Coefficient 
of Input Offset Voltage 


r~ < 1 nn o 


-10 


+ 10 


-10 


+ 10 


mV/°C 


'os 


Input Offset Current 


2S°C< T A < T A(max ) 
T A = T A(min.) 


-1.0 
-1.3 


+ 1.0 
+ 1.3 


-1.0 
-1 .6 


+1.0 
+ 1 .6 


mA 
liA 


l B 


Input Bias Current 


25°C < Ta =S T A ( m , v 1 

T A = T A(min.) 




10 

13 




10 
16 


MA 

ma 


V CM 


Input Voltage Range 




-3.3 


+2.7 


-3.3 


+2.7 


V 


CMRR 


Common Mode Rejection Ratio 


R s < 100 «, -3.3 =S V CM < +2.7 V 


80 




80 




dB 


SVRR 


Supply Voltage Rejection Ratio 


R~ < moo a v.. = + 5% 

ng *: i uu it, tivg — ISA 


70 




70 




dB 






T A = 25 C 


-0.960 


-0.810 


-0.960 


—0.81 




VOH 


Output HIGH Voltage 


T A = T A(min.) 


-1.060 


-0.890 


-1.100 


-0.920 


V 






T A = T A(max.) 


-0.890 


-0.700 


-0.850 


-0.620 


V 






T A = 25° C 


-1.850 


-1.650 


-1.850 


-1.650 


V 


Vol 


Output LOW Voltage 


T A =T A(min | 


-1.890 


-1.675 


-1.910 


-1.690 


V 






T A = T A ( m ax.) 






-1.810 


-1.575 


V 


1+ 


Positive Supply Current 




35 




32 


mA 




Negative Supply Current 






48 




44 


mA 


P DISS 


Power Dissipation 






485 




450 


raW 


Switching Characteristics (Vi n = lOOmV, V oc | 


= 5mV) 












<pd+. «pd- 


Propagation Delay, Am687A 


T A (min.) < T A < 25°C 
T A = T A ( max ) 




8.0 
10 




8.0 
12.5 


ns 
ns 


«pd+. 'pd- 


Propagation Delay, Am687 


TAlmin.) <T A < 25°C 
T A = T A(max.) 




10 
14 




10 
20 


ns 
ns 




Minimum Latch Set-up Time 


T A = 25° C 




4.0 




4.0 


ns 



Notes: 2. Derate at 9mW/°C for operation at ambient temperatures above + 1 1 5°C. 

3. Unless otherwise specified V + = +5.0V, V"" = -5.2V, V T = -2.0V, and R L = 50SI; all switching characteristics are for a 100mV input step with 
5mV overdrive. The specifications given for V os , l os , l B , CMRR, SVRR, t pc j+ and t pc j_ apply over the full Vrjiy range and for ±5% supply voltages. 
The Am687 and Am687A are designed to meet the specifications given in the table after thermal equilibrium has been established with a trans- 
verse air flow of 500 LFPM or greater. 



PERFORMANCE CURVES 



Propagation Delays as a Propagation Delays as a Output Rise and Fall Times 

Function of Input Overdrive Function of Temperature as a Function of Temperature 




LIC-137 



2-30 



Am1500 

Dual Precision Voltage Comparator 



tive 



Distinctive Characteristics 



The Ami 500 is functionally, electrically, and pin-for- 

pin equivalent to the National LH21 1 1 

The Ami 500 is a dual 111, but requires 25% less 

power than two 1 1 1 comparators 

Output Drive - 50V and 50mA 

Input Bias Current — 150nA max. 



Input Offset Voltage - 4.0mV max. 

Differential Input Voltage Range — ±30V 

100% reliability assurance testing in compliance with 

MIL-STD-883 

Available in Hermetic Dual-ln-Line or Hermetic Flat 



FUNCTIONAL DESCRIPTION 

The Am1500 is a voltage comparator featuring low input 
currents, high differential and common mode voltage ranges, 
wide supply voltage range, and outputs compatible with all 
bipolar and MOS circuitry. The inputs and outputs can be 
isolated from system ground, and the output can drive loads 
referred to ground or either supply. Strobing and offset 
balancing are available and the outputs can be wire-ORed. 



FUNCTIONAL DIAGRAM 
(each half) 



COLLECTOR 
OUTPUT 



NON-INVERTING 
INPUT c 



INVERTING,-, 

INPUT 




EMITTER 
BALANCE/ OUTPUT 
STROBE 



CONNECTION DIAGRAMS 
Top Views 



Dual In-Line 



Flat Package 



v*-aC 
emitter output — a[[ 
non inverting input - aq 

INVERTING INPUT -Af^ 
V~C 5 
BALANCE - BQ 6 
BALANCE/STROBE -8^1 
COLLECTOR OUTPUT - b |~L 



9, , 9 



(COLLECTOR OUTPUT - A 
BALANCE/STROBE - A 
BALANCE — A 
□INVERTING INPUT - B 

□ NON-INVERTING INPUT - B 

□ EMITTER OUTPUT - B 
Hv*-B 



EMITTER OUTPUT - A[ 
NON INVERTING INPUT -AC 
INVERTING INPUT -AC 
v~ C 

BALANCE - BC 
BALANCE/STROBE - BC 
COLLECTOR OUTPUT - BC 



]N.C 

^COLLECTOR OUTPUT — A 

] BALANCE/STROBE - A 

^BALANCE —A 

] INVERTING INPUT - B 

3 NON- INVERTING INPUT - E 

DEMITTER OUTPUT - B 

JV-B 



Note: Pin 1 is marked for orientation. 



ORDERING INFORMATION 



Part 

Number 



Package 
Type 



Temperature 
Range 



Order 
Number 



Am1500C 



Ami 500 L 



Am1500M 



TO-99 
Hermetic DIP 

TO-99 
Hermetic DIP 

Hermetic DIP 
Flat Pak 



C to +70 C 
0°Cto+70°C 

-25°Cto+85°C 
-25°C to +85°C 

-55°Cto+125°C 
-55°Cto+125°C 



AM1500DC 
AM1500FC 

AM1500DL 
AM1500FL 

AM1500DM 
AM1500FM 



2-31 



Ami 500 

MAXIMUM RATINGS 



Voltage from V + to V - 


36V 


Voltage from Collector Output to V - 




Am1500M, L 


50V 


Am1500C 


40V 


Voltage from Emitter Output to V - 


30V 


Voltage between Inputs 


±30V 


Voltage from Inputs to V - 


+30V, -0V 


Voltage from Inputs to V + 


-30V 


Power Dissipation (Nota i) 


500mW 


Dlltnilt Shnrt Pirrnit Hnratinn 


1 sec 


nnoratinn Tomnflratiiro Ranno 




Am1500M 


-55°Cto+125°C 


Ami 500 L 


-25°Cto+ 85°C 


Am1500C 


0°Cto+ 70°C 


Storage Temperature Range 


-65°Cto +150°C 


Lead Temperature (soldering, 10 sec) 


300°C 



ELECTRICAL CHARACTERISTICS 

(T^ = 25°C unless otherwise specified) (Note 2) 

Am1500M 



Parameter (see definitions) 


Conditions 


Am1500C 
Min. Typ. 


Max. 


Min. 


Am1500L 
Typ. 


Max. 


Units 


Input Offset Voltage (Note 3) 






2.0 


7.5 




0.7 


3.0 


mV 


Input Offset Current (Note 3) 






6.0 


50.0 




4.0 


10.0 


nA 


Input Bias Current (Note 3) 






100 


250 




60 


100 


nA 


Response Time (Note 4) 


R|_ = 500fi to +5V, V E = 


200 


200 


ns 


Supply Current— Positive (Note 5) 
—Negative (Note 5) 






3.9 
2.6 


7.5 
5.0 




7.0 
4.8 


9.5 
7.5 


mA 


Voltage Gain 




200 




200 




V/mV 


Saturation Voltage 


V in < -5.0mV, l c = 50mA 
V in < -10mV, l c = 50mA 




0.75 


1.5 




0.75 


1.5 


V 


Output Leakage Current 


V in > +5.0mV, V C to V E = 50V 
V in > +1 0m V, V C to V E = 40V 




0.2 


50.0 




0.2 


10.0 


nA 


The Following Specifications Apply Over The Operating Temperature Range 


Input Offset Voltage (Note 3) 




10.0 


4.0 


mV 


Input Offset Current (Note 3) 




70.0 


20.0 


nA 


Input Bias Current (Note 3) 




300 


150 


nA 


Saturation Voltage 


V in <S -6.0mV, l c = 8.0mA 
V in < -10mV, l c = 8.0mA 




0.23 


0.40 




0.23 


0.40 


V 


Output Leakage Current 


V in > +6.0mV, V c to V E = 50V 






0.1 


0.5 


MA 


Input Voltage Range 




±13 


±14 




±13 


±14 




V 


Supply Current— Positive (Note 5) 
—Negative (Note 5) 


T A =+125°C 






mA 



Notes: 1 . For the Flat Package derate at 6.5mW/°C for operation at ambient temperatures above 83°C, and the Dual-ln-Line at 9mW/°C for operation at 
ambient temperatures above 95°C. 

2. Unless otherwise specified, these specifications apply for V + - + 1 5V, V~ = -15V, V E = -15V, and R L at collector output = 7.5kf2 to +15V. 

3. The offset voltage, offset current and bias current given are the maximum values required to drive the collector output to within 1 V of the supplies 
with a 7.5kfi load. These parameters define an error band and take into account the worst case effects of voltage gain and input impedance. 

4. The response time specified (see definitions) is for a 1 00m V input step with 5.0mV overdrive. 

5. The Ami 500 supply current is the sum of the supply currents required by each side. 



2-32 



Ami 500 




Common Mode Limits 



Transfer Function 



Response Time For 
Various Input Overdrives 



REFERRED TO SUP 


S LY 


VOL 


T AC 


ES 




- Aml500M,L 












- Aml500C 


































































> 













































































































COLLEC1 
OUTPU 
- R L =1 


OR 






V 4+ =50V 


T 






A-M 

— 


: ■ ■ 


1 L 


Ml. 














_ 


























= 40V_ 












Aml500C 


i 

-EMITTE 
OUTPU 
R L = 60 


r"^ 

r 



































































— Zj 





-55 -35 -15 5 25 45 65 85 1 05 1 25 
TEMPERATURE-^ 




DIFFERENTIAL INPUT VOLTAGE- mV 



Response Time For 
Various Input Overdrives 



Response Time For 
Various Input Overdrives 



Response Time For 
Various Input Overdrives 






Supply Current 



Supply Current 



Leakage Current 















posn 

OUTP 


IVE S 
UT LO 


JPPLY 




















NEGATIV 


E SUP 


>LY 






1 

POSITIV 
OUTPUT 


I 

SUPP 
HIGH 


I 

_Y 












T A" 


25"C 



±5 +10 
SUPPLY VOLTAGE -V 



















_ A 


n1500M, 


L 












=A 


nl5C 


oc 






: 












PO 
OU 

■ 


ITI\ 
TPU 


E S 

r lc 


J PPL 


Y 










w- 










































N 




: GA 


TIV 


E SU 


PPL' 


r 








POSITIVE 
ni itpi it i- 


SUPPLY 
IGH 
























5V 



-55 -35 -15 5 25 45 66 85 105 125 
TEMPERATURE-"C 




45 65 85 105 125 

TEMPERATURE -°C LIC-141 



2-33 



Ami 500 



APPLICATIONS 




Offset Balancing Increasing Input 

Stage Current* 

Iks 




LIC-144 L1C-145 

'Increases input bias current and common-mode slew rate bv a factor of 3. 
* 'Typical input current = 50pA with inputs storbed OFF. 



2-34 



LH2111/2211/2311 

Dual Precision Voltage Comparator 



Distinctive Characteristics 



The LH21 1 1/221 1/231 1 are functionally, electrically, 
and pin-for-pin equivalent to the National LH2111/ 
2211/2311 

The LH2111 is a dual 111, but requires 25% less 
power than two 1 1 1 comparators 
Output Drive - 50V and 50mA 
Input Bias Current - 150nA max. 



Input Offset Voltage — 4.0mV max. 

Differential Input Voltage - ±30V 

100% reliability assurance testing in compliance with 

MIL-STD-883 

Available in Hermetic Dual-ln-Line or Hermetic Flat 
Packages 



FUNCTIONAL DESCRIPTION 

The LH21 1 1/221 1/231 1 are voltage comparators featuring 
low input currents, high differential and common mode 
voltage ranges, wide supply voltage range, and outputs com- 
patible with all bipolar and MOS circuitry. The inputs and 
outputs can be isolated from system ground, and the output 
can drive loads referred to ground or either supply. Strobing 
and offset balancing are available and the outputs can be 
wire-ORed. 



FUNCTIONAL DIAGRAM 
(Each Half) 



COLLECTOR 
OUTPUT 



NON-INVERTING 
INPUT 




EMITTER 
BALANCE/ OUTPUT 
STROBE 



CONNECTION DIAGRAMS 
Toi 



fop Views 



Dual-ln-Line 



Flat Package 



V--AC 
EMITTER OUTPUT - A{2 
NON INVERTING INPUT - a[_. 
INVERTING INPUT AQ 
v-C 
BALANCE - 
BALANCE /ST HOBE - B[_. 
COLLECTOR OUTPUT - B^ 



□ COLLECTOR OUTPUT - A 

□ BALANCE STROBE - A 
»LANCE - A 

Inverting input - B 

□ non inverting INPUT - B 

□ EMITTER OUTPUT B 

3v-» 



EMITTER OUTPUT - AfJ 
NON INVERTING INPUT - AC 
INVERTING INPUT -AC 

rc 

BALANCE - BC 
BALANCE/STROBE - BC 
COLLECTOR OUTPUT - BC 



□ N C 

"JCOLLECTOROUTPUT - A 

□ BALANCE/STROBE - A 
□BALANCE -a 

□ INVERTING INPUT - B 

□ NON INVERTING INPUT - B 

□ EMITTER OUTPUT -B 





ORDERING INFORMATION 




Part 
Number 


Package 
Type 


Temperature 
Range 


Order 
Number 


LH2311 


DIP 
Flat Pak 


0°C - +70° C 
0°C-+70°C 


LH2311D 
LH2311F 


LH2211 


DIP 
Flat Pak 


-25°C- +85°C 
-25° C- +85° C 


LH2211D 
LH2211F 


LH2111 


DIP 
Flat Pak 


-55°C-+125°C 
-55°C - +125°C 


LH2111D 
LH2111F 



2-35 



LH2111/2211/2311 
MAXIMUM RATINGS 



Voltage from V + to V - 




36V 


Voltage from Collector Output to V - 
LH2111/LH2211 

Ln/o I I 




50V 

HU V 


Voltage from Emitter Output to V 




OU V 


V UI layc UClvvCCI I I 1 l^JU lo 




±30V 


Voltage from Inputs to V~ 
Voltage from Inputs to V + 




+30V, -0V 
-30V 


Power Dissipation (NoteD 




500mW 


Output Short Circuit Duration 




10 sec 


Operating Temperature Range 
LH2111 
LH2211 
LH2311 




-55° C to +125°C 
-25°Cto +85°C 
0°Cto +70°C 


Storage Temperature Range 




-65°Cto +T50°C 



Lead Temperature (soldering, 10 sec) 300°C 



ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise specified) (Note 2) 

LH2111 

LH2311 LH2211 
Parameter (see definitions) Conditions Min. Typ. Max. Min. Typ. Max. Units 



Input Offset Voltage (Note 3) 






2 


7.5 




0.7 


3.0 


mV 


Input Offset Current (Note 3} 






6.0 


50.0 




4.0 


10.0 


nA 


Input Bias Current (Note 3) 






100 


250 




60 


100 


nA 


Response Time (Note 4) 


R L = 50012 to +5V, V E =0 




200 






200 




ns 


Supply Current— Positive (Note 5) 
—Negative (Note 5) 






3.9 


7.5 




7.0 


9.5 


mA 




2.6 


5.0 




4.8 


7.5 


Voltage Gain 






200 






200 




V/mV 


Saturation Voltage 


V||\| < -5mV, Ifj = 50mA 
V| N <: -10mV, l c « 50mA 










0.75 


1.5 


V 




0.75 


1.5 








Output Leakage Current 


V| N > +5mV, V c to V E = 50V 
V| N >+10mV,V c to V E =40V 










0.2 


10.0 


nA 




0.2 


50.0 








The Following Specifications Apply Over The Operating Temperature Ranges 


Input Offset Voltage (Note 3) 








10.0 






4.0 


mV 


Input Offset Current (Note 3) 








70.0 






20.0 


nA 


Input Bias Current (Note 3) 








300 






150 


nA 


Saturation Voltage 


V|N < -6mV, Ifj = 8mA 
V|n < -10mV, l c = 8mA 










0.23 


0.40 


V 




0.23 


0.40 








Output Leakage Current 


V| N > +6mV, V C to V E = 50V 










0.1 


0.5 


M A 


Input Voltage Range 




±13 


+ 14 




+ 13 


±14 




V 


Supply Current— Positive (Note 51 
—Negative (Note 5} 


T A = 1 25°C 










4.8 


6.4 


mA 










3.2 


4.4 



Notes: 1. For the Flat Package derate at 6.5 mW/° C for operation at ambient temperatures above 83°C, and the Dual-ln-Line at 9 mW/°C for operation at 
ambient temperatures above 95°C. 

2. Unless otherwise specified, these specifications apply for V + = 1 5V, V~ = -1 5V, V E = -15V, and R L at collector output = 7.5k£2 to + 15V. 

3. The offset voltage, offset current and bias current given are the maximum values required to drive the collector output to within 1 V of the sup- 
plies with a 7.5kfi load. These parameters define an error band and take into account the worst case effects of voltage gain and input impedance. 

4. The response time specified (see definitions) is for a 1 00m V input step with 5m V overdrive. 

5. The LH21 1 1 supply current is the sum of the supply currents required by each side. 



2-36 



Input Bias Current 



Input Offset Current 



Offset Error 



% 400 



< 200 



£ 100 

















— i 

v s 


«*1 


5V_ 








• — - 














RAIDED! 




s 














\ 






























- L 

- L 






LH 


r 

.-t 








-1^1 1 1/ 
42311 

I 


OR 


.1AL 


F 














- s 



















5 -15 5 25 46 65 85 105 125 
TEMPERATURE-^ 





A- 




1 „ 


B 1 ■ 


5V- 




- LH2 


11/ 


LH221 


'S 




1 - 






- LH2311 
































> 
















































RA 


SED 
















"NC 


RM 




















a 





















































































-55 -35 -15 5 25 45 65 86 105 125 
TEMPER ATU RE - = C 




100k 1M 
INPUT RESISTANCE- n 



Response Time For 

Common Mode Limits Transfer Function Various Input Overdrives 




■ 1 — ' 1 1 1 1 1 ■ ' =— - — b I 1 1 1 1 1 1 1 1—1 

-65 -35 -15 5 25 45 65 85 105 125 -1 -.5 .5 1 ^ 0.2 0.4 0.6 0.8 

TEMPER ATU RE -°C DIFFERENTIAL INPUT VOLTAGE-mV - TIME- us 



Response Time For Response Time For Response Time For 

Various Input Overdrives Various Input Overdrives Various Input Overdrives 




TIME-us TIME-^s TIME-m 



Supply Current Supply Current Leakage Current 




2-37 



LH21 11/221 1/2311 



APPLICATIONS 




•Increases input bias current and common-mode slew rate by a factor of 3. 
"""Typical input current = 50 pA with inputs strobed OFF. 



2-38 



A NEW HIGH-SPEED 
COMPARATOR THE Am685 

By Jim Giles and Alan Seales 





IN 1 RODUCf ION 

Modern electronic systems require more and more that 
operations be performed in a few nanoseconds so that the 
delay of the complete system, which may be very complex, be 
held to a minimum. There are abundant logic circuit elements 
available that meet this criterion: gold-doped TTL, Schottky 
TTL, and emitter-coupled logic (ECL), listed in descending 
order of propagation delay. Where it is necessary to interface 
from the analog world to the input of a logic system, or to 
detect very low-level logic signals in the presence of heavy 
noise, a high-speed precision comparator is needed. If such a 
comparator had a propagation delay less than 10ns, it could 
replace costly and complex circuitry that designers are now 
forced to use in very high-speed analog-to-digital converters, 
data acquisition systems, and optical isolators, as well as make 
possible many applications hitherto considered unfeasible. It 
could also be used as a sensitive line receiver or sense amplifier, 
in 100MHz sample and hold circuits, and in very high- 
frequency voltage-controlled oscillators. 

The basic requirements fflr a high-speed precision comparator 
are few and well-defined: good resolution (high gain), high 
common-mode and differential voltage ranges, 'outputs com- 
patible with standard logic levels, and, above all, very fast 
response to signal levels ranging from a few millivolts to several 
volts. The industry workhorse, the 710, has come close to 
meeting these requirements, and except for the most demand- 
ing applications, its 40ns propagation delay is adequate. A 
survey of presently available monolithic IC comparators 
(Table I) shows that there is really none that meets the 
requirements of very high-speed systems. The newer TTL-out- 
put circuits offer only marginal improvement over the 710 
when measured under identical conditions of large input pulse 
and small overdrive, and the ECL-output comparator, although 
faster, has such poor resolution that it can be used only for 
large input signals. Advanced Micro Devices felt there was a 
need for a family of linear devices to fill the needs of very 
high-speed systems, with the first circuit being a precision 
comparator with less than 10ns delay. 



Type 
No. 


Logic 
Family 


Propagation 
Delay 


Resolution 


Ami 11 


TTL 


200ns 


0.012mV 


uA710 


TTL 


40ns 


1.4mV 


Am 106 


TTL 


40ns 


0.06mV 


uA760 


TTL 


25ns 


0.5mV 


NE527/529 


TTL 


25ns 


0.5mV 


MC1650 


ECL 


12ns 


30mV 



Table I: Propagation Delays of Available Monolithic IC 

Comparators (lOOmV Input Step, 5mV Overdrive) 



DESIGN OBJECTIVES 



though at present the majority of systems use TTL. Designers 
striving for the highest possible speed will already be using 
ECL in the critical circuit areas of their systems to squeeze the 
last possible nanosecond out of the overall delay. Further, an 
ECL circuit requires only one-third the gain of an equivalent 
TTL circuit for the same resolution owing to its smaller output 
logic swing. This means that lower impedances can be used and 
consequently larger bandwidth realized for the same power 
dissipation. Also, there is no problem interfacing the linear 
input stages with the digital output gate since an ECL gate is 
basically a non-saturating overdriven differential amplifier. 
Properly driving a TTL gate from a linear amplifier is more 
difficult, however, because it requires a large voltage swing 
suitably biased to track the input logic threshold with 
temperature, plus a large peak negative current capability to 
turn off the gate with minimum delay. 

The usefulness and versatility of a comparator can be 
enhanced by adding a strobe or latch function to the circuit. A 
strobe simply forces the output of the comparator to one 
fixed state, independent of input signal conditions, whereas a 
latch locks the output in the logical state it was in at the 
instant the latch was enabled. The latch can thus perform a 
sample and hold function, allowing short input signals to be 
detected and held for further processing. If the latch is 
designed to operate directly upon the input stage— so the signal 
does not suffer any additional delays through the 
comparator— signals only a few nanoseconds wide can be 
acquired and held. A latch, therefore, provides a more useful 
function than a strobe for very high-speed processing. 

The most difficult input signal for a comparator to respond to 
is a large amplitude pulse that just barely exceeds the input 
threshold. This forces the input stage of the comparator to 
swing from a full off (or on) state to a point somewhere near 
the center of its linear range. This exercises both the large-and 
small-signal responses of the stage. If the comparator has less 
than 10ns delay under these stringent conditions, then it 
should be as fast or faster for any other circumstances (see 
Figure 1). The industry standard measurement is with a 



> o 



I 




^ -100mV STEP 

. : *5fnVSTEP 1 


Ti- 




//"^lOOmV STEP. 5r.-V 
// OVERDRIVE 






u 


■yjj 


T, < T 2 < T 3 < 

— T 2 





TIME — 

LIC-154 



In order to achieve the ultimate in speed, it is clear that the 
comparator outputs must be compatible with ECL, even 



Figure 1. Response to step input signals at output of 
a differential amplifier 



A NEW HIGH-SPEED COMPARATOR 



100mV input pulse and an overdrive 5m V above input 
threshold (this was used for the delays given in Table 1 ). Pulses 
larger than lOOmV might be used, but this would multiply 
measurement difficulties, since only a few tenths of a percent 
aberration or ripple in the pulse generator waveform would be 
enough to seriously affect the accuracy of the small overdrive, 
and thus would give misleading results for the propagation 
delay. 

To obtain satisfactory speed for all input signals and particu- 
larly for the worst case measurement conditions, the input 
stage of the comparator must have: 1) wide small-signal 
bandwidth, 2) high slew rate for large signals, 3) minimum 
voltage swings, and 4) high gain. The first requirement can be 
realized by using low-value load resistors, by making every 
effort in circuit design, device geometry and processing to 
minimize parasitic capacitances, and by using transistors with 
the highest fj possible. The second item calls for high 
operating currents as well as minimum capacitance. The last 
two requirements are conflicting, since obtaining high gain 
normally requires a large voltage swing; therefore some means 
of clamping the swing must be used that does not degrade the 
propagation delay. 

The overall gain of the complete comparator must also be high 
because, as illustrated in Figure 1, the propagation delay is less 
if each stage is well overdriven. To ensure that most of the 
input overdrive signal is actually used for overdriving, and not 
consumed in just moving the output from one state to the 
other, the gain error should be no more than about 10% of the 
input overdrive. Therefore, for a 5mV overdrive and an ECL 
output swing of 800mV, the minimum gain must be 1600. It is 
not practical to strive for much higher gain than this because 
the small-signal rise time begins to suffer as the stage gain 
increases. Addition of another stage is undesirable as this also 
adds delay and increases circuit complexity. It must be 
remembered that there is a maximum limit on power 
dissipation that a single integrated circuit package can handle 
adequately, and this consideration must influence the choice 
of operating currents and impedance levels throughout the 
design of the circuit. 

With a figure for the total gain required, it is now possible to 
determine the number of stages and the gain per stage. Since 
the output stage must be ECL-compatible, its design is fixed, 
giving a differential-input to single-ended-output gain of about 
6. This leaves a differential gain of 270 to be provided by the 
remainder of the comparator. This is most efficiently divided 
between two stages, each with a gain somewhat over 16. Both 
stages should be identical, since minimum overall delay time is 
obtained when identical stages are cascaded. 

A factor not yet discussed that affects the accuracy of the 
comparator is its input offset voltage. Unless this is trimmed 
out initially, it must be added to the overdrive in determining 
the worse-case value of input signal for which the propagation 
delay specifications will be met. Even with trimming, the 
temperature drift of high-offset units is typically much greater 
than that of low-offset units. Therefore, it is desirable to have 
low initial offset so that trimming is not necessary, and so that 
the offset temperature coefficient will be good. Also affecting 
the offset voltage and its drift at higher source resistances are 
the input currents. To keep this contribution to the total 
offset low requires high current gains in the input transistors. 
Therefore, obtaining offsets in the 1— 2mV range requires close 
attention to circuit design, mask layout, and very tight process 
control (equivalent to that needed for the high-performance. 



row-frequency op 
kicker of f T s well; 



ational amplifiers), 
ove 1GHz. 



but with the added 



As was mentioned, large common-mode and differential 
voltage ranges are desirable features of a comparator. The 
limits of the common-mode range in a well-designed circuit 
should be close to the supply voltages. Since a high-speed 
comparator will, of necessity, operate at fairly high current 
levels, the supply voltages must be low to stay within the 
package power dissipation limits. As a minimum, the common- 
mode range should be equal to or exceed the differential 
voltage range to take full advantage of the voltage breakdown 
characteristics of the input transistors. The basic differential 
amplifier input stage has a differential voltage breakdown in 
the range of 5 to 6 volts; the design goal for the common 
mode range should thus be at least ±3 volts. 

In summary, the design objectives for a high-speed precision 
comparator are as follows: 

11 propagation delay <10ns measured at 100mV input 
step, 5 mV overdrive 

2) ECL-compatible outputs 

3) latch capability 

4) gain >1 600 

5) input offset voltage <±2mV 

6) common -mode range >±3V 



CIRCUIT DESIGN 

The watchword in designing wideband circuits is simplicity 
— have the fewest possible active devices in the signal path, the 
lowest possible impedance levels, and the lowest possible 
capacitance. The simple, common-emitter differential ampli- 
fier can be designed to approach these ideals with one major 
exception: the deleterious shunting effect of the collector-to- 
base capacitance upon the driving source resistance is multi- 
plied by the voltage gain of the stage (Miller effect). Even 
though the impedance levels will be only a few hundred ohms 
at most, this condition cannot be tolerated if maximum speed 
is to be achieved. The solution is to add an additional pair of 
common-base transistors to form a differential cascode ampli- 
fier (Figure 2). This circuit has all of the performance features 
of a common-emitter amplifier and no feedback capacitance. 



•»1 >«2 



INPUT tO tT Q l °2 



Figure 2. Differential cascode amplifier 



2-40 



A NEW HIGH-SPEED COMPARATOR 



Further advantages of the cascode will become apparent later 
when the latch design is discussed. The only drawback is that 
there are more devices in the signal path, the positive 
common-mode range is reduced, and circuitry has to be 
provided to bias the cascode transistors. 



It is now necessary to provide a means of shifting the signal at 
the output of the cascode (which is very near the positive 
supply voltage) down to a lower voltage to drive the inputs of 
the second stage. The use of PNPs is definitely out because of 
their poor frequency response. This leaves three possibilities: a 
chain of forward-biased diodes, a programmed voltage drop 
across a resistor, or a zener diode. The diode chain is useful for 
level shifts of only a few volts at most, above that, the number 
of diodes gets too large, with a consequent increase in shunt 
capacitance and temperature coefficient. The use of a current- 
source/resistor combination is in the wrong direction for 
keeping impedance levels low. The resistors could be bypassed 
with capacitors, but this would offer only marginal improve- 
ment, since integrated capacitors have a large shunt compo- 
nent to the substrate. Besides, the addition of four capacitors 
(for both stages) would result in a large increase in chip area. 

The zener diode is definitely superior for high-frequency 
applications because its shunt capacitance to ground is low, 
being equal to the collector-to-base capacitance of a transistor. 
It has no capacitance to the substrate, and its dynamic 
resistance is quite low. It does have the disadvantage that the 
level shift is limited to one voltage (6V), which restricts the 
range of power supply variation the circuit can tolerate. In 
addition it requires very tight control of the manufacturing 
process to maintain the matching required. For an input stage 
gain of 16 the zener voltages have to be matched to better 
than 0.25% to produce less than 1mV offset voltage at the 
input. 

As shown in Figure 3, the zeners are buffered from the 
cascode collectors by emitter followers. The pulldown current 
through the zener-fol lower combination must be made large 
enough to discharge the node capacitance when the follower 
swings in the negative direction. The minimum value necessary 
is determined by the node capacitance, the signal swing, and 
the amount of delay that can be tolerated. The amount of 
signal swing can be reduced by adding clamping diodes across 
the collectors oi the cascode. Regular diode-connected transis- 
tors could be used, but would add considerable collector-to- 
substrate capacitance across the load resistors as well as 
base-to-emitter capacitance between them. Schottky diodes, 
on the other hand, require little additional chip area, and are 
very fast. With clamping, some of the common-mode range 
lost when the cascode was added can be regained because the 
cascode transistors can be biased closer to the positive supply 
without fear of going into saturation at the extremes of the 
signal swing. The use of Schottky diodes, however, puts a few 
more gray hairs on the head of the process engineer since he 
has to control another set of characteristics without affecting 
the other parameters. The circuit values given in Figure 3 are 
designed for a minimum differential gain of 16, and a 
minimum negative-going slew rate at the output of the 
level-shifter of 1000V/ms. 

As mentioned earlier the design of the output stage (Figure 4) 
can vary little from that of a standard ECL gate. The 
output emitter followers have to be large enough to handle 
loading by a 50fi transmission line (25mA), yet small enough 
not to add a lot of capacitance that would slow down the 
response Therefore, the transistor design must be as efficient 
as possible with regard to physical size and current-carrying 



2.5mA 2.5mA 
.I l_ 



* > 2.7kU 



lO 1^0, Q 2 pj o 



Figure 3. Basic cascode gain stage 

capacity. Since the input common-mode level to the gate 
varies with changes in the power supplies and resistor 
tolerance, a current source is used to supply the emitters of 
the gate, rather than the usual resistor to the negative supply. 
The design of this current source must be such as to provide 
the correct logical "1" and "0" levels at the output and the 
proper variation with temperature and power supply changes. 
The propagation delays to either output of this gate will be 
equal, whereas they are slightly different in a standard ECL 
gate owing to the additional capacitive loading on the Q 
output caused by the multiple input transistors. 

Implementation of the latch function must be accomplished 
without interfering with the normal comparator operation or 
degrading the speed in any way. It must be as close to the 
input as possible to permit short input signals to be acquired 
and held. One simple method of adding a latch to a differential 



T 



yl — ■ 

IO 1 



t o Q 22^ o 



Figure 4. Output gate 



2-41 



A NEW HIGH-SPEED COMPARATOR 



o — To, 




02 Jl O INPUT 2 




Figure 5. Simple latch circuit 



-tr- 





o 6 



pi o, 



O 1^ °10 Q9 ^| O 



amplifier is shown in Figure 5. A pair of transistors, Q5 and 
Qg, are cross-coupled at the collectors of the input transistors, 
Ql and Q2. The current source I2 is switched on when it is 
desired to enable the latch. If I2 is greater than l-|, the positive 
feedback via Q5 and Q6 will hold the circuit in whatever state 
it was in when the latch was turned on. 

The simple circuit of Figure 5 is not the best for speed because 
of the added capacitance of Q5 and Q6 and the fact that they 
can saturate unless the signal swings are very small. However, it 
can be adapted to the cascode stage quite nicely as illustrated 
in Figure 6. Drive for the positive feedback transistors is taken 
from the level shifters, and the collectors go to the emitters of 
the cascode. With this arrangement there is no significant 
capacitive loading on the gain stage at all. The current source is 
switched by another differential amplifier, Qg— Q-|0, refer- 
enced to the ECL logic threshold voltage. This provides the 
correct input levels for the Latch Enable being driven from a 
standard ECL gate as well as being very fast, since only 
currents are being switched. 

The latch current source (1 2) must be about 1mA greater than 
the input current source (I-]) to ensure positive latching for 
any condition of input signal. Thus, for 5mA in the input 
stage, at least 6mA must be used to power the latch. This 
amounts to a lot of power consumed for a function that some 
users may never even need. However, there is a way to cut the 
latch standby power down to zero; this is accomplished by the 
addition of Q7 and Qg, as shown in Figure 8. 

To understand the function of these transistors, first refer to 
Figure 7. The differential voltage appearing across the emitters 
of the cascode transistors is equal to the input signal (for small 
input signals). This is because the currents through the lower 
pair of transistors in the cascode are equal to the correspond- 
ing currents through the upper pair, and the transistors are 
matched; therefore the differences in base-emitter voltages 
must be equal. Thus, Q7 and Q.Q function as if they were 



| 2.5mA 2.5itia| | 





Figure 6. Cascode with latch 



Figure 7. Cascode with "parallel" transistors 



2-42 



A NEW HIGH-SPEED COMPARATOR 



OUTPUT 1 
O 




° — K 



y\ — 1 



OH 




Figure 8. Complete input cascode stage with latch 

simply connected in parallel with Qi and Q2, as far as the net 
effect at the collector load resistors is concerned. To obtain 
the desired total stage gain, the current I1 can be 2mA and I3 
can be 3mA. 



Now refer to Figure 8. With the latch enable HIGH, Qg will 
be switched on and the 3mA current source will be supplied to 
the parallel transistors, Q7— Qg. The comparator functions 
normally, and no current is used up in the latch. When the 
latch enable goes LOW, I2 will be switched through Q-|o to the 
positive feedback transistors, robbing 3mA from the gain stage 
and giving it to the latch. The latch current is now 1mA 
greater than the input stage current, but the total current 
required is still only 5mA. As with the latch transistors, the 
collectors of the parallel transistors are connected to the 
emitters of the cascode, so no additional capacitance is added 
across the load resistors. This places the requirement on Q7 
and Qg that they maintain their high fx at zero collector-to- 
base voltage. 

The use of the parallel transistors has the added bonus that the 
input bias currents are decreased by more than a factor of two, 
thus reducing their influence on the offset voltage. The 
penalty paid is that all three pairs of junctions (Q-|— Q2, 
Q3— Q4 and Q7— Qg) add equally to the input offset. Once 
again, the processing must be carefully controlled to keep the 
overall offset within the 2mV goal. 

The complete circuit of the comparator is given in Figure 9. It 
includes some additional refinements as well as the DC biasing. 
The drive for the latching transistors is taken from the emitters 
of the second cascode rather than from the level-shifting 
zeners. This removes their input capacitance from the level 
shifter and also ensures that Q10 cannot saturate. A resistor 
(Rg) is included to center the common-mode voltage at the 
input to the gate within its dynamic range; this prevents 
saturation of the gate or its current source over the expected 
range of signal swing, temperature drift and supply voltage 
variations. A separate ground is used for the output emitter 
followers so that heavy loading at the output will not couple 
back into the remainder of the circuit. The DC bias chain for 
the current sources is referenced to ground and the negative 
supply, so the output logic levels will track those of other ECL 
circuits connected to the same negative supply. The current 
sources are designed to stay constant with temperature, which 
keeps the open-loop gain high at elevated temperatures 
O1000 at +125°C), and thus helps to maintain good 
propagation delay. 




LATCH 
ENABLE 



ZT°7 



f 240 fi T 240 n 



"16 ._ 

is 



OUTPUT OUTPUT 



Figure 9. Complete schematic of the Am685 comparator 

2-43 



A NFW HlfiH-SPFFD COMPARATOR 

result in an input structure that has three pairs ot transistors, 

the matching of- which determines the offset voltage. This 
dictates that the matching of Vbe shall be extremely good 
between the transistors in each pair in order to meet the 2mV 
maximum offset voltage target. For the speeds necessary the 
transistor f j has to be in the region above 1 GHz, so high-fre- 
quency performance can not be compromised. The slew rate 
of the input stage has to be very high for acceptable response 
with large input signals. This is achieved by high operating 
current and low stray capacitances. It is very desirable to keep 
both the input bias current and the input offset current very 
low so that the impedances in the source voltages do not 
introduce intolerable input voltage errors. It would be possible 
to use a Darlington-connected input stage to achieve these low 
currents, but the penalty exacted in offset voltage, offset 
voltage drift, and propagation delay is unacceptable, so high 
current-gain transistors that match extremely well are needed. 
The problems are thus centered on achieving very well- 
matched transistors with high beta and high fy. 

As previously mentioned, it is desirable in a comparator to 
have a wide common-mode voltage range and high power- 
supply rejection ratio. This is facilitated by using Schottky 
diodes to clamp the collector-to-collector swings in the first 
two stages. Schottky diodes can be fabricated simply by 
making a window in the oxide over the N-type epitaxial layer 
and using the same evaporated aluminum as is used for the 
interconnects (see Figure 10). The contact potential between 
silicon and aluminum causes a potential barrier to the flow of 
electrons. Making the metal positive lowers this barrier, 
allowing electrons to pass over it by virtue of their thermal 
energy. This process is essentially the same as thermionic 
emission. Since these electrons are majority carriers, Schottky 
diodes show extremely fast turn-off characteristics, desirable 
in this application. Why the Schottky diode is so attractive is 
that the forward voltage necessary to produce a given current 
may be several hundred millivolts less than that required to 
produce the same current in a p-n junction diode of about the 
same size. It can thus be used as a "clamp" to prevent a 
bipolar transistor from saturating, when connected from 
collector to base so as to prevent the forward voltage of the 
collector-base diode from rising to a level sufficient to cause 
appreciable current flow in the collector-base diode. This is the 
common application in Schottky TTL circuits. 

In the ECL comparator the use is different. Here they are used 
back-to-back to limit the differential voltage swings between 
the collectors in both the first and the second stages. 
Connected in this way the reverse voltage seen by one 
Schottky diode is equal to the forward voltage drop of the 
other diode. Because this voltage is so small reverse leakage is 
not a great problem. In the simple Schottky diode structure, as 
described above, the reverse leakage is high. Most of this 
leakage current is generated at the perimeter of the metal, 
where there is an electric field concentration. In order to 
reduce this field the metal is extended all around the opening 
in the oxide, overlaying this oxide. Spacing the metal from the 
silicon in this way reduces the field and hence the leakage. In 
applications where low leakage is critical, the use of a P+ guard 
ring is called for, but this carries with it extra capacitance, so 
in view of the fact that the reverse voltage is so low the guard 
ring technique was discarded for this application. Even so, the 
diodes used in the comparator have low leakage characteristics 
with a breakdown at about 45V. 





1 \ t / P BASE' f* N + P+ \ 


j SINKER <= 




V V [ / N EPITAXIAL MATER IAL \ 




^ * [ N* BURIED LAYER 

Pt \ 


) 




ISOLATION 




ISOLATION 


P SUBSTRATE 







Figure 10. Cross section of transistor and Schottky 
diode showing sinker and P+ base contact 
enhancement 

At the very high speeds being considered, much effort has to 
go into reducing capacitances and resistances. Thinning down 
the epitaxial layer to the minimum required to sustain the 
voltages encountered is of benefit in two ways: 1) the 
collector-isolation sidewall area is reduced, lowering the 
collector-to-substrate capacitance; 2) the collector-series resist- 
ance is reduced. The two major contributions to collector- 
series resistance are the resistance of the epitaxial material 
between the emitter and the buried N+ layer, and the 
resistance of the epitaxial layer between the collector contact 
and the buried layer. However, the first resistance is subject to 
reduction by conductivity modulation during operation of the 
device and thus is less important than the second term. The 
second term can be made very small by using a "sinker", 
which is a high concentration N-type diffusion from the 
surface, through the epitaxial layer, to the buried N+ layer. 
Contact to the collector is then made to the surface of the 
sinker, (see Figure 10) 

Collector-to-base capacitance is held low by using very small 
dimensions and by using a relatively high epitaxial layer 
resistivity. The latter also serves to 'reduce the collector-to- 
substrate capacitance. A further reduction in collector-to-base 
capacitance results from using a shallow, high sheet-resistivity 
diffusion for the base. However, this raises the base resistance, 
both because the bulk resistance from the contact to the active 
base region is increased and because the specific contact 
resistance is increased. These resistances may be reduced by 
depositing P+ regions under the base contact areas after the 
main base diffusion. 

A compromise has to be made in selecting emitter width. 
Large emitters are desirable for Vp,E matching, but very small 
emitters are essential for high fy. A stripe emitter, ,25-mil 
wide and 1-mil long, was chosen as optimum. A difference 
in width, between two otherwise identical emitters, of 
.01-mil will be sufficient to cause an offset voltage of 1 mV. 
From this, it can be seen that the photolithography must be 
extremely carefully controlled, since the offset voltages of 
three pairs of transistors are summed to give the total offset of 
the comparator. Because the emitters are so narrow the normal 
procedure of making a contact cut inside of the emitter cannot 
be used. Instead, the emitter oxide is simply dissolved in 
hydrofluoric acid immediately before the aluminum evapora- 
tion in order to expose the emitter. As a consequence, the 
lateral distance between the metal and the emitter-base 
junction is very small, being equal to the lateral diffusion of 
the emitter. This means that the sintering process must be 
carried out at a temperature lower than is customary in linear 
circuit manufacture in order to avoid short-circuiting the 



2-44 



emitter-base junction by lateral migration of aluminum. An 
additional reason for lowering the sintering temperature is to 
avoid penetration of aluminum down through the emitter and 
base, causing emitter-to-collector shorts. 

The requirement for high current gain, for low input bias 
currents, necessitates narrow base widths. Emitter-to-collector 
shorts can be a problem in these shallow, narrow-base 
structures. The probability of shorting can be minimized by 
careful cleaning procedures and by proper emitter doping 
levels. Keeping the emitter doping level low also reduces the 
magnitude of the "emitter dip" effect, whereby the diffusion 
coefficient of the boron in the region under the emitter is 
greatly increased by the lattice strain caused by the emitter, 
resulting in the running-on of the base under the emitter, 
making it very difficult to achieve a narrow base width. 

An area that is neglected in digital circuit processing, because 
high beta is not necessary, but which is of major importance in 
linear processing, is the control of surface conditions. It high 
current gains are to be realized, both the surface area of the 
emitter-base-depletion region and the surface recombination 
velocity must be minimized. The former implies that ionic 
contamination, such as sodium ions, must be eliminated and 
that the surface state charge density, Qss, should be made as 
low as possible. The surface recombination velocity is propor- 
tional to the fast surface state density and so can be minimized 
by making this density very low. These three goals; low ionic 
contamination, low Qss and low fast surface state density are 
achieved by using the well known techniques of MOS and 
linear circuit processing, such as annealing in an inert 
atmosphere and proper choice of sintering cycle. 

In the interests of minimum capacitance, the metal inter- 
connects are designed to be narrower than is usual in linear 
circuits. Special etching techniques have to be employed in 
order to reproduce these narrow lines reliably. These lines can 
be seen in the photomicrograph of Figure 11. 



Figure 11. Photomicrograph of the Am685 comparator 
PERFORMANCE 

The primary design objective for the comparator was to obtain 
under 10ns propagation delay for large input signals with small 
overdrive. It should then be as fast or faster for any other 
input conditions. The performance of the Am685 compara- 
tor for a 100mV step input at various overdrives is shown in 
Figures 12 and 13. The propagation delay is measured from 
the time the input step crosses the input threshold voltage to 
the time the output crosses the logic threshold voltage. The 
input threshold voltage (i.e., the offset voltage) was adjusted 
for the figures so that the delay can be simply measured by 



A NEW HIGH-SPEED COMPARATOR 




Figure 12. Tpd -"1" for lOOmV step input and various 
overdrives (input = 5mV/cm, output = 
200mV/cm) 





M 




mm 


m 


■ 








mm 


m 






mm 


mm 






■ 




mm 


vm 












Mil 






I 


















NEB 



















Figure 13. Tpd —"0" for lOOmV step input and various 
overdrives (input = 5mV/cm, output = 
200m V/cm) 



counting up 5, 10, or 20m V from the bottom of the input 
pulse. The input pulse, therefore, is displayed on a magnified 
scale to facilitate this measurement and also to illustrate the 
purity of input signal required to make accurate measurements 
at millivolt overdrives. 

For a 100mV input step and 5mV overdrive, the propagation 
delay for a logical "0" is 6.3ns and for a logical "1" is about 
300ps less. A graph of delay as a function of overdrive is given 
in Figure 14. It was previously stated that any other condition 







7a 


= 25°C 










V|N 


= lOOmV STEP 








8 


















6 






OU1 


PUT 






d - * 


















7" " 


4 


















T enb 








-T p 






2 


T apt 


LA 


CH 












^= 















5 10 15 20 

OVERDRIVE - mV LIC-163 



Figure 14. Delay times as a function of input overdrive 




2-45 



A NEW HIGH-SPEED COMPARATOR 




Figure 15. Response to symmetrical input signals 



of input signal should give faster response (refer back to 
Figure 1). This is demonstrated by Figure 15, which illustrates 
the response of the comparator to symmetrical inputs ranging 
from ±5mV to ±500mV. The speeds are at least 1 to 2ns faster 
than for small overdrives. 

Figure 16 shows how the delay time varies with temperature. 
The adverse effects of resistor and gain changes at elevated 
temperatures result in an increase in delay from 6.3ns at 25°C 
to 8.4 ns at 85°C and 10.4 ns at 125°C. All of the above data 
were taken with output loads of 50f2 connected to —2.0V. 
For lighter loading (such as 500f2 to -5.2V) the output rise 
and fall times and propagation delays are all slightly faster. 

The usefulness of the latch is directly related to how quickly it 
can be enabled following a change in the input signal. The 
input signal must be present long enough to pass through the 
first stage of the comparator before the latching transistors can 
act upon it. The minimum time that the input must be present 
before the latch can be turned on is defined as the latch enable 
time. This is measured as the minimum time that must elapse 



o 



V )N ■ lOOmV STEP 








5mV OVERDRIVE 








i 




| T pd 


-"0 








ou 


TV 


r 








d- 
























































-LATCH 


























-T» 












— 







-55 -15 25 65 105 
TEMPERATURE - °C 



LIC-164 



Figure 16. Delay times as a function of temperature 

between the time the input step crosses the input threshold 
voltage and the time the latch enable input crosses the logic 
threshold voltage for which the comparator outputs will 
assume the correct states. 



. . . 

r 

1 < 


IKK 




mm 




MM 




■nan 

rnvmrn 

mrnrnm 


mm 




1 \L . 

■ 


1r 









Figure 17. Latch enable time and latch aperature time 
for 100mV input step, 5mV overdrive 
(input = 5mV/cm, latch = 200m V/cm, 
output = 400mV/cm) 



The performance of the latch function is illustrated by 
Figure 17. The input signal is the standard 100mV step with 
5mV overdrive and is in the direction to cause the output to 
switch from a logical "0" to a logical "1". The delay of the 
latch signal relative to the input is adjusted until the output 
just switches to a "1"; this is the latch enable time and under 
these conditions is 1.8 ns. The difference between the latch 
timing for which the output just barely switches and when it 
does not switch is the latch aperture time; this is about 500ps 
for 5mV overdrive. The performance of the latch with input 
overdrive and temperature generally follows that of the 
propagation delays (Figure 14 and 16). 

The overall performance of the Am685 is summarized in 
Table II. It is apparent from the table and the previous 
discussion that the device is ideally suited for applications 
where both precision and high speed are required, such as in 
analog-to-digital converters, data acquisition systems, and 
optical isolators. The device is the first in a family of new 
wideband linear integrated circuits designed to meet the 
requirements of very high-speed systems. 















Propagation Delay 




(100mV step, 5mV overdrive) 


Bi5ns MAX 


Input Offset Voltage 


2.0mV MAX 


Average Temperature Coefficient 




Of Input Offset Voltage 


10/iV/°C MAX 


Input Offset Current 


1.0uA MAX 


Input Bias Current 


10/jA MAX 


Common Mode Voltage Range 


±3.3V MIN 


Common Mode Rejection Ratio 


80dB MIN 


Supply Voltage Rejection Ratio 


70dB MIN 


Positive Supply Current 


22mA MAX 


Negative Supply Current 


26mA MAX 



Table 1 1 : Performance Characteristics of the Am685 
Comparator (Ta = 25°C, V+ = 6.0V, 
V" = -5.2V, R|_ = 50n to -2.0V) 



2-46 



A NEW HIGH-SPEED COMPARATOR 



THE A-D APPLICATION 

Very fast, precision, analog-to-digital conversion stands to 
benefit considerably from the availability of a fast comparator. 
As the block diagram of a fast 10-bit converter in Fig. 18 
shows, a typical rapid conversion technique may resemble the 
use of feedforward compensation in an operational amplifier. 

The analog input signal is sampled at the beginning of a con- 
version period and fed to a fast five-bit a-d converter, which 
provides the first five most significant bits of the output. 
These five bits also drive a companion d-a converter, which 
must be accurate to better than 10 bits. The output of the d-a 
converter is a replica of the input signal, quantized to five bits. 
This is compared with the actual input signal stored in the 
sample-and-hold amplifier. The difference between the two 
analog levels is the remaining part of the input signal that must 
be quantized. This difference is amplified and applied to an- 
other five-bit a-d converter to provide the five least-significant- 
bits of the final output. 

Typical five-bit a-d converters may consist of 31 106-type 
comparators connected to the signal source and referenced to 
the full-scale input in steps of 1/32. The output of each com- 
parator goes into a latch, and the latch outputs are decoded by 
three stages of TTL gages to develop the five-bit digital output. 

Typical propagation delays are 40 ns for the comparators, 
22 ns for the latches, and 10 ns for the decoding, resulting in a 



total delay of 80 ns. Average settling time for the five-bit d-a 
converter and the difference amplifier together comes to about 
200 ns, and the settling time for the input sample-and-hold 
amplifier is 70 ns. Thus, the over-all conversion time for this 
10-bit converter amounts to 430 ns. 

Substitution of the high-speed ECL comparator for the 106 
type in each of the five-bit converters leads to a significant im- 
provement in propagation delay. The typical delay of the com- 
parator is about 6.5 ns, and no external latch is required. With 
ECL it is possible to wire-OR outputs, so only one level of de- 
coding gates is required. Allowing 1.5 ns for the gates, the 
total five-bit conversion time is only 8 ns — a tenfold improve- 
ment over the existing circuit. 

If the latch function of the comparators is used as the sample- 
and-hold for the first five-bit converter, the sample-and-hold 
can be put in parallel with the first quantization step, as shown 
by the dotted lines in Fig. 18. This eliminates its settling time 
from the over-all delay of the system. With the new compara- 
tor, the total 10-bit conversion time drops to 216 ns, with over 
90% of the delay attributable to the d-a converter and the dif- 
ference amplifier. Moreover, the availability of an 8 ns five-bit 
converter should provide the impetus to improve the slower 
sections of the system. A 10-bit a-d converter with a delay 
under 100 ns is not an extravagant prediction. 




10BIT 

DIGITAL 

OUTPUT 





5-aiT 

AD 
CONVERTER 

















If the standard 106-type comparator in this a-d converter is replaced by the 10 ns device, a tenfold improve- 
ment in speed is possible. What is more, the ECL makes possible both wired-OR outputs and a single level 
of decoding for gates. 

LIC- 165 



Figure 18. Analog to digital. 
2-47 



Am685/Am686/Am687 
DESIGNING WITH HIGH SPEED 
COMPARATORS 

By Leonard Brown 



INTRODUCTION 

The Am685, Am686 and Am687 are a family of high-speed 
sampling comparators capable of detecting low-level signals of 
the order of 5-1 OmV in 12-1 5ns over the temperature range 
-55°C < T A < 125°C. The Am686 is fully TTL-compatible 
and complementary outputs are available generated from a 
true differential output stage assuring a maximum output 
skew of under 2ns at 25°C. The Am685 and Am687 are single 
and dual ECL-compatible versions, respectively, and have 
output skews of less than 1ns. A high-speed latch is incor- 
porated in the input stage permitting input signals to be 
acquired in 4.0ns maximum for the ECL versions and 6.0ns 
for the TTL device. 

Applications of the devices are not limited to high-speed 
designs as the combination of the excellent DC input charac- 
teristics, availability of true differential outputs and the 
latch function permit unique solutions for slower speed 
applications where the response time of the comparators can 
be considered negligible. 

THE SAMPLING COMPARATOR 

The sampling comparator may be visualized as a conventional 
voltage comparator with the provision that the outputs may 
be latched into the logic states determined by the input signal 
conditions existing at the time of application of the latch 
signal. This is achieved by incorporating the latch circuitry 
in the input stage of the device. The minimum latch enable 
pulse width is necessarily less than the propagation delay of 
the device and, therefore, the comparator can be unlatched 
for a fraction of its propagation delay (4.0ns for the Am685). 
The outputs will then change in accordance with the input 
conditions existing at the time of the latch signal. Note: It 
is impossible for the comparator to oscillate under these 
conditions. 

If the latch function is not used, the device operates as a 
conventional voltage comparator. 

BACK TO BASICS 

Comparators are designed to have both high gain and large 
bandwidth. This creates instability problems or oscillations 
when the device outputs are in the transition region. The 
tendency of a device to oscillate is a function of the layout, 
(poor layout increasing the amount of feedback caused by 
parasitic capacitance) and the source impedance of the circuit 
employed (The higher the source impedance the less parasitic 
coupling is necessary to cause oscillation.) It is mandatory 
with comparators of the gain and bandwidth of the Am685, 
Am686 and Am687 to ensure that power supplies are well 
decoupled, lead lengths are kept as short as possible, and 
wherever possible (especially in the case of the Am686), a 
ground plane should be employed. 

In addition to reducing the effects of stray capacitance, a 
ground plane substantially reduces the possibility of the 



output current spike coupling back to the inputs through the 
ground lead when the TTL output stages switch. 

The minimum slew rate at which the input signal must cross 
the threshold region to prevent oscillation, regardless of the 
particular layout parasitics, may be determined by applying a 
DC voltage to the input until the circuit just commences to 
oscillate and increasing this voltage until the oscillation ceases. 
The minimum necessary input slew rate is then given by 
AV/tpd MIN, where AV is the input voltage required to 
prevent oscillation and t pc j MIN is the minimum propagation 
delay of the comparator. 

The minimum slew rate will be found to be a function of 
source impedance and source impedance mismatch. 

The curves of Figures 1 and 2 show the minimum slew rate 
for the Am686 as a function of source impedance and source 
impedance mismatch. 



10 




SOURCE RESISTANCE — £2 UC-166 

Figure 1. Minimum Slew Rate Versus 
Source Resistance (TO -5). 



I.O 



> 







































V 



10 100 1000 

SOURCE RESISTANCE - fi LIC-167 

Figure 2. Minimum Slew Rate Versus 
Source Resistance (DIP). 



2-48 



Am685/Am686/Am687 



1 

'C TO -5 




C, = 2 


.OpF 




y dip 










'B' D 








'A' & 'B'^Ni 
TO~~51 ^ 


V DIP 







10 100 1000 

SOURCE RESISTANCE - SI LIC-168 

Figure 3. Minimum Slew Rate Versus 

Source Resistance (TO— 5 & DIP). 

It can be seen that unbalanced sources dramatically effect the 
minimum input slew rate required. Note that for optimum 
performance, the source impedance seen by the comparator 
should be both DC and AC balanced to reduce the differential 
feedback to a minimum. 

The effect of an AC unbalanced source is seen especially on 
the Am686 as when the output switches, the output current 
spike is coupled back to the input. This can be eliminated by 
forcing the AC unbalance to result in positive feedback, which 
may be achieved by decoupling the inverting input or applying 
positive feedback via a 2-4pF capacitor from the Q output to 
the non-inverting input. 

The curves of Figure 3 illustrate the improvement in minimum 
slew rate when a small amount of positive feedback is em- 
ployed by virtue of a 2pF feedback capacitor. 

OPTIMUM SOURCE CONDITIONS <Cf = OpF) 

With low source impedances « 5052), the majority of the 
feedback between the output and the input occurs internal 
to the device. As the source impedance is raised, external feed- 
back increases through the parasitic feedback capacitance 
until, at high source impedances, the external feedback 
dominates. This explains the anomolous characteristics of the 
minimum slew rate curves and suggests that the optimum 
source resistance for the device is between 300 and 500f2 
for unbalanced sources and is approximately 100012 for a 
balanced source. 

OPTIMUM SOURCE CONDITIONS (Cf = 2pF) 

With a source impedance of 100S2, the minimum slew rate is 

0. 15./MS for the DIP configuration and 0.02V/MS for the 
TO-5. For balanced sources the minimum slew rate is 0.03V//JS 
for Rs > 100J2 and for a source impedance between 1 kS2 
and 3kft, the minimum slew rate is <0.02V//us regardless of 
impedance, DC imbalance or package type. 

The use of the feedback capacitor is recommended when: 

1. The input slew rate is within a factor of 2 greater than the 
minimum theoretical slew rate. 

2. System constraints do not permit optimisation of layout 
and lead lengths. 

3. Unbalanced souice impedances are used (it is not always 
possible to provide input conditions which are both DC and 
AC balanced). 



A FAMILY AFFAIR 

It must be stressed that the concepts discussed concerning 
source imbalance and minimum input slew rate apply to all 
devices in the family. The Am686 was highlighted as it is more 
sensitive to layout constraints and parasitic feedback because 
of its significantly higher voltage gain. 

Similarly all of the applications which follow may be imple- 
mented with any device in the series provided due caution is 
exercised with regard to the different output logic levels. 

THE RELAXATION OSCILLATOR 

The principal problems in the design of a classical relaxation 
oscillator are: 

1. The variation in potential to which the energy storage 
device (normally a capacitor) is charged. 

2. The variation in the threshold level at which the capacitor 
is to be discharged. 

3. The variation inherent in the sensor element (normally a 
comparator) in detecting equivalence between the threshold 
level and the capacitor's instantaneous potential. 

The variations are all functions of both time and temperature 
and are the primary causes of frequency drift, symmetry error, 
and jitter. 

By taking advantage of two unique properties of the Am686, 
a relaxation oscillator may be designed to eliminate the first 
two problems and reduce the third to a second-order effect for 
oscillation frequencies from 1MHz to 30MHz. 

The true differential output stage of the comparator ensures 
that the Q and Q outputs change within 1-2ns of each other. 
This feature ensures that the outputs can never be in the same 
logic state instantaneously, either HIGH or LOW, and that the 
only time they are equal in voltage is when traversing the logic 
uncertainty levels. This property permits the design of a 
threshold setting circuit that varies in accordance with the 
charging voltage applied to the timing capacitor. Therefore, 
any change in charging potential is automatically compensated 
by a corresponding change in threshold level. 

Second, the combination of the short propagation delay 
7-10ns, the minimum difference in propagation delay between 
outputs and the stability of these delays with temperature 
assures square wave symmetry of better than 1% @> 1MHz and 
5% @ 25MHz and a frequency stability of 1% @ 10MHz and 
4% @ 25MHz. 

The above statements are true from device to device and over 
the operating temperature range of — 55° C to +125°C. Over 
the industrial temperature range, a factor of two improvement 
should be obtained. 

CIRCUIT THEORY (Fig. 4) 

Assuming the circuit is in an oscillating mode, the voltage 
appearing at the non-inverting terminal will alternate between 
Vx and Vy where: 

Ri 

V X = , (Vqh - V 0L ) + V 0L and 



v Y = 



(R1 +R2> 
R2 



(VqH-VoJ + Vol 



(R1 + R2> 

WhenV+|N = Vx, tne timing capacitor C will be charging 
towards Voh. and when V+in = Vy, the timing capacitor will 
be discharging towards VqL- 



2-49 



Am685/Am686/Am687 





H M h 



Figure 4. Circuit Design. 



After the voltage on the capacitor equals the voltage on the 
non-inverting input, a finite time will elapse before the output 
of the circuit changes, during which time (the propagation 
delay of the Am686) the capacitor will continue to charge 
towards VfjH. or discharge towards Vol- 

Therefore, the capacitor will charge to a voltage 



V A = Vqh - e 



-t PHL /CR 



(VQH -V X ) 



and discharge to a voltage 

V B =V OL + e- t ' > LH/CR. (VY _ VoL) 

where tpHL ar| d *PLH = propagation delay of the Am686 from 
the inputs to the output changing from HIGH - LOW and 
LOW - HIGH respectively. 

The time to charge from Vb to Va which is the positive half 
cycle is given by: 



t+ = CR In 



Vqh 



Vqh - V A 



substituting for V A and Vg 

,+ = CR1n[(-5l + 1)e t PHL/CR_ 1] 
R2 



Similarily the negative half cycle is given by: 

V A - V 0L 
t- = CR In — — 

v B - Vol 
t- = CRHi[(-^+1)e t PLH/CH_ 1 ] 

Note: The only assumptions are: 

1. < v oh - v ol> of the Q output = (Vqh - Vol) of t ne Q 
output. 

2. Offset voltage and offset current errors are negligible. 
3 e t PLH /CR x e -t PHL /CR = 1 

The only factor affecting pulse width variation is, therefore, 
tpHL ar| d tpLH- As tpHL > tPLH by 1-2ns, it is therefore antici- 
pated that t+ will be marginally greater than t~. 



MINIMUM OPERATING FREQUENCY 

For the Am686, it is specified that the minimum slew rate 
at the input to insure that the device will not oscillate in the 
transition region is IV/us. This will determine the minimum 
operating frequency of the circuit. 

The rate of change of voltage on the timing node is given by: 



3v Vo 
p = — = — x e 
3t CR 



-t/CR 



In the circuit, 

a) Vo = Vqh - V B (assuming positive ramp) 
and 

b) t = CR 1n [(— + 1) e^HL/CR 

R 2 

As the slew rate is only critical in determining the lowest 
operating frequency, it may be assumed that e tpHL '' CR = 1 
(CR »> tpH L >; therefore, Vo = V 0H - V B « V 0H - V Y 



Vo = (Vqh-Vol) 



Ri + R 3 



and, t = CR In — 
R 2 



■P = — 



8v 

at 

AV 



(Vqh - Vol) 
CR 
R 2 



R, + R 2 Ri 



CR R-i + R 2 
where, AV = (Vqh - Vol) 
The minimum operating frequency 

1 



f M IN - 



2 CR 1n 



R 2 



substituting 



AV 

CR = — 



R2 



P (R1/R2 + D 
fMIN %AV X lnRl /R 2 



p R, + R 2 



The expression for minimum frequency indicates that an 
optimum ratio of R!/R 2 exists that is independent of any 
particular RC time constant which may have been chosen. 



2-50 



Am685/Am686/Am687 



The ratio may be determined by differentiating f M!N with 
respect to R,/R 2 . 



d f MIN 

*1 
3 — 
R 2 



2AV 



Ri Ri R, 

1n — _(— + 1)/ — 

R2 R2 ^2 ) 

m Rl ,2 
(1n — ) 

R 2 



R2 



1 Rl 

1n — _ 1 

P R 2 

2AV * lt Ri 2 
(1n — ) 
R 2 



3 F_ 

Setting 3 R, 
R2 



= 



R, R 2 
R 2 Ri 



R 2 



1 



1n 1 

R 2 



= 3.59112 



R 2 



Therefore, the lowest frequency the oscillator will perform 
consistent with the 1V/^s constraint is: 



fMlN " - 



1 x4.6 



x 3.5 1n 3.6 



: ,513MHz 



D.C. OFFSET ERRORS 

The presence of DC errors resulting from the bias and offset 
currents and offset voltage of the Am686 will cause the V Y 
and V x thresholds to be both shifted either positive or negative 
by an equal amount 6V where SV is the sum of all such errors. 

The magnitude of these effects may be calculated as follows: 

When the capacitor is discharging - 




Figure 5. 



V(t) = V <> 



-t/CR 



dv 
dt 

5t, 



_J_ V o*- t/CR 
CR 

SV 



1 

— V (t ) 
CR W 



-SVCR 



CR 



5t 2 = 

v (t 2 ) 

At - Negative Pulse Width Change = 

v (t,) -V( tl ) 
812-61, = SVCR !3i 

v (tl , v (t2) 

AsV x = V tl .V Y = V t2 

SVCR (V Y -V X ) 

At- = 

V X V Y 

Similarly for the positive pulse 




Figure 6. 



V (t ) = Vo (1 -e t/CR ) 

1 

Whence, dv/dt = — (Vo - V( t |) 
CR 



•St, 



St, 



SVCR 
" Vo - V t , 

SVCR 



Vo - V t2 



Positive Pulse Width Change At+ = 5t 2 - St, 
1 1 



■ SVCR 



Vo-V (t2 ) Vo-V (tl ) 
In the circuit V t2 = V x ,V tl = V Y ,Vo-V x = V Y 

V X -V Y 



At+ = SVCR (- ) = SVC 

\V Y V x / 



V X V Y 



= -At- 



.'. Offset errors do not affect the frequency of oscillation, only 
the symmetry of the waveshape. 



2-51 



Am685/Am686/Am687 



SYMMETRY ERROR 

At+ - At- V Y 

Symmetry S = x 100% where T = CR 1n — 

2T V X 



2At+ 

S = x 100% 

2T 

_ 5VCR (V x - V Y ) 



i 



CR 1n V Y /V X 



Symmetry is worse for maximum value of V x -V Y . Maximum 
value of V x - V Y occurs when and R 2 are arranged for 
minimum operating frequency, i.e., R-| /R 2 = 3.6 

Substituing SV = 5mV 

V X /V Y =3.6 

1 3.6 
V X V Y = — V OH x — V 0H 
4.6 4.6 

V h = 3-5V and neglecting Vol 

Symmetry is < 0.38% 

Note: 1. For any given ratio of : R 2 (i.e., V x and V Y ), 
offset voltage Symmetry error is independent of 
frequency. 

2. Symmetry improves to .33% @ R-| :R 2 = 2.5 

EXTENDING LOW FREQUENCY PERFORMANCE 

If it is necessary to extend the lower limit of the oscillation 
frequency, a small amount of positive feedback may be intro- 
duced by connecting a 2-4pF capacitor between the Q output 
and the non-inverting input. This will decrease the minimum 
input slew rate required and enable oscillation frequencies of 
1kHz to be achieved without spurious oscillations occuring 
on the rising or falling edges of the waveform. At frequencies 
below 1MHz, it is not necessary to take into account any 
potential frequency shift this additional feedback introduces. 
(Above 1MHz, it is not necessary to use this additional 
feedback.) 

PERFORMANCE CHARACTERISTICS: 



% 

♦4- 

«- 


f = 5.0MHz 

■--a^rT^i — - 


—\ 1 1 

-55^^^^25^^^0^^^25 5 

-4 - 


) 75^^.100^. 125 T CASE - = C 
>^f- 10MHz 
f = 20MHz 

LIC-173 



75 X ,00 -^ 125 T CASE-" C 
f = 5.0MHz 




Figure 8. Change in Symmetry Versus Case Temperature. 





nmo 












KHZ 


lOOmS 200n 


C 



Figure 9. Output Waveform at 1.0 MHz. 



Figure 7. Percentage Change in Frequency Versus 
Case Temperature. 




Figure 10. Output Waveform at 10MHz. 



2-52 



Am685/Am686/Am687 




Figure 1 1 



Output Waveform at 24 MHz and Expan 
Falling Edge Exhibiting <50ps Jitter. 




Figure 12. Change in Pulse Width and Jitter from 25 C to 
125°C,f = 10MHz. 




Figure 13. Expanded Fall Time Showing Change in Pulse 
Width from 25°C to 125°C, f = 1.0MHz, 
(Jitter ~ 300ps). 



I 




Figure 14. Circuit and Component Values used in 
Obtaining Performance Characteristics. 



LOW LEVEL PULSE DETECTOR 



+5.0V O Wv 




-±T R A = lOkH, C c = 47pF, B B = 390kH ^ 



TRANSFER FUNCTION 



10 12 20 



MAXIMUM INPUT PULSE WIDTH 

MINIMUM INPUT PULSE WIDTH 

MAXIMUM REP. RATE (20ns, 20mV) CONTINUOUS 

MAXIMUM REP. RATE (20ns. 20mV) CONTINUOUS w/o R A , B C C 



' R| = 5.1kfi 

r 2 = ion 

fl 3 = R 4 = 1 kn 
C, =470pF 
C. - 2pF 



> 25MHz 
s 12MHz 



Figure 15. 



CIRCUIT OPERATION 

The input resistance is essentially determined by R4 which was 
chosen to be 1kS2 on the basis that most sources would not 
be unduly loaded at this value and consequentially higher 
values would make the circuit excessively prone to oscillation. 
To minimize bias current errors, the inverting input is connec- 
ted to the lOmV reference source (R1 and R2) through an 
equal-valued resistor (R3). 

Positive feedback is provided by Cf which provides a 50- 
60mV, 3-4ns pulse, significantly improving the switching time 
and narrowing the uncertainty region for pulses just in excess 
of the 10mV threshold. 



2-53 



Am685/Am686,Am687 



Capacitor Ci provides A-C coupling and thus isolates the 
circuit from slowly varying signals which may be superimposed 
on the signal to be detected. Such is the case for a detector 
sensing the output from a fibreoptic cable receiver. The A C 
coupling imposes additional constraints; namely, the repetition 
rate and duty cycle of the input signal. 

The signal which is seen by the non-inverting terminal and 
then compared to the reference is not simply the peak value 
of the input pulse but the peak value less the average D.C. 
value of the input signal. 

Assuming a 20mV input pulse, 20ns wide and repeated every 
20ns, the signal seen across R4 will be as follows: 



mnn 



U¥LP 



Note: The response time of the feedback path must be the 
same as the input network; i.e., RaCc = ^4^-1 ' n ° r der for 
the feedback to follow rapid changes in repetition rate or 
duty cycle. 

PRECISION MONOSTABLE 

Commercially available one-shots encounter problems in the 
generation of narrow « 100ns) pulses. Namely, there is a 
significant delay between the input pulse and the output 
pulse of the order of 20ns and the resultant output pulse 
width is highly temperature dependent due to the variation in 
internal delays with temperature. Second, the input pulse must 
be of the logic level for the type of logic employed in the 
design - TTL, DTL, RTL, etc. Thus, the circuits are incapable 
of responding to low-level input signals in the millivolt range. 

The Am685 series of sampling comparators can be employed 
in the design of a custom one-shot to overcome both of these 
problems. 

Figure 18 shows the design of a monostable employing the 
Am686 to generate precision output pulses in the 20-100ns 
range and the values shown are for a 50ns pulse width. 



Figure 16. 

By the ninth pulse, the peak signal will be 15.2mV dropping 
to 14.6mV by the end of the pulse; thus, after a pulse train 
of ~10 pulses, the detector will not detect the incoming signal. 

Additionally, consider the case of a 20ns pulse repeated every 
60 nanoseconds. 




Figure 17. 

The peak signal at the input will now be only 15mV; there- 
fore, the maximum repetition rate consistent with providing a 
5.0mV overdrive is 1/80nsor 12.5MHz. 

Therefore, the circuit will only successfully detect 20mV, 20ns 
signals if: a) the pulse train is < 10 pulses or b) the repetition 
rate< 12MHz. 

To compensate for these problems, a DC feedback signal is 
generated by Ra, Rb ar| d Cc wmcn adjusts the reference level 
accordingly. 

RA and Cq form a low-pass filter that gives a maximum DC 
level of 1.7 volts at a 1:1 duty cycle. At this duty cycle, it 
is required to reduce the reference level by 5mV to maintain 
adequate overdrive. Rb and R4 form an attenuator and the 
DC voltage level returned to the non-inverting input = 1.7V 
x R4/(R4 + Rg) = 4.3mV. Using this network permits the 
circuit to work up to 25 MHz, or better than a 1 : 1 duty cycle 
and removes the limitation imposed by the input A-C 
coupling. 




IVi+Vol/Voh/VRa+Rb^ Ri' J 



Figure 18. 

The timing diagram illustrates the circuit operation. 




A 



J | 




Figure 19. 



2-54 



Am685/Am686/Am687 



The circuit triggers on the negative-going edge of the input 
pulse and the Q output switches high. The output signal is 
attenuated by Ra and Rb to keep the coupled pulse inside 
the common mode limits of the device. The output remains 
high until the voltage on the non-inverting input reaches the 
threshold set by Ri and R2- In order that the pulse width be 
independent of the input pulse amplitude, it is important to 
make the input time constant small compared to the desired 
output pulse width. 

A unique feature of the circuit is the use of the differential 
outputs of the device to set the threshold, V^h thus providing 
temperature compensation and a reduction in pulse width 
variation from device to device. 

Diode Di shortens the recovery time of the timing capacitor 
and permits retriggering 30ns after the end of the pulse with 
less than a 5% change in pulse width. 

Complete Isolation of the input signal and the timing network 
may be achieved by employing the latch function as shown 
below: 

I 1 




LIC- 182 



Figure 20. 

When the input signal exceed VRf=p,the output will switch and 
latch the comparator in the high state. When timing capacitor 
charges to the latch threshold, the latch will become disabled 
and the output will switch back to zero, providing the input 
is now below Vref- 
The advantages of this approach are: 

1. No interaction between input signal and timing capacitor. 

2. The input threshold set by Vref is independent of the 
timing threshold. 

Thus, the input threshold can be varied from millivolts to volts. 
A practical circuit is shown: 




LIC-183 



Figure 21. 



The circuit is applicable for situations where accuracy of 
trigger threshold is important, a large variation in input signal 
level is expected or the input signal level is low. Timing 
accuracy (pulse width) is independent of the amplitude of the 
input pulse, but the output pulse width varies with tempera- 
ture in accordance with the temperature dependence of the 
latch threshold (~ 3.0mV/°C for Am686). 

APPLICATIONS REQUIRING INPUT HYSTERESIS 

Comparators are frequently employed in systems where it 
is required that the transfer function contain a defined amount 
of hysteresis. Conventional comparators employing positive 
feedback can be used to generate hysteresis as shown below: 




Figure 22. 

Drawbacks of this technique include: 

1. Response time of hysteresis loop> comparator propagation 
delay 

2. Hysteresis varies with VoH and VOL changes 

3. Hysteresis is not centered about zero unless an additional 
reference is used. 

By utilizing the latch function on the Am685, Am686 and 
Am687, hysteresis can be inserted in a manner to overcome 
these drawbacks; namely: 

1. Response time of hysteresis loop « propagation delay 

2. Hysteresis not affected by VoH ar| d Vol changes 

3. Hysteresis is symmetrical about zero. 

4. Full input differential capability maintained over complete 
common mode range. 

The hysteresis is obtained by applying a slight bias to the latch 
inputs. The technique is illustrated in the test circuit shown 
for the Am687. 




Figure 23. 



2-55 



Am685/Am686/Am687 



The hysteresis is essentially symmetrical about zero and 
between ±5 and ±50mV of hysteresis can be generated before 
the relationship between the latch voltage and the thresholds 
become too sensitive. 

The hysteresis is independent of changes in the positive supply 
voltage and the input common mode range and varies only 
with changes in temperature and negative supply voltage. 



-HYSTER1SIS tiV 



+HYSTER1SIS I 



-100 -80 -60 -40 -20 




DIFFERENTIAL LATCH VOLTAGE IVpl - mV 



L1C-186 




Figure 25. Change in Hysteresis Versus Change in 
Negative Supply Voltage. 




Figure 24. Input Hysteresis Versus Latch Voltage, T A = 25°C. Figure 26. Change in Hysteresis Versus Case Temperature. 

COMPARATOR PERFORMANCE SPECIFICATIONS 



Am687 



FUNCTIONAL DIAGRAM 



ELECTRICAL CHARACTERISTICS OVER THE OPERATING 
TEMPERATURE RANGES (Unless Otherwise Specifiedl 
DC Characteristics 



Am687AL 
Am687-L 



Am687A-M 
Am687-M 




l»TCH ENABLE 



The outputs are open emitters; therefore external pull-down resistors 
I be in the range of 5O-20OP. 
connected to -5.2V. 



connected to -2.0V, or 



CONNECTION DIAGRAM 
Top View 




Symbol 


Parameter 


Con in ion; (Nok3I 


Min. 


Max. 


Min. 


Max. 


Units 




Input Offset Voltage 


R s < 10011. T A = 25°C. 


-3.0 


+3.0 


-2.0 


+2.0 


mV 




R s H 100H 


-3.5 


+3.5 


-3.0 


+3.0 


mV 


-W os MT 


Average Temperature Coefficient 
of Inpui Offset Voltage 


R s «. 10011 


-10 


+ 10 


-10 


+ 10 


u vrc 


'OS 


Input Offset Current 


35 n C<T A <T A(mal ,.| 
T A =T A(mil , | 


-1 
-1.3 


+ 1.0 
♦IJ 


-1.0 
-1.6 


+ 1.0 
+ 1.6 


■A 
m* 


•b 


Input Bin Current 


25Dc < T A.< T A(max.] 
TA=T A(m , n .) 




10 
13 




10 
16 


«A 
«A 


V C M 


Input Voltage Range 




-3.3 


+2.7 


-3.3 


+2.7 




CMRH 


Common Mode Rejeciion Ratio 


H s <; 10011, -3.3* V CM < +2.7 V 


80 




80 




tie 


SVRH 


Supply Voltage Rejection Ratio 


R s < 10011. AV S = t.5% 


70 




70 




i!B 






T A = 25"C 


-0.960 


-0.810 


-0.960 


-0.810 




v OH 


Output HIGH Voltage 


T A -T A(mio ., 


-1.060 


-0 890 


-1.100 


-0.920 










-0.890 


-0.700 


-0.850 


-0.620 








T A = 25*C 


-1.850 


-1 .650 


-1.850 


-1 650 


V 




Output LOW Voltage 


T A "T A(m , n , 


-1 890 


-1.676 


-1.910 


-1.690 








T* -T Alma ,., 


-1 .825 


-1.625 


-1.810 


-1.575 






Positive Supply Current 






35 




32 


mA 


r 


Negative Supply Current 






48 




44 




P DISS 


Power Dissipation 






485 




450 




Switching Characteristics ,V in = 100 mV. v od 


5mV) 














Propagation Delay. Am687A 


TAt m inJ< T A <25X 
T A " T A(max 1 




8.0 
ID 




SO 
12.5 






Propagation Delay. Am687 


TAlmm.l < T A < 25'C 

Ta =T fl ( m3( .) 




10 




10 
20 






Minimum Latch Set-up Time 


T A - 25" C 




J 




4.0 





Note* 2. □■rate ei 9mW/°C for opera. 
3. Unleo oiri»r*»i«a •pacified \ 
5mV overdrive The ipec-fica 
Tha Am687 at 



ereria-.tt.ci are for a 100m v .r 



2-56 



COMPARATOR PERFORMANCE SPECIFICATIONS (Cont.) 



Am685/Am686/Am687 



Am685 



FUNCTIONAL DIAGRAM 



ELECTRICAL CHARACTERISTICS OVER THE OPERATING 
TEMPERATURE RANGES (Unless Otherwise Specified) 

ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE RANGES (Unless Oihwwise Specified! 
DC Characteristics Am6!&L AmHi5 .M 

Symbol Parameter (see definitions) Condition! (Note 31 Min. Max. Min. Max. Units 




LATCH ENABLE 



The outputs are open emitters, therefore external pull- 
down resistors are required. These resistors may be in 
the range of 50-20012 connected to -2.0 V, or 200- 
2000fi connected to —5.2 V. 



CONNECTION DIAGRAMS 
Top Views 




LIC-121 



vos 


Input Offset Voltage 


R S <: 100 fl, T A = 25"C 

r s v i oo n 


-2.0 
-2.5 


+2-0 
+2-5 


-2.0 
-3.0 


+2.0 
+3.0 


mV 


iV QS MT 


Average Temperature Coefficient 
of Input Offset Voltage 


r s < ioon 


-10 


+10 


-10 


+10 


ItVfiC 


'OS 


Input Offset Current 


T A -25"C 


-1.0 


+1.0 


-1.0 


+1.0 


m 


>■ 


Input B:a= Current 


T A - 25° C 




" 




10 


uA 


"in 


Input Resistance 


T A -25'C 


6.0 




6.0 




ktl 




Input Capaciunce 


T A -25-C 




3.0 




3.0 


pf= 


V C M . 


Input Voltage Range 




-3 3 


+3.3 


-3-3 


+3.3 






Common Mode Reaction Ratio 


R S < 100 ft. -3.3 < Vcm < +3.3 V 












SVRR 


Supply Voliisie Reiitc.iion FOno 


R S < 100ft, av s - i5% 


70 




70 




rJB 


VoH 


Output HIGH Voltage 


T A - 25" C 
Ta ■ TMndnJ 
Ta " TAtmn.l 


~?060 
-0.890 


^0890 
-0.700 


~°\ 'too 

-0.850 


_____ 
-0.620 


V 


vol 


Output LOW Voltage 


T A - 25°C 
TA = T A ( min>) 
TA-^Atofisatl 


-1 .850 
-1.890 
-1.825 


-1 .650 
-1 .675 
-1.625 


-1 .850 
-1.910 
-1.810 


-1.650 
-1.690 
-1 575 


v 


i- 


Positive Supply Current 






22 




22 


mA 




Negative Supply Current 






26 




36 


mA 


P DISS 


Power Dm. pat ion 






300 




300 




Switching C 


haracteristics {v jn = lOOmV, V d = 5mV) 












<pd+ 


Input to Output HIGH 


TAImm.l * T A < 25*C 
T A " T Aimax.) 


4.5 

5.0 


6.5 
9.5 


u 

s.s 


6.5 
12 




'pd- 


Input to Output LOW 


TA(min.l*T A «;25 s C 


4.5 
5.0 


6.5 
9.5 


4.5 

5.5 


K8 
12 






Latch Enable to Output HIGH 
(Note 4) 


T A (min.) < T A < 25°C 


4.5 

5.0 


6.5 
9.5 


4.5 

SJ5 


6.5 
12 






Latch Enable to Output LOW 
(Note 4) 


T A (min.l*T A <2S"C 
t a - T A(mW ., 


4.5 

5.0 


6.5 
9.5 


4.S 

&.B 


6.5 
12 




% 


Minimum Set-up Time (Note 4) 


TA(min.)«T A <25"C 
T A " T A ,m»*.) 




3.0 
4.0 




3.0 
6.0 






Minimum Hold Time (Note 41 


^A(mm) *- T A * T A (nait.) 




1JJ 




1.0 




tp^lE) 


Minimum Latch Enable Pulse Width 
(Note 4) 


TAImin.)«T A <25°C 
T A " Tftimax.) 




3.0 
4.0 




io 

5.0 




NOTES: 2: Fot in. metal on pit.).. «Ma at 6.8 


mW-C tor operation at ambient tempera! 
lures above •105°C. 




*ioo"c. f 









/. V- - -5.2V. V T - -2.0V. and. R L - Soft; all switching 
given (or V ot , l „ Ig. CMRR, SVHR. 1 B „, and t pcJ .. apply 



Am686 



FUNCTIONAL DIAGRAM 




LATCH ENABLE 



CONNECTION DIAGRAMS 
Top Views 
Metal Can Dual-ln-Line 




ELECTRICAL CHARACTERISTICS OVER THE OPERATING 
TEMPERATURE RANGES (Unless Otherwise Specified) 



Symbol 




Conditions (Note 3) 


Am686-C 


Am686-M 


Units 


Vos 


Input Offset Voltage 


R S <i 100ft.T A - 25' c 

R S < ioon 


3.0 
3.5 


2.0 
3.0 


mV MAX. 
mV MAX. 


iV 0s /iT 


Average Temperature Coefficient 
of Input Offset Voltage 


r s <. ioon 


10 


10 


uVrCMAX. 


'OS 


Input Offset Current 


26*C <T A <T A (mtxA 
Ta " T A (min.) 


1.0 
1.3 


1.0 
1.6 


U A MAX. 
uA MAX. 




Input Bias Current 


26*C«T A <T A (man.) 


* 1 


10 


uAMAX. 


■b 


Ta-t a tmin _i 


13 


16 


„A MAX. 


V C M 


Input Voltage flange 




+2.7, -3.3 


+ 2.7. -3.3 


V MIN 


CMRR 


Common Mode Rejection Ratio 


R S < 1 00SI, -3.3 V < V CM <. *2. 7 V 


80 


B0 


•m min. 


SVRR 


Supply Voltage Rejection Ratio 


Rj c S00i! 


70 


70 


.-IB MIN. 


V H 


Output HIGH voltage 


lL " -1.0mA, v s - v 5 Imin.l 


2.7 


2.5 


V MIN 


Vol 


Output LOW Voltage 


l[_ * 10mA. Vs ■ Vs (rnan.l 


0.5 


0.5 


V MAX 


i* 


Positive Supply Current 




42 


40 


mA MAX. 


i~ 


Negative Supply Current 




34 


32 


mA MAX 


P DISS 


Power Dissipation 




415 


400 


mWMAX. 


Switching Characteristics (V* = +5.0V, v~ = 


-6.0V, Vi n = lOOmV, V-d = 5.0mV, C u = 15pF) (Note 4) 




«po* 


Propagation Delay. 
Input to Output HIGH 


T A (min.) < T A < 25°C 

Ta ■ t a (max.) 


12 
15 


12 
15 


rrs MAX. 
ns MAX, 


Vd- 


Propagation Delay, 
Input to Output LOW 


Ta lmin.l<T A <25°C 
T A " T A Imax.) 


12 
IS 


12 
15 


ni MAX. 
ns MAX. 


Atpd 


Difference in Propagation Delay 
between Outputs 


Ta-25*C 


zo 


" "77 


nt MAX. 



lation. tin rate-c-t change ■ 



may t» applied around the comparator t( 



ot hyiiaraiis. 



2-57 





MOS MEMORY AND MICROPROCESSOR INTERFACE 



5 





SPECIAL FUNCTIONS 



7 




VOLTAGE REGULATORS 



8 




Data Conversion Products - Section III 

AmDAC-08 8-Bit High-Speed Multiplying D/A Converter 3-1 

LF1 98 Monolithic Sample and Hold Circuits 3-7 

LF298 Monolithic Sample and Hold Circuits 3-7 

LF398 Monolithic Sample and Hold Circuits 3-7 

Am1508/1408 8-Bit Multiplying D/A Converter 3-14 

SSS1508A/1408A 8-Bit Multiplying D/A Converter 3-14 

Am2502 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am2503 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am2504 8-Bit/1 2-Bit Successive Approximation Registers 3-18 

Am25L02 Low Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am25L03 Low Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am25L04 Low Power, 8-Bit/1 2-Bit Successive Approximation Registers 3-24 

Am6070 Companding D-to-A Converter for Control Systems 3-28 

Am6071 Companding D-to-A Converter for Control Systems 3-40 

Am6072 Companding D-to-A Converter for PCM Communication Systems 3-52 

Am6073 Companding D-to-A Converter for PCM Communication Systems 3-64 

Am6080 Microprocessor System Compatible 8-Bit High-Speed Multiplying 

D/A Converter 3-76 

Am6081 Microprocessor System Compatible 8-Bit High-Speed Multiplying 

D/A Converter 3-84 

Application Notes 

Companding DAC 3-96 



AmDAC-08 

8-Bit High Speed Multiplying D/A Converter 



Distinctive Characteristics 

• Fast settling output current — 85nsec 

• Full scale current prematched to ±1 .0 LSB 

• Direct interface to TTL, CMOS, ECL, HTL, NMOS 

• Nonlinearity to ±0.1% max over temperature range 

• High output impedance and compliance 

-10V to+18V 



Differential current outputs 
Wide range multiplying capability 

1.0MHz bandwidth 
Low FS current drift - ±10ppm/°C 
Wide power supply range — ±4.5V to ±18V 
Low power consumption — 33mW @ ±5V 



GENERAL DESCRIPTION 



The DAC-08 series of 8-bit monolithic multiplying Digital- 
to-Analog Converters provide very high speed performance 
coupled with low cost and outstanding applications flexibility. 

Advanced circuit design achieves 85 nsec settling times with 
very low "glitch" and a low power consumption. Monotonic 
multiplying performance is attained over more than a 40 to 1 
reference current range. Matching to within 1 LSB between 
reference and full scale currents eliminates the need for full 
scale trimming in most applications. Direct interface to all 
popular logic families with full noise immunity is provided by 
the high swing, adjustable threshold logic inputs. 

High voltage compliance dual complementary current outputs 
are provided, increasing versatility and enabling differential 
operation to effectively double the peak-to-peak output swing. 
In many applications, the outputs can be directly converted to 
voltage without the need for an external op amp. 



All DAC-08 series models guarantee full 8-bit monotonicity, 
and nonlinearities as tight as 0.1% over the entire operating 
temperature range are available. Device performance is essen- 
tially unchanged over the ±4.5V to ±18V power supply range, 
with 33mW power consumption attainable at ±5V supplies. 

The compact size and low power consumption make the 
DAC-08 attractive for portable and military /aerospace applica- 
tions. All devices are processed to M I L-STD-883. 

DAC-08 applications include 8-bit, LO/isec A/D converters, 
servo-motor and pen drivers, waveform generators, audio 
encoders and attenuators, analog meter drivers, programmable 
power supplies, CRT display drivers, high speed modems and 
other applications where low cost, high speed and complete 
input/output versatility are required. 



EQUIVALENT CIRCUIT 



»4 D 5 D 6 "7 ™» 




ORDERING INFORMATION 



Order 
Number 


Temperature 
Range 


Nonlinearity 


DAC-08AQ 


-55°Cto+125°C 


±.1% 


DAC-08Q 


-55°Cto+125°C 


±.19% 


DAC-08EQ 


0°Cto +70° C 


±.19% 


DAC-08CQ 


0°Cto +70° C 


±.39% 


DAC-08HQ 


0°Cto +70° C 


±.1% 


DAC-08HN 


0°Cto +70° C 


±.1% 


DAC-08 EN 


0"Cto +70°C 


±.19% 


DAC-08CN 


0°C to +70° C 


±.39% 



CONNECTION DIAGRAM 
Top View 

| COMPENSATION 

I-) 




Note: Pin 1 is marked for orientation. 



3-1 



AmDAC-08 

MAXIMUM RATINGS (T A = 25° C Unless Otherwise Noted) 



Operating Temperature 




V+ supply to V- Supply 


36V 


DAC-08AQ, Q 


-55°Cto +125°C 


Logic Inputs 


V-to V+plus 36V 


DAC-08EQ, CQ, HQ 


0°Cto +70° C 


Vlc 


V- to V+ 


Storage Temperature 


-65°Cto +150°C 


Analog Current Outputs 


See Fig. 12 


Power Dissipation 


500mW 


Reference Inputs (V14, V15) 


V-to V+ 


Derate above 100°C 


10mW/°C 


Reference Input Differential Voltage (V14 to V 15 ) ±18V 


Lead Temperature (Soldering, 60 sec) 


300° C 


Reference Input Current (l 14 ) 


5.0mA 



— 



ELECTRICAL CHARACTERISTICS (V s = ±15V, l REF = 2.0mA) 

AmDAC-08A AmDAC-08 

AmDAC-OSH AmDAC-08E AmDAC-08C 



Parameter Description Test Conditions Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units 





Resolution 




8 


8 


8 


8 


8 


8 


8 


8 


8 


Bits 




Monotonicity 




8 


8 


8 


8 


8 


8 


8 


8 


8 


Bits 




Nonlinearitv 


T A - MIN. to MAX. 






±0.1 






■0.19 






±0.39 


%FS 




Settling Time 


To ±1/2 LSB.all bits 
switched ON or OFF 
T A - 25° C 


DAC-08A 
DAC-0S 




85 


135 




85 


136 








ns 


DAC-08E 
DAC-08C 










85 


150 




85 


150 


tp|_n, 
*PHL 


Propagation 
Delay 


Each Bit 


T A -25°C 




35 


60 




35 


60 




35 


60 


ns 


All Bits 
Switched 




35 


60 




35 


60 




35 


60 


TCI FS 


Full Scale Tempco 






±10 


±50 




' 10 


±50 




no 


±80 


ppm/°C 


voc 


Output Voltage Compliance 


Full scale current 
change < 1 12 LSB 
R OUT >20Me 9 nt VP. 


-10 




+18 


-10 




+ 18 


-10 




+18 


Volts 


!fS4 


Full Scale Current 


V REF - 10.000V 
R 14. R 15 = 5-OOOkSl 
T A - 25°C 


1.984 


1.992 


2.000 


1.94 


1.99 


2.04 


1.94 


1.99 


2.04 


mA 


'FSS 


Full Scale Symmetry 


1 FS4 - 1 FS2 




±0.5 


±4.0 




±1.0 


±8.0 




±2.0 


±16 


(lA 


>zs 


Zero Scale Current 






0.1 


1.0 




0.2 


2.0 




0.2 


4.0 


"A 


Ifsr 


Output Current Range 


V 5.0 V 





2.0 


2.1 





2.0 


2.1 





2.0 


2.1 


mA 


V- - -7.0V to -18V 





2.0 


4.2 





2.0 


4.2 





2.0 


4.2 


V|L 


Logic Input 
Levels 


Logic "0" 


v LC -ov 






OS 






0.8 






0.8 


Volts 


V|H 


Logic "1" 


2.0 






2.0 






2.0 






l|L 


Logic 1 nput 
Current 


Logic "0" 


v LC -ov 


V, N - -10V to 
+ 0.8 V 




-2.0 


-10 




-2.0 


-10 




-2.0 


-10 


MA 


>IH 


Logic "1" 


V| N = 2.0V to 
18V 




0.002 


10 




0.002 


10 




0.002 


10 


VlS 


Logic Input Swing 


V 1-5V 


-10 




+18 


-10 




+18 


-10 




+ 18 


Volts 


VtHR 


Logic Threshold Range 


V S = *15V 


-10 




+13.5 


-10 




+13.5 


-10 




+ 13.5 


Volts 


'15 


Reference Bias Current 






-1.0 


-3.0 




-1.0 


-3.0 




-1.0 


-3.0 


nA 


dl/dt 


Reference Input Slew Rate 




4.0 


8.0 




4.0 


8.0 




4.0 


8.0 




mA/us 


PSSI FS+ 


Power Supply Sensitivity 


V+ = 4.5Vto 18 V 




±0.0003 


±0.01 




±0.0003 


±0.01 




±0.0003 


±0.01 


%l% 


PSS'FS- 


V-- -4.5 V to -18 V 
IrEf = 1.0mA 




±0.002 


±0.01 




±0.002 


±0.01 




±0.002 


±0.01 




1 + 


Power Supply Current 


V s - ±5.0V, l REF - 1.0mA 




2.3 


3.8 




2.3 


3.8 




2.3 


3.8 








^1.3 


-5.8 




-4.3 


-5.8 




-4.3 


-5.8 




| + 


V S »+5.0V.-15V, 
'REF = 2.0mA 




2.4 


3.8 




2.4 


3.8 




2.4 


3.8 


mA 






-6.4 


-7.8 




-6.4 


-7.8 




-6.4 


-7.8 




| + 


V S - 115V. I REF -2.0mA 




2.5 


3.8 




2.5 


3.8 




25 


3.8 








-6.5 


-7.3 




-6.5 


-7.8 




-6.5 


-7.8 






Power Dissipation 


±5.0V. I REF = 1.0mA 




33 


48 




33 


48 




33 


48 




+5.0V, -15V, l REF -2.0mA 




108 


136 




108 


136 




108 


136 


mW 


±15V, l REF -2.0mA 




135 


174 




135 


174 




135 


174 





3-2 



AmDAC-08 



BASIC CONNECTIONS 



V REF MO 




1 FS 



+ VREF 255 
RREF X 256 



10+ 10 = 'FS for ALL 
LOGIC STATES 



FOR FIXED REFERENCE, TTL 
OPERATION, TYPICAL VALUES 
ARE: 

Vref = +10.000V 

RREF * 5.000k 

R15 «* R REF 

C C = 0.01,iF 

V L C = OV (GROUND) 



Figure 1. Basic Positive Reference Operation. 



vref. 
*iov v 



APPROX. 
5.0kli 

4r ( 



r 



LOW T.C. 
4.Skfi ,j 

— w, — r 

l REF W-2.0tnA 



Figure 2. Recommended Full Scale Adjustment Circuit. 



"ref'-'o \w- 





IFS 



- vref x 255 

RREF X 256 



Note 1. Rref Sets 1 FS; Fi-| 5 is for Bias 
Current Cancellation. 

Figure 3. Basic Negative Reference Operation. 





61 


B2 


B3 


B4 


B5 


B6 


B7 


B8 






EO 


Eo 


FULL SCALE 


1 


1 


1 


1 


1 


1 


1 


1 


1.992 


000 


-9.960 


000 


FULL SCALE -LS8 


1 


1 


1 


1 


1 


1 


1 





1.984 


.008 


-9.920 


-.040 


HALF SCALE +LSB 


1 




















1 


1.008 


.984 


-5.040 


-4.920 


HALF SCALE 


1 























1.000 


.992 


-5.000 


-4.960 


HALF SCALE — LSB 





1 


1 


1 


1 




1 




.992 


1.000 


-4.960 


-5.000 


ZERO SCALE +LSB 























1 


.008 


1.984 


-.040 


-9.920 


ZERO SCALE 


























.000 


1.992 


.000 


-9.960 



Figure 4. Basic Unipolar Negative Operation. 



l RE p = 2.000mA 



lO.OOOkil 

— VA — 



10.000 k.n 
VA — 




+15VO 6-isv 





B1 


B2 


B3 


B4 


B5 


Bfl 


B7 


88 


EO 


EO 


POS FULL SCALE 


1 




1 


1 


1 


1 


1 


1 


-9.920 


+ 10.000 


POS FULL SCALE -LSB 


1 




1 


1 


t 


1 


1 





-9.840 


+9.920 


ZERO SCALE +LSB 


1 




















1 


-0.080 


+0.160 


ZERO SCALE 


1 























0.000 


+0.080 


ZERO SCALE —LSB 





1 


1 


1 


1 


1 


1 


1 


+0.080 


0.000 


N EG FULL 


SCALE +LSB 























1 


*9.020 


-9.04O 


NEG FULL 


SCALE 


























+ 10.000 


-9.920 





B1 B2- B3 B4 B5 B6 B7 B8 


Eo 


POS FULL SCALE 

POS FULL SCALE —LSB 
(+) ZERO SCALE 
I-} ZERO SCALE 

NEG FULL SCALE +LSB 

NEG FULL SCALE 


11111111 
11111110 
1 
1111111 
1 
00000000 


+9.960 
+9.880 
+0.040 
-O.040 
-9.880 
-9.960 



Figure 5. Basic Bipolar Output Operation. 



Figure 6. Symmetrical Offset Binary Operation. 



3-3 



AmDAC-08 



BASIC CONNECTIONS (Cont.) 





OTO +I FS ■ R L 



LIC-198 



255 

IFS - ^ 



FOR COMPLEMENTARY OUTPUT (OPERATION AS NEGATIVE 
LOGIC DAC), CONNECT INVERTING INPUT OF OP-AMP TO i^j 
(PIN 2), CONNECT l (PIN 41 TO GROUND 

Figure 7. Positive Low Impedance Output Operation. 




o E o 



255 

IFS = ~256 REF 



FOR COMPLEMENTARY (OPERATION AS A NEGATIVE LOGIC 
DAC), CONNECT NON-INVERTING INPUT OF OP-AMP TO To" 
(PIN 2);CONNECT l (PIN 4) TO GROUND. 

Figure 8. Negative Low Impedance Output Operation. 



TTL. DTL 
V TH -*1.4« 



} 




? 

[. OPTIONAL 

R REF S resistor 

S FOR OFFSET 
IM 1 IMPUTS 




CMOS, HTL, NMOS 



Rpn « 20012 




~~ V 

3-08 > 2 



J. 



SET VOLTAGE AT NODE "A" EQUAL TO DESIRED LOGIC 
THRESHOLD. 

Figure 9. Interfacing With Various Logic Families. 



TYPICAL VALUES: 
R|N = 5k 
+V !N = 10V 



Figure 10. Pulsed Reference Operation. 



v ref1+> 



'in : 






14 






"in 


15 







a) l REF > Peak Negative Swing of l| N . 



"REF 


14 




R 15 (OPTIONAL) 


15 









HIGH II . 
IMPEDANCE 

Rref^Ris LIC-202 
b ' + Vref Mus t Be Above Peak Positive Swing of V| N . 
Figure 11. Accomodating Bipolar References. 




•i 4 

+15V 

FOR TURN-ON, V L = 2.7 V 
FOR TURN-OFF, V L - 0.7 V 

Figure 12. Settling Time Measurement. 



3-4 



AmDAC-08 



APPLICATIONS INFORMATION 

REFERENCE AMPLIFIER SET-UP 

The DAC-08 is a multiplying D/A converter in which the out- 
put current is the product of a digital number and the input 
reference current. The reference current may be fixed or may 
vary from nearly zero to +4.0mA.The full scale output current 
is a linear function of the reference current and is given by: 
255 

' FS= "25fF X 'REFwhere lREF = H4- 
In positive reference applications (Fig. 1), an external positive 
reference voltage forces current through R14 into the Vref(+) 
terminal (pin 14) of the reference amplifier. Alternatively, a 
negative reference may be applied to Vref(— ) at pin 15 (Fig. 
3); reference current flows from ground through R14 into 
Vref(+) a s m tne positive reference case. This negative refer- 
ence connection has the advantage of a very high impedance 
presented at pin 15. The voltage at pin 14 is equal to and 
tracks the voltage at pin 1 5 due to the high gain of the internal 
reference amplifier. R-| 5 (nominally equal to R14) is used to 
cancel bias current errors; R-| 5 may be eliminated with only a 
minor increase in error. 

Bipolar references may be accommodated by offsetting Vref 
or pin 15 as shown in Fig. 11. The negative common mode 
range of the reference amplifier is given by: Vcm— = V— plus 
(Iref X 1.0kS2) plus 2.5V. The positive common mode range 
is V+less 1.5V. 

When a DC reference is used, a reference bypass capacitor is 
recommended. A 5.0V TTL logic supply is not recommended 
as a reference. If a regulated power supply is used as a refer- 
ence, R-|4 should be split into two resistors with the junction 
bypassed to ground with a 0.1/jF capacitor. 

For most applications, a +10.0V reference is recommended for 
optimum full scale temperature coefficient performance. This 
will minimize the contributions of reference amplifier Vqs 
and TCVqs- For most applications the tight relationship 
between Iref and Ips will eliminate the need for trimming 
Iref- If required, full scale trimming may be accomplished by 
adjusting the value of R14, or by using a potentiometer for 
R14. An improved method of full scale trimming which elimi- 
nates potentiometer T.C. effects is shown in Fig. 2. 

Using lower values of reference current reduces negative power 
supply current and increases reference amplifier negative com- 
mon mode range. The recommended range for operation with 
a DC reference current is +0.2mA to +4.0mA. 

The reference amplifier must be compensated by using a 
capacitor from pin 16 to V-. For fixed reference operation, 
a 0.01uF capacitor is recommended. For variable reference 
applications, see section entitled "Reference Amplifier Com- 
pensation for Multiplying Applications." 

MULTIPLYING OPERATION 

The DAC-08 provides excellent multiplying performance with 
an extremely linear relationship between l F s and I RE f over a 
range of 4.0mA to 4.0uA. Monotonic operation is maintained 
over a typical range of Iref from 100uA to 4.0mA; consult 
factory for devices selected for monotonic operation over 
wider Iref ranges. 

REFERENCE AMPLIFIER COMPENSATION 
FOR MULTIPLYING APPLICATIONS 

AC reference applications will require the reference amplifier 
to be compensated using a capacitor from pin 16 to V— The 
value of this capacitor depends on the impedance presented to 
pin 14: for R 14 values of 1.0, 2.5 and 5.0kQ, minimum values 
of C c are 15, 37, and 75pF. Larger values of R14 require pro- 
portionately increased values of C c for proper phase margin. 



For fastest response to a pulse, low values of R14 enabling 
small C c values should be used. If pin 14 is driven by a high 
impedance such as a transistor current source, none of the 
above values will suffice and the amplifier must be heavily 
compensated which will decrease overall bandwidth and slew 
rate. For R14 = 1.0kf2 and C c = 15pF, the reference amplifier 
slews at 4.0mA/;US enabling a transition from Iref = to 
Iref = 2.0mA in 500ns. 

Operation with pulse inputs to the reference amplifier may be 
accommodated by an alternate compensation scheme shown in 
Fig. 10. This technique provides lowest full scale transition 
times. An internal clamp allows quick recovery of the reference 
amplifier from a cutoff (Iref = 0) condition. Full scale transi- 
tion (0 to 2.0mA) occurs in 120ns when the equivalent im- 
pedance at pin 14 is 200f2 and C c = 0. This yields a reference 
slew rate of 16mA/us which is relatively independent of Rim 
and V| N values. 



LOGIC INPUTS 

The DAC-08 design incorporates a unique logic input circuit 
which enables direct interface to all popular logic families and 
provides maximum noise immunity. This feature is made 
possible by the large input swing capability, 2.0uA logic input 
current and completely adjustable logic threshold voltage. For 
V— = —15V, the logic inputs may swing between —10V and 
+18V. This enables direct interface with +15V CMOS logic, 
even when the DAC-08 is powered from a +5V supply. Mini- 
mum input logic swing and minimum logic threshold voltage 
are given by: V— plus (Iref X 1.0kJ2) plus 2.5V. The logic 
threshold may be adjusted over a wide range by placing an 
appropriate voltage at the logic threshold control pin (pin 1, 
V|_c). For TTL and DTL interface, simply ground pin LWhen 
interfacing ECL, an Iref = 1.0mA is recommended. For 
interfacing other logic families, see Fig. 9. For general set-up 
of the logic control circuit, it should be noted that pin 1 will 
source IOOuA typical; external circuitry should be designed 
to accommodate this current. 

Fastest settling times are obtained when pin 1 sees a low im- 
pedance. If pin 1 is connected to a 1.0kf2 divider, for example, 
it should be bypassed to ground by a 0.01juF capacitor. 



ANALOG OUTPUT CURRENTS 

Both true and complemented output sink currents are pro- 
vided, when lo + To = I ps- Current appears at the "true" 
output when a "1 " is applied to each logic input. As the binary 
count increases, the sink current at pin 4 increases propor- 
tionally, in the fashion of a "positive logic" D/A converter. 
When a "0" is applied to any input bit, that current is turned 
off at pin_4 and turned on at pin 2. A decreasing logic count 
increases lo as in a negative or inverted logic D/A converter. 
Both outputs may be used simultaneously. If one of the out- 
puts is not required it must still be connected to ground or to 
a point capable of sourcing Ips; do not leave an unused output 
pin open. 

Both outputs have an extremely wide voltage compliance 
enabling fast direct current-to-voltage conversion through a 
resistor tied to ground or other voltage source. Positive com- 
pliance is 36V above V— and is independent of the positive 
supply. Negative compliance is given by V— plus (Iref • 1 0kS2) 
plus 2.5V. 

The dual outputs enable double the usual peak-to-peak load 
swing when driving loads in quasi-differential fashion. This 
feature is especially useful in cable driving, CRT deflection and 
in other balanced applications such as driving center-tapped 
coils and transformers. 



AmDAC-08 



POWER SUPPLIES 

The DAC-08 operates over a wide range of power supply voltages 
from a total supply of 9V to 36V. When operating at supplies of 
±5V or less, Ir ef < 1mA is recommended. Low reference current 
operation decreases power consumption and increases negative 
compliance, reference amplifier negative common mode range, 
negative logic input range, and negative logic threshold range. For 
example, operation at —4.5V with Iref = 2mA is not recom- 
mended because negative output compliance would be reduced 
to near zero. Operation from lower supplies is possible, however 
at least 8V total must be applied to insure turn-on of the internal 
bias network. 

Symmetrical supplies are not required, as the DAC-08 is quite 
insensitive to variations in supply voltage. Battery operation is 
feasible as no ground connection is required : however, an artificial 
ground may be useful to insure logic swings, etc. remain between 
acceptable limits. 

Power consumption may be calculated as follows: 

Pd = (V+) + (l+) (V-) + (2 Iref) (V-). A useful feature of 
the DAC-08 design is that supply current is constant and inde- 
pendent of input logic states; this is useful in cryptographic 
applications and further serves to reduce the size of the power 
supply bypass capacitors. 



TEMPERATURE PERFORMANCE 

The nonlinearity and monotonicity specifications of the DAC-08 
are guaranteed to apply over the entire rated operating tempera- 
ture range. Full scale output current drift is tight, typically 
±10ppm/°C, with zero scale output current and drift essentially 
negligible compared to 1/2 LSB. 

Full scale output drift performance will be best with +10.0V 
references as V s and TCVqs of the reference amplifier will be 
very small compared to 10.0V. The temperature coefficient of 
the reference resistor R 14 should match and track that of the out- 
put resistor for minimum overall full scale drift. Settling times of 
the DAC-08 decrease approximately 10% at -55°C; at +125°C an 
increase of about 15% is typical. 



SETTLING TIME 

The DAC-08 is capable of extremely fast settling times, typically 
85nsecat Iref = 2.0mA. Judicious circuit design and careful board 
layout must be employed to obtain full performance potential 
during testing and application. The logic switch design enables 
propagation delays of only 35nsec for each of the 8 bits. Settling 
time to within 1/2 LSB of the LSB is therefore 35nsec, with each 
progressively larger bit taking successively longer. The MSB settles 
in 85nsec, thus determining the overall settling time of 85nsec. 
Settling to 6-bit accuracy requires about 65 to 70nsec. The output 
capacitance of the DAC-08 including the package is approximately 
15pF, therefore the output RC time constant dominates settling 
time if R L > 500H. 

Settling time and propagation delay are relatively insensitive to 
logic input amplitude and rise and fall times, due to the high gain 
of the logic switches. Settling time also remains essentially 
constant for Iref values down to 1.0mA, with gradual increases 
for lower Iref values. The principal advantage of higher Iref 
values lies in the ability to attain a given output level with lower 
load resistors, thus reducing the output RC time constant. 

Measurement of settling time requires the ability to accurately 
resolve ±4^A, therefore a 1kf2 load is needed to provide adequate 
drive for most oscilloscopes. The settling time fixture of Fig. 12 
uses a cascode design to permit driving a 1ki2 load with less than 
5pF of parasitic capacitance at the measurement node. At Iref 
values of less than 1mA, excessive RC damping of the output is 
difficult to prevent while maintaining adequate sensitivity. How- 
ever, the major carry from 01111111 to 10000000 provides an 
accurate indicator of settling time. This code change does not 
require the normal 6.2 time constants to settle to within ±0.2% 
of the final value, and thus settling times may be observed at 
lower values of Iref- 

DAC-08 switching transients of "glitches" are very low and may 
be further reduced by small capacitive loads at the output at a 
minor sacrifice in settling time. 

Fastest operation can be obtained by using short leads, minimizing 
output capacitance and load resistor values, and by adequate 
bypassing at the supply, reference and V|_c terminals. Supplies 
do not require large electrolytic bypass capacitors as the supply 
current drain is independent of input logic states. O.I/iF capacitors 
at the supply pins provide full transient protection. 



3-6 



LF198/LF298/LF398 

Monolithic Sample and Hold Circuits 



Distinctive Characteristics 

• Operates from ±5V to ±18V supplies 



Less than 10jus acquisition time 
TTL, PMOS, CMOS compatible logic input 
0.5mV typical hold step at Ch = O.OIjuF 
Low input offset 



• 0.002% gain accuracy 

• Low output noise in hold mode 

• Input characteristics do not change during hold mode 

• High supply rejection ratio in sample or hold 

• Wide bandwidth 



GENERAL DESCRIPTION 

The LF198/LF298/LF398 are BI-FET monolithic sample and 
hold circuits with ultra-high DC accuracy, fast acquisition time 
(6us to 0.01%) and low droop rate. A bipolar input stage is 
used to obtain the lowest possible offset voltage and wide 
bandwidth. These circuits are designed to have high common 
mode rejection and a gain accuracy of 0.002%. High input 
impedance (10 10 S2) permits their use with a high impedance 
source without degrading accuracy. 



The output buffer has a p-channel JFET input with a typical 
input current of 30pA, giving a droop rate as low as 5mV/Min 
with a 1uF hold capacitor. The JFET has a very low noise level 
and high temperature stability. 

A differential logic input allows the logic to be referenced to 
a separate ground from analog ground, permitting a direct inter- 
face to nearly any logic family. The LF198 series guarantees 
no feed through in the hold mode including input signal swings 
equal to the power supply. 



FUNCTION DIAGRAM 



LOGIC ~J_ 
REFERENCE °— 






HOLD 
CAPACITOR 



■O OUTPUT 



ORDERING INFORMATION 



Part 
Number 


Package 
Type 


Temperature 
Range 


Order 
Number 


LF398 


Metal Can 
Dice 


0°C to +70°C 


LF398H 
LD398 


LF298 


Metal Can 


-25°C to +85°C 


LF298H 


LF198 


Metal Can 
Dice 


-55°C to + 125X 


LF198H 
LD198 



CONNECTION DIAGRAM 
Metal Can 
Top View 




3-7 



LF298 


-25°Cto +85° C 


LF398 


0°Cto +70° C 


Storage Temperature Range 


-65°Cto+150°C 


Power Dissipation (Package Limitation, Note 1) 


500mW 


Supply Voltage 


±18V 


Input Voltage 


Equal to Supply Voltage 


Logic to Logic Reference Differential Voltage (Note 2) 


+7V, -30V 


Hold Capacitor Short Circuit Duration 


10 sec 



Lead Temperature (Soldering 10 seconds) 300°C 



ELECTRICAL CHARACTERISTICS (Note 3) LF198/LF298 LF398 



Parameter 


Test Conditions 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Unit 


Input Offset Voltage, (Note 6) 


Tj = 25° C 




1 


3 




2 


7 


mV 


Full Temperature Range 






5 






10 


mV 


Input Bias Current, (Note 6) 


Tj = 25° C 




5 


25 




10 


50 


nA 


Full Temperature Range 






75 






100 


nA 


Input Impedance 


Tj = 25° C 




1010 






ioio I n 


Gain Error 


Tj = 25° C, R L =10kH 




0.002 


0.005 








Full Temperature Range 






0.02 






0.02 


% 


Feedthrough Attenuation Ratio 
at 1 kHz 


Tj = 25°C, C n = 0.01mF 


86 


96 




80 


90 




dB 


Output Impedance 


Tj =25°C, "HOLD" mode 




0.5 


2 




0.5 


4 


CI 


Full Temperature Range 






4 






6 


n 


"HOLD" Step, (Note 41 


Tj = 25°C, C h = 0.0VF, V UT = ° 




0.5 


2.0 




1.0 


2.5 


mV 


Supply Current, (Note 6) 


Tj > 25° C 




4.5 


5.5 




4.5 


6.5 


mA 


Logic and Logic Reference Input 
Current 


Tj - 25° C 




2 


10 




2 


10 


MA 


Leakage Current into Hold 
Capacitor (Note 6) 


Tj = 25° C, (Note 5) 
Hold Mode 




30 


100 




30 


200 


pA 


Acquisition Time to 0.1% 


AV 0UT = 10V, C h - 1000 pF 




4 






4 




MS 


C h = 0.01mF 




20 






20 




MS 


Hold Capacitor Charge Current 


V|N - V UT = 2V 




5 






5 




mA 


Supply Voltage Rejection Ratio 


V O UT=0 


80 


110 




80 


110 




dB 


Differential Logic Threshold 


Tj = 25° C 


0.8 


1.4 


2.4 


0.8 


1.4 


2.4 


V 



Notes: 1, The maximum junction temperature is 150°C for the LF198, 115°C for the LF298, and 100"C for the LF398. When used at a higher ambient temperature, the 
TO-5 can package must be derated based on a thermal resistance (0jA) of 150°C/W. 

2. The differential voltage may not exceed this limit. The common mode voltage on the logic pins may equal the supply voltage without causing damage to the 
device. For the LF198 to operate properly, one of the logic pins must be at least 2V below the positive supply and 3V above the negative supply. 

3. The following conditions apply unless otherwise noted: Device is in " sample mode". Tj = 25°C, = ±15V, -1 1.5V < V|n < + 1 1.5V, = 0.01/iF, and Rl = 
lOkXl. Logic reference voltage = OV. Logic input voltage = 2.5V. 

4. The hold step is produced by a charge which is coupled from the logic input signal to the hold capacitor via parasitic capacitance and internal operating 
point changes. Stray capacitance equal to 1 pF will create a 0.5mV step with a 5 volt logic swing and a 0.0 VF hold capacitor. This step can be reduced by 
increasing the magnitude of the hold capacitor. 

5. Leakage current is measured at a junction temperature of 25°C. The junction temperature doubles the 25°C value for each 11°C increase in chip temperature. 
Leakage is guaranteed over the full input signal range. 

6. These values are guaranteed over the ±5 to ±18V supply range. 



3-8 



LF1 98/298/398 




Hold Step 



Output Droop Rate 



"Hold" Settling Time 





















111 I ! Ill 

V+ - V-- 15V = 

































































































































































































































































































































lOOpF 1000pF 0.0W O.lpF lpF 
HOLD CAPACITOR 




100pF 1000pF O.OlpF 0.1uF VF 
HOLD CAPACITOR 




50 100 150 

JUNCTION TEMPERATURE - °C 



Gain Error 



-0.8 
-1.0 



i ; 

Tj = 25° C 








= 10k 








SAM 


PLE N 


ODE 























































































INPUT VOLTAGE — V 



Input Bias Current 




-25 25 50 75 100 125 150 
JUNCTION TEMPERATURE - °C 



Dynamic Sampling Error 




0.1 i 10 100 1000 

INPUT SLEW RATE - Wms 



Feedthrough Rejection Ratio 
(Hold Mode) 



-130 
-120 
-110 
§ -100 

g -90 

2 -80 















> 


+ = v- = 15V 
IN " 10Vp-p - 
'7.8 ' 














- \ 
\ 






c 


h-O.^F 


1 




25 


•c 










± 


I Mill I ■ 














_( 


: t - o.oiuF . 










Nil II 


ll 


L. 




















1000 


•p 





























































10 100 1k 10k 100k 1M 
FREQUENCY - Hi 



Phase and Gain 
(Input to Output, Small Signal) 




10k 100k 
FREQUENCY - Hz 



Hold Step Versus 
Input Voltage 



g 1.0 































Tj-H 


0°C 


















- 2r 


































Ti - -55*C 































INPUT VOLTAGE - V 



LIC-206 



3-9 



LF1 98/298/398 



LOGIC INPUT CONFIGURATIONS 

TTL AND CMOS 
3V<V|_G<HI STATE) < 7V 



ANALOG n £ 

INPUT 



JT: 



VlgO 




Threshold = 1.4V 



O 




_TL- 



VlgO- 



"=" o 

V- 



Threshold= 1.4V 

Rl select for 2.8V at Pin 8 



7V<V|_G<HI STATE) « 15V 



o 



ANALOG Q i 

INPUT 



HOLD 




LIC-209 



Threshold = 0.6 (V+) + 1 .4V 



O 




_TL 



V- 



Threshold = 0.6 (V+) - 1.4V 



OP AMP DRIVE 
OUTPUT VOLTAGE = ±13V 





Threshold « 4V 



Threshold = -4V 



3-10 



LF1 98/298/398 



APPLICATION INFORMATION 

Freezing the input to an analog-to-digital (A/D) converter is an 
important application for the sample and hold amplifier. If the 
analog input to the A/D changes during conversion by the 
amount ±1/2LSB, an ideal A/D would produce 1 LSB error 
beyond normal quantization error. A sample and hold amplifier 
eliminates this problem by holding the input signal to the A/D 
converter during the conversion interval. The proper choice of 
hold capacitor value and type is necessary to obtain optimum 
performance. The capacitor value directly affects several 
circuit parameters, particularly acquisition time, droop rate, 
and hold step. The hold step error is inversely proportional to 
the value of the hold capacitor. 

Graphs are provided in this data sheet for use as guides in se- 
lecting a suitable value of capacitance. However, the capacitor 
should have extremely high insulation resistance and low di- 
electric absorption, or dielectric hysteresis. Polypropylene 
(below +85°C) and Teflon (above +85°C) types are recom- 
mended. The hysteresis error can be significantly reduced if 
the output of the LF198 is digitized immediately after the 
hold mode is initiated. The hysteresis relaxation time constant 
in polypropylene, for instance, is 10-50ms, thus if A/D conver- 
sion can be made within 1ms, hysteresis error will be reduced 
by a factor of ten. 

The logic inputs on the LF198 are fully differential with low 
input current and will operate from TTL levels up to 15V. 
Some typical logic input configurations are shown in this data 
sheet. The logic signal into the LF198 must have a minimum 
slew rate of 0.2V//JS. Slower signals cause excess hold step errors. 

When switched from sample to hold, delay in response to the 
hold command (aperture time and aperture time uncertainty) 
can cause the frozen value of a fast moving waveform to differ 
from the value it had at the instant the hold command is given. 
However, the hold capacitor has an additional lag due to the 
30OJ2 series resistor on the chip which cancels out some of the 
error due to aperture time and aperture time uncertainty. 

For example, using an analog input of 20 volts p-p at 10kHz, 
maximum slew rate 0.5V/us, with no phase delay and 80ns logic 



delay, one could expect up to (0.08/is) • (0.5V/us) = 40mV 
error if the input is sampled during the maximum dv/dt 
period. A positive going input would give a +40mV error. 
Assume that the slew rate of the charging amplifier and the RC 
constant of the analog loop cause a delay of 120ns. If the hold 
capacitor sees this exact delay, then the analog delay would be 
(0.5MV/sec).(.12Ms) = -60mV. Total output error is +40mV 
-60mV = -20mV. 

For a sample and hold amplifier in a multiplexed A/D system, 
acquisition and aperture times are critical parameters. In order 
to maintain the acquired signal level within the specified 
accuracy, these times must be considered when selecting the 
sampling rate. For example, if a 16 channel MUX drives a 
sample and hold amplifier in which each channel is 5KHz and 
2 samples per cycle are needed to satisfy the Nyquist criteria, 
the minimum sampling rate = 160000 samples/sec. ((5KHz X 
16) cycles/sec X 2 samples/cycle). The minimum channel 
period is the reciprocal of the sampling rate of 6.25jus. During 
the hold mode the MUX can switch to another channel. This 
eliminates the need to consider the MUX and source settling 
time and shortens the channel period. 

Calculating the sum of the sample and hold acquisition time, 
aperture time and A/D conversion time is usually a convenient 
method for estimating maximum channel period. 

In multiplex applications, sample and hold feed-through is a 
significant problem. Since each channel voltage differs, the 
sample and hold input signal becomes a series of varied height 
pulses that cause errors in the sample and hold voltage. 

Digital feed through occurs when a fast rising logic signal is 
coupled into the analog input. To minimize it, the logic signal 
trace in the PCB layout should be kept as far as possible from 
the analog input. Guarded trace may also be used around the 
input pin for shielding purposes. 

To adjust the DC offset zeroing, the wiper of a 1K potentio- 
meter is connected to the offset adjust pin. One end of the 
potentiometer is connected to VCC and the other is connected 
through a resistor to ground. The value of the resistor is se- 
lected such that the current flows through it at approximately 
6mA. 



Metallization and Pad Layout 




3-11 



LF1 98/298/398 



APPLICATIONS 

-,5v o o +15V dc W™a°«=t 

1.0k 24k 



CH16 [ 



CH9 O- 



A„ A, A 2 OE 



o- 
o- 



r. 



A n A n A, OE 



1.0k 

+5.0 V WV- 



10 



14 




Vv\ -| 



I ■ LS04 



11 



LOAD r ~^__ rt 
ADDR ^ ^ 



ENP ENT Q fl Q B Q c Q D 
LOAD Am25LSl61 CP 
A 8 C D CLR 



ADO0 C>— 
AD01 O- 



AD03 C>- 
RST 



-15V 
O 



O.OlfjF 

HH 



+15V 
Q 



r 




-O B 5 



-O B 2 
-O Et MSB 



Am2502 

START 



CP 74LS109 



B12 
O — 



Am25LS162 CY 



LOAD CP CLR 



7<X^ 



SEQUENTIAL ADDRESSING OVERLAP MODE A/D CONVERSION 



2 MHz 
CLOCK 



rinjiiinnnjirir^^ 

j 



LF198 y 



XCHANN 
— 



TIMING DIAGRAM FOR SEQUENTIAL ADDRESSING OVERLAP MODE A/D CONVERSION 



3-12 



LF1 98/298/398 



APPLICATIONS (Cont.) 





INPUT | 
I SIGNAL I I 

I I I 

I I I 

*MPLE | HOLD [ " 



TRACK AND HOLD PEAK RECORDER 



+ 15V O O -15V 




FAST ACQUISITION, LOW DROOP SAMPLE AND HOLD 



DEFINITION OF TERMS 

Acquisition Time — The time required to acquire a new analog 
input voltage with an output step of 10V. Note that acquisition 
time is not just the time required for the output to settle, but 
also includes the time required for all internal nodes to settle 
so that the output assumes the proper value when switched to 
the hold mode. 

Aperture time — The delay between the command to hold and 
the actual opening of the hold switch. 

Aperture time uncertainty — The tolerance, or jitter of the 
aperture time. 

Droop rate - The rate of change of output voltage in the hold 
mode. It is caused by leakage currents at the hold capacitor 
node. 



Feed-through - During hold, a small part of the input signal 
feeds through the capacitor of the switch to the hold capacitor 
and output. This is usually a function of the level and fre- 
quency of the input signal and is expressed .in dB. 

Dynamic sampling error — The error introduced into the out- 
puts due to input voltage varying when the hold command is 
issued. Error is expressed in mV with a given hold capacitor. 

Gain error — The ratio of output voltage swing to input voltage 
swing in the sample mode expressed as a percent difference. 

Hold step — The voltage step at the output of the sample and 
hold when switching from sample mode to hold mode with a 
steady (DC) analog input voltage. 



3-13 



Am1508/1408 • SSS1508A/1408A 

8-Bit Multiplying D/A Converter 



Distinctive Characteristics 

• Improved direct replacement for MC 1508/ 1408 

• ±0.19% nonlinearity guaranteed over temperature 
range 

• Improved settling time (SSS1508A/1408A) 

250ns, typ. 



Improved power consumption (SSS1508A/1408A) 

157mW, typ. 
Compatible with TTL, CMOS logic 
Standard supply voltage: +5.0V and -5.0V to -15V 
Output voltage swing: +0.5V to —5.0V 
High speed multiplying input: 4.0mA//zs 



FUNCTIONAL DESCRIPTION 



The SSS1508A/1408A, Ami 508/1408 are 8-bit monolithic 
multiplying Digital-to-Analog Converters consisting of a 
reference current amplifier, an R-2R ladder, and eight high 
speed current switches. For many applications, only a refer- 
ence resistor and reference voltage need be added. Improve- 
ments in design and processing techniques provide faster 
settling times combined with lower power consumption while 
retaining direct interchangeability with MC1 508/1408 devices. 

The R-2R ladder divides the reference current into eight 
binarily-related components which are fed to the switches. 
A remainder current equal to the least significant bit is always 



shunted to ground, therefore the maximum output current is 
255/256 of the reference amplifier input current. For example, 
a full scale output current of 1.992mA would result from a 
reference input current of 2.0mA. 

The SSS1508A/1408A, Am1508/1408 is useful in a wide 
variety of applications, including waveform synthesizers, 
digitally programmable gain and attenuation blocks, CRT 
character generation, audio digitizing and decoding, stepping 
motor drives, programmable power supplies and in building 
Tracking and Successive Approximation Analog-to-Digital 
Converters. 



BLOCK DIAGRAM 



A, A 2 A3 A 4 A 5 A 6 A, 

T T T T T T T 



CURRENT SWITCHES 



I I I I I I I I 



-o'o 



R-2R LADDER 



v HEF (-lo- 



BIAS CIRCUIT 



IENCE V | I 

MT AMP ' — W*<— f— \»A ' 



-o v cc 



-O COMPENSATION 



ORDERING INFORMATION 



Part 


Package 


Temperature 


Order 


Number 


Type 


Range 


Number 




Hermetic DIP 


0°C to +70° C 


AM1408L8 




Hermetic DIP 


0°C to +70° C 


AM1408L7 




Hermetic DIP 


0°C to +70°C 


AM1408L6 




Hermetic DIP 


0°C to +70° C 


SSS1408A-8Q 


Am 1408 


Hermetic DIP 


0°C to +70° C 


SSS1408A-7Q 


Hermetic DIP 


0°C to +70° C 


SSS1408A-6Q 




Plastic DIP 


0° C to +70° C 


AM1408N8 




Plastic DIP 


0° C to +70° C 


AM1408N7 




Plastic DIP 


0°C to +70° C 


AM1408N6 




Dice 


0°C to +70° C 


LD1408 




Hermetic DIP 


-55° C to +125°C 


AM1508L8 


Am 1508 


Hermetic DIP 


-55°Ctp+125°C 


SSS1 508A-8Q 




Dice 


-55°C to +125°C 


LD1508 



CONNECTION DIAGRAM 
Top View 



GND 2 

v EeC 3 

MSBA,Q 5 

*3C 7 



] COMPENSATION 



i5 P v bef'-i 

13 □ V CC 
12 □ A 8 LSB 
11 D A 7 
10 □Aj 



Note: Pin 1 is marked for orientation. 



3-14 



Am1508/1408 • SSS1508A/1408A 

MAXIMUM RATINGS (Above which the useful life may be impaired) 
(Ta = +25°C unless otherwise noted) 



Power Supply Voltage 

vcc 


+5.5Vdc 


Power Dissipation (Package Limitation), Pq 
Ceramic Package 


1000mW 


VEE 


-16.5Vdc 


Derate above Ta = +25° C 


6.7mW/°C 


Digital Input Voltage, V5— V12 
Applied Output Voltage, Vrj 


+5.5,0Vdc 
+0.5, -5.2Vdc 


Operating Temperature Range, Ta 
SSS1508A-8, Am 1508 


-55°Cto+125°C 


Reference Current, 1 14 


5.0mA 


SSS1408A Series, Am1408 Series 


0°Cto +75° C 


Reference Amplifier Inputs, V14, V15 



VCC. V E E Vdc 


Storage Temperature, T s tg 


-65°Cto +150°C 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

Vref 

(V CC = 5.0Vdc, V E £ = -15Vdc, = 2.0mA, SSS1508A-8/Am1508L8: T A = -55°C to+125°C, SSS1408A/Am1408 Series: T A - 0°C to +75°C unless 

R 14 

otherwise noted. All digital inputs at high logic level.) 



Parameters 


Description 


Test Conditions 


Min. 


Typ. 


Max. 


Units 




Relative Accuracy 














SSS1508A-8, SSS1408A-8, Am1508L8, Am1408L8 








±0.19 




Er 


SSS1408A-7. Am1408L7 








±0.39 


% IFS 




SSS1408A-6, Am1408L6 








±0.78 




to 


Settling Time to within 1/2 LSB (includes tp|_H) 

SSS1508A/1408A 


T A - +25° C 




250 






Ami 508/1408 




300 






»PLH. «PHL 


Propagation Delay Time 


T A = +25° C 




30 


100 


ns 


TCI 


Output Full Scale Current Drift 






±20 




PPM/°C 




Digital Input Logic Levels (MSB) 












V| H 


High Level, Logic "1" 




2.0 






Vdc 


V|L 


Low Level, Logic "0" 








0.8 


■iH 


Digital Input Current (MSB) 


High Level, V| H ■ 5.0V 







0.04 


mA 


•IL 


Low Level, V|l = 0.8V 




-0.002 


-0.8 




Reference Input Bias Current (Pin 15) 












1 1 r- 


SSS1508A/1408A 






-1.0 


-3.0 


UM 


Ami 508/1408 






-1.0 


-5.0 


'or 


Output Current Range 


VEE " -5.0V 





2.0 


2.1 


mA 


VEE " -7.0V to -15V 





2.0 


4.2 


10 


Output Current 


V ref ' 2.000V, R 14 = 1000f2 


1.9 


1.99 


2.1 


mA 


'O (min.) 


Output Current (All Bits Low) 









4.0 


uA 


v 


Output Voltage Compliance 


V E E " -5V 






-0.6, +0.5 


Vdc 


(E r <0.19%at T A = +25°C) 


V E E below -10V 






-5.0, +0.5 


SRIref 


Reference Current Slew Rate 






4.0 




mA/^s 


PSSI 


Output Current Power Supply Sensitivity 






0.5 


2.7 


MA/V 




Power Supply Current 












'cc 


SSS 1508 A/1 408A 






2.5 


14 




'EE 






-6.4 


-13 


mA 


ice 


Am 1508/1 408 






2.5 


22 


'EE 






-6.4 


-13 




V CCR 


Power Supply Voltage Range 


T A - +25° C 


4.5 


5.0 


5.5 


Vdc 


veer 


-4.5 


-15 


-16.5 




Power Dissipation 


All Bits Low 

VEE = -5.0Vdc 




34 


136 






SSS1508A/1408A 


V EE = -15Vdc 




108 


265 






All Bits High 

V E E = -5.0Vdc 




34 






Pd 




V E £ = -15Vdc 




108 




mW 






All Bits Low 














V EE = -5.0Vdc 




34 


170 






Am1E08/1408 


V EE 15 Vdc 




108 


305 






All Bits High 














V EE = -5.0Vdc 




34 










V EE - -15Vdc 




108 







3-15 



Ami 508/1 408 • SSS 1508 A/1 408 A 



TYPICAL APPLICATIONS 



RELATIVE ACCURACY TEST CIRCUIT 



A, 






A 2 






A 3 12-BIT 
A 4 D-TO-A 
fl CONVERTER 
A 5 (±0.01% 
A 6 ERROR MAXI 


A 7 






Ag A 


A 




2 


LSB j 










USE WITH CURRENT-TO-VOLTAGE 
CONVERTING OP AMP 



A 2 O- 
A 3 O- 



«6 0- 



Am 1508 
Am 1408 
SSS1508A 
SSS1408A 
SERIES 



15 



V REF = 2.0Vdc 
Rid = Ric = V0kf2 



*0 



I ~~ ^ 



r 



THEORETICAL V 



V = 



VREF 



(RqI 



At 
2 



A 2 A 3 A 4 
4 8 16 



A 5 A 6 A 7 A 8 
32 64 126 256 



ADJUST V REF , R 14 OR R SO THAT V WITH ALL DIGITAL 
INPUTS AT HIGH LEVEL IS EQUAL TO 9.961 VOLTS 



2V 

V = (5k) 

1k 



111111 1 1 "| 

- + — + — + — + — + — + + 

2 4 8 16 32 64 126 256j 



255 



256 



USE WITH POSITIVE V REF 



Am1508 
Aml408 
SSS1508A 




_TL 

OI+)V REF 



~i_r 



USE WITH NEGATIVE V REF 

<? v cc 



Ami 508 
Ami 408 
SSS1508A 
SSS1408A 
SERIES 




PL 

T i 
J * 



~i_r 



TRANSIENT RESPONSE AND 
SETTLING TIME TEST CIRCUIT 




FOR SETTLING TIME 
MEASUREMENT 
(ALL BITS SWITCHED 
LOW TO HIGH) 



~ C « 25pP 



3-16 



Ami 508/1 408 • SSS1508A/1408A 



GENERAL INFORMATION AND APPLICATION NOTES 



REFERENCE AMPLIFIER DRIVE AND COMPENSATION 

The reference amplifier provides a voltage at pin 14 for con- 
verting the reference voltage to a current, and a turn-around 
circuit or current mirror for feeding the ladder. The reference 
amplifier input current, l 14 must always flow into pin 14 
regardless of the setup method or reference voltage polarity. 
Connections for a positive voltage are shown on page 3. The 
reference voltage source supplies the full current I14. For 
bipolar reference signals, as in the multiplying mode, R 15 can 
be tied to a negative voltage corresponding to the minimum 
input level. It is possible to eliminate R 15 with only a small 
sacrifice in accuracy and temperature drift. 

The compensation capacitor value must be increased with 
increases in R 14 to maintain proper phase margin; for R14 
values of 1.0, 2.5 and 5.0 kilohms, minimum capacitor values 
are 15, 37, and 75 pF. The capacitor may be tied to either 
V EE or ground, but using V EE increases negative supply 
rejection. 

A negative reference voltage may be used if R 14 is grounded 
and the reference voltage is applied to R15 as shown. A high 
input impedance is the main advantage of this method. Com- 
pensation involves a capacitor to on pin 16, using the 
values of the previous paragraph. The negative reference 
voltage must be at least 4.0 volts above the Vgr; supply. 
Bipolar input signals may be handled by connecting R} 4 to a 
positive reference voltage equal to the peak positive input level 
at pin 1 5. 

When a dc reference voltage is used, capacitive bypass to ground 
is recommended. The 5.0V logic supply is not recommended 
as a reference voltage. If a well regulated 5.0V supply which 
drives logic is to be used as the reference, R 14 should be de- 
coupled by connecting it to +5.0V through another resistor 
and bypassing the junction of the two resistors with 0.1uF 
to ground. For reference voltages greater than 5.0V, a clamp 
diode is recommended between pin 14 and ground. 

If pin 14 is driven by a high impedance such as a transistor 
current source, none of the above compensation methods 
apply and the amplifier must be heavily compensated, de- 
creasing the overall bandwidth. 

OUTPUT VOLTAGE RANGE 

The voltage on pin 4 is restricted to a range of —0.6 to +0.5 
volts when Vg£= —5.0V due to the current switching methods 
employed in the SSS1 508A-8, Ami 508. 

The negative output voltage compliance of the SSS1508A-8, 
Ami 508 is extended to -5.0V where the negative supply 
voltage is more negative than -10 volts. Using a full scale 
current of 1.992mA and load resistor of 2.5 kilohms between 
pin 4 and ground will yield a voltage output of 256 levels 
between and -4.980 volts. Floating pin 1 does not affect 
the converter speed or power dissipation. However, the value 
of the load resistor determines the switching time due to 
increased voltage swing. Values of R|_ up to 500 ohms do not 
significantly affect performance but a 2.5-kilohm load increases 
"worst case" settling time to '\.2nS (when all bits are switched 
on). Refer to the subsequent text section on Settling Time 
for more details on output loading. 

OUTPUT CURRENT RANGE 

The output current maximum rating of 4.2mA may be used 
only for negative supply voltages more negative than -7.0 
volts, due to the increased voltage drop across the resistors 
in the reference current amplifier. 



ACCURACY 

Absolute accuracy is the measure of each output current 
level with respect to its intended value, and is dependent 
upon relative accuracy and full scale current drift. Relative 
accuracy is the measure of each output current level as a frac- 
tion of the full scale current. The relative accuracy of the 
SSS1508A-8, Am1508 is essentially constant with tempera- 
ture due to the excellent temperature tracking of the mono- 
lithic resistor ladder. The reference current may drift with 
temperature, causing a change in the absolute accuracy of out- 
put current. However, the SSS1508A8 has a very low full 
scale current drift with temperature. 

The SSS1508A-8/Am1508 Series is guaranteed accurate to 
within ±1/2 LSB at a full scale output current of 1.992mA. 
This corresponds to a reference amplifier output current drive 
to the ladder network of 2.0mA, with the loss of one LSB 
(8.0uAI which is the ladder remainder shunted to ground. 
The input current to pin 14 has a guaranteed value of between 
1.9 and 2.1mA, allowing some mismatch in the NPN current 
source pair. The accuracy test circuit is shown on page 3. 
The 12-bit converter is calibrated for a full scale output current 
of 1.992mA. This is an optional step since the SSS1508A-8, 
Am 1508 accuracy is essentially the same between 1.5 and 
2.5mA. Then the SSS1508A-8, Ami 508 circuits' full scale 
current is trimmed to the same value with R 14 so that a zero 
value appears at the error amplifier output. The counter is 
activated and the error band may be displayed on an oscil- 
loscope, detected by comparators, or stored in a peak detector. 

Two 8-bit D-to-A converters may not be used to construct a 
16-bit accuracy D-to-A converter. 16-bit accuracy implies a 
total error of ±1/2 of one part in 65,536 or ±0.00076%, 
which is much more accurate than the ±0.19% specification 
provided by the SSS1508A-8, Ami 508. 

MULTIPLYING ACCURACY 

The SSS1508A-8, Am 1508 may be used in the multiplying 
mode with eight-bit accuracy when the reference current is 
varied over a range of 256:1. If the reference current in the 
multiplying mode ranges from 16/nA to 4.0mA, the additional 
error contributions are less than 1.6/jA. This is well within 
eight-bit accuracy when referred to full scale. 

A monotonic converter is one which supplies an increase in 
current for each increment in the binary word. Typically, the 
SSS1508A-8, Am 1508 is monotonic for all values of reference 
current above 0.5mA. The recommended range for operation 
with a dc reference current is 0.5 to 4.0mA. 

SETTLING TIME 

The "worst case" switching condition occurs when all bits are 
switched "on," which coresponds to a LOW-to-HIGH transi- 
tion for all bits. This time is typically 250ns for settling to 
within ±1/2 LSB, for 8-bit accuracy, and 200ns to 1/2 LSB 
for 7 and 6-bit accuracy. The turn off is typically under 100ns. 
These times apply when R L < 500 ohms and Co < 25pF. 

The slowest single switch is the least significant bit. In applica- 
tions where the D-to-A converter functions in a positive-going 
ramp mode, the "worst case" switching condition does not 
occur, and a settling time of less than 250ns may be realized. 
Extra care must be taken in board layout since this is usually 
the dominant factor in satisfactory test results when measuring 
settling time. Short leads, 100juF supply bypassing for low 
frequencies, and minimum scope lead length are all mandatory. 



3-17 



Am2502/2503/2504 

Eight-Bit/Twelve-Bit Successive Approximation Registers 



Distinctive Characteristics 

• Contains all the storage and control for successive 
approximation A-to-D converters. 

• Provision for register extension or truncation. 

• Can be operated in START-STOP or continuous 
conversion mode. 



FUNCTIONAL DESCRIPTION 

The Am2502, Am2503 and Am2504 are 8-bit and 12-bit TTL Suc- 
cessive Approximation Registers. The registers contain all the digital 
control and storage necessary for successive approximation analog-to- 
digital conversion. They can also be used in digital systems as the 
control and storage element in recursive digital routines. 
The registers consist of a set of master latches that act as the control 
elements in the device and change state when the input clock is'LOW, 
and a set of slave latches that hold the register data and change on the 
input clock LOW-to-HIGH transition. Externally the device acts as a 
special purpose serial-to-paratlel converter that accepts data at the D 
input of the register and sends the data to the appropriate slave latch 
to appear at the register output and the DO output on the Am2502 
and Am2504 when the clock goes from LOW-to-HIGH. There are no 
restrictions on the data input; it can change state at any time except 
during the set-up time just prior to the clock transition. At the same 
time that data enters the register bit the next less significant bit is set 
to a LOW ready for the next iteration. 

The register is reset by holding the S (Start) signal LOW during the 
clock LOW-to-HIGH transition. The register synchronously resets to 
the state Q 7 (11j LOW, (Note 2} and all the remaining register outputs 
HIGH. The_CC (Conversion Complete) signal is also set HIGH at this 
time. The S signal should not be brought back HIGH until after the 



• 100% reliability assurance testing in compliance 
with MlL-STD-883. 

• Can be used as serial-to-parallel converter or ring 
counters. 

• Electrically tested and optically inspected dice for 
the assemblers of hybrid products. 



clock LOW-to-HIGH transition in order to guarantee correct resetting. 
After the clock has gone HIGH resetting the register, the S signal is 
removed. On the next clock LOW-to-HIGH transition the data on the 
D input is set into the Q 7 (1 1 ) register bit and the Qq{10) register bit is 
set to a LOW ready for the next clock cycle. On the next clock LOW- 
to-HIGH transition data enters the QgdO) register bit and Q 5 (9) is set 
to a LOW. This operation is repeated foseach register bit in turn until 
the register has been filled. When the data goes into Qq, the CC signal 
goes LOW, and the register is inhibited from ftfrther change until reset 
by a Start signal. 

In order to allow complementary conversion the complementary 
output of the most significant register bit is made available. An active 
LOW enable input, E, on the Am2503 and Am2504 allows devices to 
be connected together to form a longer register by connecting the 
clock, D, and_S inputs together and connecting the CC output of one 
device to the E input of the next less significant device. When the Start 
signal resets the register, the E signal goes HIGH, forcing the 07(H) bit 
HIGH and inhibiting the_ device from accepting data until the previous 
device is full and its CC goes LOW. If only one device is used the E 
input should be held at a LOW logic level (Ground). If all the bits are 
not required, the register may be truncated and conversion_time saved 
by using a register output going LOW rather than the CC signal to 
indicate the end of conversion. 



LOGIC DIAGRAMS 



D 



TJ 



pO OS Q — , 



Notes: 1. Cell logic is repeated for register stages. Q 5 to Qi Am2502/3, Qg to Qi, Am2504. 
2. Numbers in parentheses are for Am2504. 



LOGIC SYMBOLS 



fi T TT i T l' T 

15 14 13 12 11 fl 5 4 3 



V cc » Pin 16 
GND - Pin 8 



Q,, 0i Qg Q 8 Oj Ob e Q,, Q 3 Qg 

VI I I I I I I I I I I I 

13 !1 W19 IS 17 16 9 a ; 8 5 * 

LIC-226 

V CC - Pin 24 
GND = Pin 12 
NC - Pins 10, 15 22 



CONNECTION DIAGRAMS 
Top Views 



1" 



°oC < 

°>C 

°.E ■ 

°6C ■ 

*>c « 



" - ' 
- 3- 
□ •■■ 

» □=,« 
* 5«i 

.7 

u 3, 

73 



Note: Pin 1 is marked for orientation. 



LIC-228 



3-18 



Am2502/03/04 

MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 


— DO lj to ' I OU \j 


Temperature (Ambient) Under Bias 


—bo L. to + 1 L- 


Supply Voltage to Ground Potential Continuous 


— u.o v to +/ V 


DC Voltage Applied to Outputs for High Output State 


-0.5 V to +V CC max 


DC Input Voltage 


-0.5 V to +5.5 V 


Output Current, Into Outputs 


30 mA 


DC Input Current 


-30 mA to +5.0 mA 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) 

Am2502XC Am2503XC Am2504XC T A = 0°C to +75° C V cc = 5.0V ±5% 

Am2502XM Am2503XM Am2504XM T A = -55° C to + 1 25° C V CC =5.0V±10% 



Parameters 




Description 


Test Conditions 




Min. 


Typ. (Note 1) 


Max. 


Units 


v OH 




Output HIGH Voltage 


V cc - MIN., I 0H = -0.48mA 
V |N =V |H or V |L 


2.4 


3.6 




Volts 


v OL 




Output LOW Voltage 
(Note 2 ) 


V cc = MIN., l OL = 9.6mA 
V IN = V IH orV IL 




0.2 


0.4 


Volts 


V| H 


Input HIGH Level 


Guaranteed input logical HIGH 
voltage for all inputs 


2.0 






Volts 


V IL 


Input LOW Level 


Guaranteed input logical LOW 
voltage for all inputs 






0.8 


Volts 


Ml 


Unit Load 


V cc = MAX., V, N = 0.4V 


CP, D, S 




-1.0 


-1.6 


mA 


Input LOW Current 


E 




-1 .5 


-2.4 






Unit Load 


V cc m MAX., V, N = 2.4V 


CP, D 




6.0 


40 


HA 


' ! H 




Input HIGH Current 


E, S 




12.0 


80 






Input HIGH Current 


V cc « MAX., V, N =5.5V 






1.0 


mA 


'sc 


Output Short Circuit Current 


V cc = MAX., V 0UT = 0.0V 


-10 


-25 


-45 


mA 










Am2502 


XM 




65 


85 


mA 










XC 




65 


95 






Power Supply Current 


V cc = MAX. 


Am2503 


XM 




60 


80 


mA 


'cc 




XC 




60 


90 










Am2504 


XM 




90 


110 


mA 










XC 




90 


124 



Notes: 1. Typical Limits are at Vcc = 5.0V, 25°C ambient and maximum loading. 

2. Vol (max ) 58 °- 4v with total device fanout of less than 50 TTL Unit Loads (80mA). Otherwise, V lI max -> = 0.45V. 



Switching Characteristics (Ta = 25°C, Vcc = 5.0V, c L = i5pF) 



Parameters 


Description 




Min. 


Typ. 


Max. 


Units 


tpd+ 


Turn Off Delay CP to Output HIGH (except Q-j 1 , 1 ) 


10 


29 


45 


ns 


'pd+ 


Turn Off Delay CP to Q-| 1 or 1 HIGH 


10 


35 


50 


ns 


<pd- 


Turn On Delay CP to Output LOW 


10 


27 


40 


ns 


t s (DI 


Set-up Time Data Input 


-10 


4.0 


10 


ns 


t s (S) 


Set-up Time Start Input 





9.0 


16 


ns 


tpd+IE) 


Turn Off Delay E to Q 7 (11) HIGH 


(Am2503/Am2504) 




15 


23 


ns 


tpd-(EI 


Turn On Delay E to 07(H) LOW 


Cp = H,S=L 




20 


30 


ns 


tpwLlCP) 


Minimum LOW Clock Pulse Width 




28 


46 


ns 


'pwH(CP) 


Minimum HIGH Clock Pulse Width 




12 


20 


ns 


f max. 


Maximum Clock Frequency 


15 


25 




MHz 



3-19 



Am2502/03/04 



SWITCHING TIME WAVEFORMS 




KEY TO TIMING DIAGRAM 



ViViViViViWiYiViYiViWiWiViyi 

WiV»V»V 4 V»YiYiV»Y»V»V»ViYiYAV, 



tp^ MAX._ 



1'AYiViViYiVi 



w 



m 



MUST BE 
STEADY 



MAY CHANGE 
FROM L TO H 



WILL BE 
CHANGING 
FROM H TO L 



WILL BE 
CHANGING 
FROM L TO H 



DON'T CARE; CHANGING. 
ANY CHANGE STATE 
PERMITTED UNKNOWN 














_tpo,(EI MAX 




-t„j-(Ei MAX 


Wh 


1 wv 



DEFINITION OF TERMS 

SUBSCRIPT TERMS: 

H HIGH, applying to a HIGH logic level or when used with Vcc 
to indicate high Vcc value. 
I Input 

L LOW, applying to LOW logic level or when used with V cc to 
indicate low Vcc value. 
O Output 

FUNCTIONAL TERMS: 

Fan-Out The logic HIGH or LOW output drive capability in 
terms of Input Unit Loads. 

Input Unit Load One T 2 L gate input load. In the HIGH state it 
is equal to l| H and in the LOW state it is equal to l| L . 
CP The clock input of the register. 

CC The conversion complete output. This output remains HIGH 
during a conversion and goes LOW when a conversion is complete. 

D The serial data input of the register. 

E The register enable. This input is used to expand the length of 
the register and when HIGH forces the Q 7 (11) register output 
HIGH and inhibits conversion. When not used for expansion the 
enable is held at a LOW logic level (Ground). 

Q7<11) The true output of the MSB of the register. 
Q7<11) The complement output of the MSB of the register. 
Qj i = 7(11) to The outputs of the register. 
S The start input. If the start input is held LOW for at least a 
clock period the register will be reset to Q 7 (11) LOW and all the 
remaining outputs HIGH. A start pulse that is LOW for a shorter 
period of time can be used if it meets the set-up time require- 
ments of the S input. 

DO The serial data output. (The D input delayed one bit). 

OPERATIONAL TERMS: 

IlL Forward input load current. 



'oh Output HIGH current, forced out of output V QH test. 

Iql Output LOW current, forced into the output in Vql test. 

1 1 h Reverse input load current. 

Negative Current Current flowing out of the device. 

Positive Current Current flowing into the device. 

V|h Minimum logic HIGH input voltage. 

V|i_ Maximum logic LOW input voltage. 

V h Minimum logic HIGH output voltage with output HIGH 
current l 0H flowing out of output. 

Vql Maximum logic LOW output voltage with output LOW cur- 
rent Iql flowing into output. 

SWITCHING TERMS: ( Measured at the 1.5V logic level), 
tpd- Tne propagation delay from the clock signal LOW-HIGH 
transition to an output signal HIGH-LOW transition. 
t pd+ The propagation delay from the clock signal LOW-HIGH 
transition to an output signal LOW-HIGH transition. 
tpc.fE) The propagation delay from the Enable signal HIGH- 
LOW transition to the Q 7 (11) output signal HIGH-LOW trans- 
ition. 

tpd+(E) The propagation delay from the Enable signal LOW- 
HIGH transition to Q 7 (11) output signal LOW-HIGH transition. 
t s (D) Set-up time required for the logic level to be present at the 
data input prior to the clock transition from LOW to HIGH in 
order for the register to respond. The data input should remain 
steady between t s max. and t s min. before the clock. 
tjIS) Set-up time required for a LOW level to be present at the 
S input prior to the clock transition from LOW to HIGH in order 
for the register to be reset, or time required for a HIGH level to 
be present on S before the HIGH to LOW clock transition to 
prevent resetting. 
tpw(CP) The m 

required for proper register operation. 
3-20 



Am2502/03/04 



Am2502/3 TRUTH TABLE 



Time Inputs Outputs 



'n 


D 


s 


E 


D 


Q 7 


Q 6 


Q 5 


Q 4 


Q 3 


Q 2 


Q 1 





CC 





X 


L 


L 


X 


X 


X 


X 


X 


X 


X 


X 


X 


X 


1 


D 7 


H 


L 


X 


L 


H 


H 


H 


H 


H 


H 


H 


H 


2 


D 6 


H 


L 


°7 


D 7 


L 


H 


H 


H 


H 


H 


H 


H 


2 


n 
D 5 


|_| 




n 


D 7 


n 


I 


l_l 


l_l 


l_l 


^1 




i-l 


4 


D 4 


H 


L 


D 5 


D 7 


D 6 


D 5 


L 


H 


H 


H 


H 


H 


5 


D 3 


H 


L 


D 4 


°7 


D 6 


D 5 


°4 


L 


H 


H 


H 


H 


6 


D 2 


H 


L 


D 3 


D 7 


D 6 


D 5 


°4 


D 3 


L 


H 


H 


H 


7 


D 1 


H 


L 


D 2 


°7 


D 6 


D 5 


D 4 


D 3 


D 2 


L 


H 


H 


8 


D 


H 


L 


D 1 


D 7 


D 6 


D 5 


D 4 


D 3 


D 2 


D 1 


L 


H 


9 


X 


H 


L 


D 


D 7 


D 6 


D 5 


D 4 


D 3 


D 2 


D 1 


D 


L 


10 


X 


X 


L 


X 


D 7 


D 6 


D 5 


D 4 


D 3 


D 2 


D 1 


D o 


L 




x 


X 


H 


X 


H 


NC 


NC 


NC 


NC 


NC 


NC 


NC 


NC 



H = HIGH Voltage Lev/el 
L = LOW Voltage Level 
X = Don't Care 
NC - No Change 



Note: Truth Table for Am2504 is extended to include 
12 outputs. 



USER NOTES FOR A/D CONVERSION 

1. The register can be used with either current switches 
that require a low voltage level to turn the switch on, 
or current switches that require a high voltage level to 
turn the current switch on. If current switches are used 
which turn on with a low logic level the resulting digital 
output from the register is active LOW. That is, a logic 
" 1 " is represented as a low voltage level. If current swit- 
ches are used that turn on with a high logic level then 
the digital output is active HIGH; a logic "1 " is repre- 
sented as a high voltage level. 

2. For a maximum digital error of I'/iLSB the comparator 
must be biased. If current switches that require a high 
voltage level to turn on are used, the comparator should 
be biased +V2LSB and if the current switches require a 
high logic level to turn on then the comparator must be 
biased — ViLSB. 

3. The register, by suitable selection of resistor ladder net- 
work, can be used to perform either binary or BCD 
conversion. Additional data input gating should be used to 
eliminate the possibility of false BCD codes. 

4. The register can be used to perform 2's complement 
conversion by offsetting the comparator V4 full range 
+'/2 LSB and using the complement of the MSB Qy 
(0-1 1 ) as the sign bit. 

5. If the register is truncated and operated in the continuous 
conversion mode a lock-up condition may occur on power- 
on. This situation can be overcome by making the 
START input the OR function of CC and the appropriate 
register output. 




Am2502/03/04 



Am2502/3 LOADING RULES (IN UNIT LOADS) 



Input 



Fanout 



Input/Output 


Pin 
No.'s 


Unit Load 
LOW HIGH 


Output 
HIGH 


Output 
LOW 


F (2503) 




1 .5 


2 






no (9502) 


1 






12 


6 


cc 


2 






1 o 


O 


Q o 


6 






1 1 
1 z 





Q 1 


4 






1 2 


6 


r\ 
Q 2 









1 o 


o 




6 






12 


6 


D 


7 


1 


1 






GND 


g 










CP 


g 


1 


1 






g 


10 


1 


2 






Q. 


1 1 






12 


6 


Q 5 


12 






12 


6 


Q 6 


13 






12 


6 


Q 7 


14 






12 


6 


^7 


15 






12 


6 


V CC 


16 











Am2504 LOADING RULES (IN UNIT LOADS) 



MSI INTERFACING RULES 

Equivalent 
Input Unit Load 

Interfacing Digital Family HIGH LOW 



Advanced Micro Devices 9300/2500 Series 1 1 


FSC Series 9300 1 1 


Advanced Micro Devices 54/7400 


1 


1 


Tl Series 54/7400 


1 


1 


Signetics Series 8200 


2 


2 


National Series DM 75/85 


1 


1 


DTL Series 930 


12 


1 



Input 



Fanout 



Input/Output 


Pin 
No.'s 


Unit Load 
LOW HIGH 


Output 
HIGH 


Output 
LOW 


E 


1 


1.5 


2 







nn 


2 






1 2 


5 


CC 


3 






1 2 


6 


U 


4 






1 7 





Q 1 


5 






12 


6 


Q 2 


6 






1 2 


6 


Q 3 


7 






I 2 


6 


Q 4 


8 






1 2 


6 


5 


9 






1 2 


6 


NC 


1 










D 


1 1 


1 


1 






GND 


1 2 










CP 


1 3 


1 








s 


1 4 


1 


2 







MP 


1 










n 
U 6 


1 6 


— 




1 2 




Q 7 


1 7 






1 2 


6 


u 8 


1 8 






1 2 


6 


Qg 


19 






12 


6 


Q 10 


20 






12 


6 


Q tl 


21 






12 


6 


NC 


22 










5 11 


23 






12 


6 


Vcc 


24 











A Standard TTL Unit Load is defined as 40^A measured at 2.4V 
HIGH and -1.6mA measured at 0.4V LOW. 



NC = No Connection 



INPUT/OUTPUT INTERFACE CONDITIONS 



Voltage Interface Conditions - LOW & HIGH 



Current Interface Conditions — LOW 



MINIMUM LOGIC 
"HIGH" OUTPUT 
VOLTAGE 



MAXIMUM LOGIC 
"LOW" OUTPUT 
VOLTAGE 





V IH 2 




MINIMUM LOGIC 


IMMUNITY 


"HIGH" INPUT 


(High level) 


VOLTAGE 




V|L 2 


^T^&r — 

NOISE 
IMMUNITY 
(Low leuel) 


MAXIMUM LOGIC 
"LOW" INPUT 
VOLTAGE 



DF1IVING D€VICE 



DRIVEN DEVICE 



OUTPUT DRIVING 
LOW 



INPUT LOAD 
DRIVEN LOW 





Current Interface Conditions 

OUTPUT DRIVING 



HIGH 




3-22 



Am2502/03/04 



Am2502/3/4 APPLICATION 
Continuous Conversion Analog-to-Digital Converter 













D S 

E Am2504 00 
12-fllTSAH 




CLOCK 




SERIAL DATA OUT 








COMPLETE 



12-BIT D/A CONVEHTER 




This shows how the Am2502/3/4 registers are used with a Digital-to-Analog converter and a comparator to form a very high-speed con 
tinuous conversion Analog-to-Digital converter. Conversion time is limited mainly by the speed of the D/A converter and comparator with 
typical conversion rates of 100,000 conversions per second. 



LIC-233 



Metallization and Pad Layout 



Am2502 Am2503 Am2504 




DIE SIZE 0.087" X 0.105" DIE SIZE 0.087" X 0.105" DIE SIZE 0.087" X 0.135" 



3-23 



Low-F 



Am25L02/25L03/25L04 

Approximation Registers 



Distinctive Characteristics 

• Contains all the storage and control for successive 
approximation A-to-D converters. 

• Can be operated in START-STOP or continuous 
conversion mode. 



• 100% reliability assurance testing in compliance with 
MIL-STD-883. 

• Can be used as serial-to-parallel converter or ring 
counters. 



FUNCTIONAL DESCRIPTION 

The Am25L02, Am25L03 and Am25L04 are 8-bit and 12-bit TTL 
Successive Approximation Registers. The registers contain all the digital 
control and storage necessary for successive approximation analog-to- 
digital conversion. They can also be used in digital systems as the 
control and storage element in recursive digital routines. 
The registers consist of a set of master latches that act as the control 
elements in the device and change state when the input clock is LOW, 
and a set of slave latches that hold the register data and change on the 
input clock LOW-to-HIGH transition. Externally the device acts as a 
special purpose serial-to-parallel converter that accepts data at the D 
input of the register and sends the data to the appropriate slave latch 
to appear at the register output and the DO output on the Am25L02 
and Am25L04 when the clock goes from LOW-to-HIGH. There are no 
restrictions on the data input; it can change state at any time except 
during the set-up time just prior to the clock transition. At the same 
time that data enters the register bit the next less significant bit is set 
to a LOW ready for the next iteration. 

The register is reset by holding the S (Start) signal LOW during the 
clock LOW-to-HIGH transition. The register synchronously resets to 
the state 0.7{1J_) LOW, (Note 2) and all the remaining register outputs 
HIGH. The_CC (Conversion Complete) signal is also set HIGH at this 
time. The S signal should not be brought back HIGH until after the 
clock LOW-to-HIGH transition in order to guarantee correct resetting. 



After the clock has gone HIGH resetting the register, the S signal is 
removed. On the next clock LOW-to-HIGH transition the data on the 
D input is set into the 07(11) register bit and the QgOO) register bit is 
set to a LOW ready for the next clock cycle. On the next clock LOW- 
to-HIGH transition data enters the Qg(10) register bit and Q5O) is set 
to a LOW. This operation is repeated for each register bit in turn until 
the register has been filled. When the data goes into Qq, the CC signal 
goes LOW, and the register is inhibited from further change until reset 
by a Start signal. 

In order to allow complementary conversion the complementary 
output of the most significant register bit is made available. An active 
LOW enable input, E, on the Am25L03 and Am25L04 allows devices 
to be connecte_d together to form a longer register by connecting the 
clock, D, and_S inputs together and connecting the CC output of one 
device to the E input of the next less significant device. When the Start 
signal resets the register, the E signal goes HIGH, forcing the 07(1 1 ) bit 
HIGH and inhibiting the device from accepting data until the previous 
device is full and its CC goes LOW. If only one device is used the E 
input should be held at a LOW logic level (G_round). For continuous 
conversion the CC output is connected to the S input so that the device 
automatically restarts at the end of a conversion. If all the bits are 
not required, the register may be truncated and conversion time saved 
by using a register output going LOW rather than the CC signal to 
indicate the end of conversion. 



LOGIC DIAGRAMS 




1. Cell logic is repeated for register stages. Qg to Qi Am25L02/3, Qg to Q} Am25L04. 

2. Numbers in parentheses are for Am25L04. 



LOGIC SYMBOLS 



Qf Q E Q 5 O a Q 3 Q; Q 



T II I II I M 



V cc = p in 16 
GND - Pin 8 



o n q i0 QaQa o 7 q 6 o 5 a„ o 3 a, □, Oq 

TTTI 



TT 



v C c 

GND 
NC = 



- Pin 24 
=■ Pin 12 
Pins 10, 1 



CONNECTION DIAGRAMS 
Top Views 



■C 
gndQ 



An:/": ACl 
US-Pinf 



3- 

3°' 

□ °. 

□ °. 

^CP 



EC 
00 C 

«c 

o«C 

°>c 

a,C 

'C 

»:C 
0C 

GNO 



2, n»ce 
» □=„ 
n 3»c 
!. Zl°n 

30 □ Q I0 
„ 3 0, 

Do, 

do, 
« 3°. 

15 3 NC 

□! 
10 □ CP 



Note: Pin 1 is marked for orientation. 



3-24 



Am25L02/L03/L04 



MAXIMUM RATINGS (Above which the useful life may be impaired) 






Storage Temperature 




-65°Cto+150°C 


Temperature (Ambient) Under Bias 




-55°C to +125°C 


Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous 




-0.5V to +7V 


DC Voltage Applied to Outputs for High Output State 




-0.5V to +V CC max. 


DC Input Voltage 




-0.5V to +5.5V 


Output Current, Into Outputs 




30 mA 


DC Input Current 




-30 mA to +5.0 mA 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) 



Am25L02XC 
Am25L02XM 

Parameters 



Am25L03XC 
Am25L03XM 



Am25L04XC 
Am25L04XM 



Description 



T. = C to +75 C 



Test Conditions 



Min. 



Typ.fNote 1) 



Max. 



Units 



V H 


Output HIGH Voltage 


V cc = MIN., I H = -0.4mA 
V|N » V| H or V| L 


2.4 


3.6 




Volts 


vol 


Output LOW Voltage 


V C c - MIN., Iql = 4.92mA 
V IN " V IH or V IL 




0.15 


0.3 


Volts 


V|H 


Input HIGH Level 


Guaranteed Input logical HIGH 
voltage for all inputs 


2.0 






Volts 


V IL 


Input LOW Level 


Guaranteed input logical LOW 
voltage for all inputs 






0.7 


Volts 


•|L 


Input LOW Current 


V CC = MAX., V 




CP,D,S 




-0.25 


-0.4 


mA 


| N =■ 0.3V 


E 




-0.4 


-0.6 


■|H 


Input HIGH Current 


Vcc * MAX., V 




CP, D 




2.0 


20 


ma 


IN « 2.4V 


E, S 




4.0 


40 


Input HIGH Current 


VCC ■ MAX., V| N = 5.5V 






1.0 


mA 


!SC 


Output Short Circuit Current 


V C C = MAX., V O UT = 0.0V 


4.0 


15 


35 


mA 


'CC 


Power Supply Current 


V CC - MAX. 


Am25L02 


XM 




25 


33 


mA 


XC 




25 


35 


Am25L03 


XM 




22 


31 


mA 


XC 




22 


33 


Am25L04 


XM 




30 


42 


mA 


XC 




30 


45 



Notes: 1 
2 



Typical limits are at V C c * 5.0V, 25°C ambient and maximum loading. 

VqlIMAX) - 0.3V with total device fanout of less than 90 Low Power TTL Unit Loads (36mA), otherwise, VqlIMAX) = 0.35V. 



Switching Characteristics (Ta = 25°C, Vcc = 5.0V, Cl = l5pF) 



Parameters 


Description 




Min. 


Typ. 


Max. 


Units 


tpd+ 


Turn Off Delay CP to Output HIGH (except Q<| i, Q<|j) 


20 


75 


110 


ns 


tpd + 


Turn Off Delay CP to Qi i or Q-| ^ HIGH 


30 


100 


140 


ns 


tpd- 


Turn On Delay CP to Output LOW 


20 


75 


100 


ns 


t s (D) 


Set-up Time Data Input 


-15 


8.0 


20 


ns 


t s (S) 


Set-up Time Start Input 





20 


25 


ns 


tpd+tE) 


Turn Off Delay E to Q 7 (11) HIGH 


(Am25L03/Am25L04) 




50 


75 


ns 


tpd (E) 


Turn On Delay EtoQ 7 (11| LOW 


Cp - H,S = L 




60 


75 


ns 


tpwL<CP) 


Minimum LOW Clock Pulse Width 




100 


150 


ns 


«pwH(CP) 


Minimum HIGH Clock Pulse Width 




70 


100 


ns 


*max. 


Maximum Clock Frequency 


3.5 


5.0 




MHz 



3-25 



Am25L02/L03/L04 



Am25L02/3 TRUTH TABLE 



Time Inputs 



Outputs 





D 


s 


E 


D 


Q 7 


Q 6 


Q 5 


Q 4 


Q 3 


Q 2 Q, 


Q 


CC 


n 


x 


l_ 


L 


x 


X 


X 


X 


X 


x 


X X 


x 


x 


1 


7 


H 


L 


X 


L 


H 


H 


H 


H 


H H 


H 


H 


2 


D 6 


H 


L 


D 7 


D ? L 


H 


H 


H 


H H 


H 


H 


3 


D 5 


H 


L 


D 6 


D 7 


D 6 


L 


H 


H 


H H 


H 


H 


4 


D 4 


M 


L 


D 5 


D 7 


D 6 


D 5 


L 


H 


H H 


H 


H 


5 


D 3 


H 


L 


D 4 


D 7 


D 6 


D 5 


D 4 


L 


H H 


H 


H 


6 


D 2 


H 


L 


D 3 


D 7 


D 6 


D 5 


D 4 


D 3 


L H 


H 


H 


7 


D 1 


H 


L 


D 2 


D 7 


D 6 


D 5 


D 4 


D 3 


D 2 L 


H 


H 


8 


D 


H 


L 


D 1 


D 7 


D 6 


D 5 


D 4 


°3 


D 2 D 1 


L 


H 


9 


X 


H 


L 


D 


D 7 


D 6 


°5 


D 4 


D 3 


D 2 D, 


D 


L 


10 


X 


X 


L 


X 


°7 


D 6 


°5 


°4 


°3 


D 2 


D 


L 




X 


X 


H 


X 


H 


NC 


NC 


NC 


NC 


NC NC 


NC 


NC 



H = HIGH Voltage Level 
L ■ LOW Voltage Level 
X = Don't Care 
NC = No Change 

Note: Truth Table for Am25L04 is extended to include 
12 outputs. 



USER NOTES FOR A/D CONVERSION 

1. The register can be used with either current switches 
that require a low voltage level to turn the switch on, 
or current switches that require a high voltage level to 
turn the current switch on. If current switches are used 
which turn on with a low logic level the resulting digital 
output from the register is active LOW. That is, a logic 
" 1 " is represented as a low voltage level. If current swit- 
ches are used that turn on with a high logic level then 
the digital output is active HIGH; a logic "1 " is repre- 
sented as a high voltage level. 

2. For a maximum digital error of ±%LSB the comparator 
must be biased. If current switches that require a low 
voltage level to turn on are used, the comparator should 
be biased +HLSB and if the current switches require a 
high logic level to turn on then the comparator must be 
biased — ViLSB. 

3. The register, by suitable selection of resistor ladder net- 
work, can be used to perform either binary or BCD 
conversion. 

4. The register can be used to perform 2's complement 
conversion by offsetting the comparator 1 / 2 full range 
+54 LSB and using the complement of the MSB 
Q 7 (1 1 ) as the sign bit. 

5. If the register is truncated and operated in the contin- 
uous conversion mode a lock-up condition may occur on 
power-on. This situation can be overcome by making 
the START input the OR function of CC and the appro- 
priate register output. 



SWITCHING TIME WAVEFORMS 




KEY TO TIMING DIAGRAM 



m 
urn 



MAY CHANGE 



MAY CHANGE 



CHANGING 



FROM H TO L F ROM H TO L 



WILL BE 

FROM I Tfl H CHANGING 
FROM L TO H pR0M L TQ H 



DON'T CARE; CHANGING, 
ANY CHANGE STATE 
PERMITTED UNKNOWN 



I25L03. 25LQ4> 








APPLIES ONLY WHEN 5TAPT-SIGN 
DURING PREVIOUS CLOCK PERIOI 



3-26 



Am25L02/L03/L04 



Am25L02/3 TIMING CHART 



CLOCK 
START 
DATA 

°' ! 
° 6 '. 

°« 

°2 



J L 



J L 



i r 



: r 



i r 



Am25L02/3/4 APPLICATION 
Continuous Conversion Analog-to-Digital Converter 



GND 
CLOCK 



O,, O^Qg Og • • • • Q 3 2 Q, Qq 



SERIAL DATA OUT 



T PARALLEL 
i DATA 
A OUT 



12 BIT D/A CONVERTER 



> 



ANALOG INPUT - 



COMPARATOR 



This shows how the Am25L02/3/4 registers are used with a Digital-to-Analog converter and a comparator to form a very high-speed 
continuous conversion Analog-to-Digital converter. Conversion time is limited mainly by the speed of the D/A converter and comparator 
with typical conversion rates of 300,000 conversions per second. The comparator can be the Ami 1 1 precision comparator, or Ami 06 
high-speed comparator. 



Am25L02 



Metallization and Pad Layout 
Am25L03 



Am25L04 




24 CC 




DIE SIZE 0.087" X 0.105" 



DIE SIZE 0.087" X 0. 105" 



DIE SIZE 0.087" X 0.135" 



3-27 



Am6070 

Companding D-to-A Converter for Control Systems 



Distinctive Characteristics 

• Tested to /x-255 companding law 

• Absolute accuracy specified - includes all errors over 
temperature range 

• Settling time 300ns typical 

• Ideal for multiplexed PCM, audio, and 8-bit /x-P 
systems 

• Output dynamic range of 72 dB 

• 12-bit accuracy and resolution around zero 



• Sign plus 12-bit range with sign plus 7-bit coding 

• Improved pin-for-pin replacement for DAC-76 

• Microprocessor controlled operations 

• Multiplying operation 

• Negligible output noise 

• Monotonicity guaranteed over entire dynamic range 

• Wide output voltage compliance 

• Low power consumption 



GENERAL DESCRIPTION 



The Am6070 monolithic companding D/A converter achieves 
a 72dB dynamic range which is equivalent to that achieved 
by a 12-bit converter. 

The transfer function of the Am6070 complies with the Bell 
system /i-255 companding law, and consists of 15 linear 
segments or chords. A particular chord is identified with the 
sign bit input, (SB) and three chord select input bits. Each 
chord contains 16 uniformly spaced linear steps which are 



determined by four step select input bits. Accuracy and 
monotonicity are assured by the internal circuit design and 
are guaranteed over the full temperature range. 

Applications for the Am6070 include digital audio recording, 
servo-motor controls, electromechanical positioning, voice 
synthesis, secure communications, microprocessor con- 
trolled sound and voice systems, log sweep generators and 
various data acquisition systems. 



FUNCTIONAL BLOCK DIAGRAM 



/ Bj **2 Bp 1 



8* 8 S Bg B 7 4 

o o o o 



CHORD DECODER 



i r 



CONNECTION DIAGRAM 
Am6070 



ENCODE/DECODE SELECT: 1 = ENCODE 1 

SIGN BIT INPUT: 1 = POSITIVE 2 Q 

MOST SIGNIFICANT CHORD BIT INPUT 3 L7 

SECOND CHORD BIT INPUT 4 Q 

LEAST SIGNIFICANT CHORD BIT INPUT 5 Q 

MOST SIGNIFICANT STEP BIT INPUT 6 [J 

SECOND STEP BIT INPUT 7[~ 

THIRD STEP BIT INPUT 8 £ 

LEAST SIGNIFICANT STEP BIT INPUT 3 [J 




18 POSITIVE POWER SUPPLY 

I? DECODER OUT: E/D SB = 00 

16 DECODER OUT: E/D SB = 01 

2 16 ENCODER OUT: E'D SB =10 

2 14 ENCODER OUT: E/D SB = 11 

2 13 NEGATIVE POWER SUPPLY 

^] 12 NEGATIVE REFERENCE INPUT 

2 11 POSITIVE REFERENCE INPUT 

□ 10 THRESHOLD CONTROL 



Top View 
Pin 1 is marked for orientation. 



ORDERING INFORMATION 



SIMPLIFIED CONVERSION TRANSFER FUNCTIONS 



Decoder 
Characteristic 



Encoder 
Characteristic 



Part Number 


Temperature 


Accuracy 


Am6070ADM 


-55°C to + 125°C 


±1/2 step 


Am6070DM 


-55°Cto +125X 


±1 step 


Am6070ADC 


0°C to +70°C 


±1/2 step 


Am6070DC 


0°C to + 70°C 


±1 step 




3-28 



Am6070 



MAXIMUM RATINGS above which useful life may be impaired 



V+ Supply to V- Supply 


36V 


Operating Temperature 


V|_c Swing 


V— plUS OV tO V + 


MIL Grade 


—bo L. to +1 zb L, 


Output Voltage Swing 


V nine PA/ tn \f nine *3fi\/ 

V — pi Ub OV lO V — piUbODV 


COM'L Grade 


0°Cto +70° C 


Reference Inputs 


V- to V+ 


Storage Temperature 


-65°Cto+150°C 


Reference Input Differential Voltage 


±18V 


Power Dissipation Ta < 100° C 


500mW 


Reference Input Current 


1.25mA 


For Ta > 100°C derate at 


10mW/°C 


Logic Inputs 


V-plus 8V to V- plus 36V 


Lead Soldering Temperature 


300° C (60 sec) 



GUARANTEED FUNCTIONAL SPECIFICATIONS 



Resolution 


± 1 28 Steps 


Monotonicity 


For both groups of 128 steps and over full operating temperature range 


Dynamic Range 


72dB, (20log(l 7j15 /lo, 1)) 



ELECTRICAL CHARACTERISTICS 

These specifications apply for V+ = +15V, V- = -15V, l REF = 528ju.A, 0°C sT A =s +70°C, for the commercial grade, -55°C sT A s 
+ 125C, for the military grade, and for all 4 outputs unless otherwise specified. Am6070ADM Am6070DM 

Am6070ADC Am6070DC 

Parameter Description Test Conditions Min. Typ. Max. Min. Typ. Max. Units 



«5 




Settling Time 


To within ±1/2 step at T A = 25°C 
output switched from 
Izs to !fs 




300 


500 




300 


500 


ns 


'fSID) 
'fS(E) 




Chord Endpoint Accuracy 


Guaranteed by output 
current error specified 
below. 






±1/2 






±1 


Step 


Step Nonlinearity 






±1/2 






±1 


Step 


Full Scale Current Deviation 
From Ideal 






±1/2 






±1 








±1/2 






±1 




Al 




Output Current Error 


V REF = 10.000V 

R REF+ = 18.94kn 

R REF _ = 20kfl 

-5.0V s V 0UT s +18V 

Error referred to nominal values 

in Table 1. 






±1/2 






±1 


Step 


'cx+i-'oi 


-) 


Full Scale Symmetry Error 


w nrr — in nnnv 

v REF — IU.UUUV 

R REF+ = 18.94kn 
R REF = 20kfl 

-5.0V s V OUT « +18V 

Error referred to nominal values 

in Table 1 




1/40 
1/40 


1/8 
1/8 




1/20 
1/20 


1/4 
1/4 


Step 
Step 


'en 




Encode Current 


Additional output 
Encode/Decode = 1 


3/8 


1/2 


5/8 


1/4 


1/2 


3/4 


Step 


•zs 




Zero Scale Current 


Measured at selected output 
with 000 0000 input 




1/40 


1/4 




1/20 


1/2 


Step 


Mfs 


Full Scale Drift 


Operating temperature range 




±1/20 


±1/4 




±1/10 


±1/2 


Step 


Vqc 


Output Voltage Compliance 


Full scale current change 
«1/2 step 


-5.0 




+ 18 


-5.0 




+ 18 


Volts 


bis 


Disable Current 


Output leakage 

Output disabled by E/D and SB 




5.0 


50 




5.0 


50 


nA 


'FSR 


Output Current Range 







2.0 


4.2 





2.0 


4.2 


mA 


V|L 
V| H 


Logic Input Levels 


Logic "0" 


V LC - 0V 


2.0 




0.8 


2.0 




0.8 


Volts 


Logic "1" 


■in 


Logic Input Current 


V| N = -5.0V to +18V 






40 






40 


MA 


Vis 


Logic Input Swing 


V- = -15V 


-5.0 




-18 


-5.0 




+ 18 


Volts 


!b ref- 


Reference Bias Current 






-1.0 


-4.0 




-1.0 


-4.0 


fiA 


di/dt 


Reference Input Slew Rate 




0.12 


0.25 




0.12 


0.25 




mA//ns 


PSSI FS+ 
PSSIps- 


Power Supply Sensitivity 
Over Supply Range (Refer 
to Characteristic Curves) 


V+ = 4.5 to 18V, V- = -15V 
V- = 10.8 + -18V, V+ = 15V 


±1/20 
±1/10 


±1/2 
±1/2 




±1/20 
±1/10 


±1/2 
±1/2 




Step 
Step 


14 
1- 


Power Supply Current 


V+ = +5.0 to +15V. V- = -15V 
l FS = 2.0mA 




2.7 
-6.7 


4.0 

-8.8 




2.7 
-6.7 


4.0 
-8.8 


mA 


P D 


Power Dissipation 


V- = -15V, V OU T = 
l FS = 2.0mA 


V+ = 5.0V 




114 
141 


152 
192 




114 
141 


152 
192 


mW 


V+ = +15V 



3-29 



Am6070 



ELECTRICAL CHARACTERISTICS (Cont.) 



TABLE 1 

NOMINAL DECODER OUTPUT CURRENT LEVELS IN /xA 



STEP 


CHORD 





1 


2 


3 


4 


5 


6 


7 





.000 


8.250 


24.750 


57.750 


123.75 


255.75 


519.75 


1047.75 


1 


.500 


9.250 


26.750 


61.750 


131.75 


271.75 


551.75 


1111.75 


2 


1.000 


10.250 


28.750 


65.750 


139.75 


287.75 


583.75 


1175.75 


3 


1.500 


11.250 


30.750 


69.750 


147.75 


303.75 


615.75 


1239.75 


4 


2.000 


12.250 


32.750 


73.750 


155.75 


319.75 


647.75 


1303.75 


5 


2.500 


13.250 


34.750 


77.750 


163.75 


335.75 


679.75 


1367.75 


6 


3.000 


14.250 


36.750 


81.750 


171.75 


351.75 


711.75 


1431.75 


7 


3.500 


15.250 


38.750 


85.750 


179.75 


367.75 


743.75 


1495.75 


8 


4.000 


16.250 


40.750 


89.750 


187.75 


383.75 


775.75 


1559.75 


9 


4.500 


17.250 


42.750 


93.750 


195.75 


399.75 


807.75 


1623.75 


10 


5.000 


18.250 


44.750 


97.750 


203.75 


415.75 


839.75 


1687.75 


11 


5.500 


19.250 


46.750 


101.750 


211.75 


431.75 


871.75 


1751.75 


12 


6.000 


20.250 


48.750 


105.750 


219.75 


447.75 


903.75 


1815.75 


13 


6.500 


21.250 


50.750 


109.750 


227.75 


463.75 


935.75 


1879.75 


14 


7.000 


22.250 


52.750 


113.750 


235.75 


479.75 


967.75 


1943.75 


15 


7.500 


23.250 


54.750 


117.750 


243.75 


495.75 


999.75 


2007.75 


STEP 
SIZE 


.5 


1 


2 


4 


8 


16 


32 


64 



TABLE 2 

DECODER OUTPUT VALUES EXPRESSED IN dB DOWN FROM FULL SCALE 



STEP 








CHORD 













1 


2 


3 


4 


5 


6 


7 







-47.73 


-38.18 


-30.82 


-24.20 


-17.90 


-11.74 


-5.65 


1 


-72.07 


-46.73 


-37.51 


-30.24 


-23.66 


-17.37 


-11.22 


-5.13 


2 


-66.05 


-45.84 


-36.88 


-29.70 


-23.15 


-16.87 


-10.73 


-4.65 


3 


-62.53 


-45.03 


-36.30 


-29.18 


-22.66 


-16.40 


-10.27 


-4.19 


4 


-60.03 


-44.29 


-35.75 


-28.70 


-22.21 


-15.96 


-9.83 


-3.75 


5 


-58.10 


-43.61 


-35.24 


-28.24 


-21.77 


-15.53 


-9.41 


-3.33 


6 


-56.51 


-42.98 


-34.75 


-27.80 


-21.36 


-15.13 


-9.01 


-2.94 


7 


-55.17 


-42.39 


-34.29 


-27.39 


-20.96 


-14.74 


-8.63 


-2.56 


8 


-54.01 


-41.84 


-33.85 


-26.99 


-20.58 


-14.37 


-8.26 


-2.19 


9 


-52.99 


-41.32 


-33.44 


-26.61 


-20.22 


-14.02 


-7.91 


-1.84 


10 


-52.07 


-40.83 


-33.04 


-26.25 


-19.87 


-13.68 


-7.57 


-1.51 


11 


-51.25 


-40.37 


-32.66 


-25.90 


-19.54 


-13.35 


-7.25 


-1.18 


12 


-50.49 


-39.93 


-32.29 


-25.57 


-19.22 


-13.03 


-6.93 


-0.87 


13 


-49.80 


-39.51 


-31.95 


-25.25 


-18.91 


-12.73 


-6.63 


-0.57 


14 


-49.15 


-39.11 


-31.61 


-24.94 


-18.61 


-12.43 


-6.34 


-0.28 


15 


-48.55 


-38.73 


-31.29 


-24.63 


-18.32 


-12.15 


-6.06 


0.00 



3-30 



AmB070 



THEORY OF OPERATION 
Functional Description 

The Am6070 is an 8-bit, nonlinear, digital-to-analog conver- 
ter with high impedance current outputs. The output current 
value is proportional to the product of the digital inputs and 
the input reference current. The full scale output current, I FS , 
is specified by the input binary code 111 1111, and is a linear 
function of the reference current, l REF . There are two operat- 
ing modes, encode and decode, which are controlled by the 
Encode/Decode, (E/D), input signal. A logic 1 applied to the 
E/D input places the Am6072 in the encode mode and current 
will flow into the Ioe<+) or 'oe(-) output, depending_on the 
state of the Sign Bit (SB) input. A logic at the E/D input 
places the Am6070 in the decode mode. 

The transfer characteristic is a piece-wise linear approxi- 
mation to the Bell System pi-225 logarithmic law which 
can be written as follows: 



i wri 



Y = 0.182n (1 + ft IXI ) sgn (X) 

where: X = analog signal level normalized to unity 
(encoder input or decoder output) 
Y = digital signal level normalized to unity 
(encoder output or decoder input) 

fj. = 255 

The current flows from the external circuit into one offour 
possible analog outputs determined by the SB and E/D in- 
puts. The output current transfer function can be represented 
by a total of 16 segments or chords addressable through the 
SB input and three chord select bits. Each chord can be 
further divided into 16 steps, all of the same size. The step 
size changes from one chord to another, with the smallest 
step of 0.5nA found in the first chord near zero output cur- 
rent, and the largest step of 64/xA found in the last chord near 
full scale output current. This nonlinear feature provides 
exceptional accuracy for small signal levels near zero output 
current. The accuracy for signal amplitudes corresponding 
to chord is equivalent to that of a 12-bit linear, binary D/A 
converter. However, the ratio (in dB) between the chord 





ANALOG 
OUTPUT 

:5.0V 



6 -1SV 6 *1SV 

!ref ■ Vref'Rref 

IDEAL VALUES: l REF = 528/iA, l FS = 2007.75mA 





E/D 


SB 


Bl 


B 2 


B3 




B 5 


Be 


B7 




POSITIVE FULL SCALE 





1 


1 


1 






1 


i 


1 


5.019V 


1 + ) ZERO SCALE +1 STEP 





i 











'"i 


i) 







0.0012V 


<*) ZERO SCALE 




























0V 


!-)Z£RO SCALE 











□ 

















OV 


(-1 ZERO SCALE +1 STEP 


























1 


-0.001 2V 


NEGATIVE FULL SCALE 








1 


1 


: 


1 


i 




■ 


-5.019V 



endpoint current, (Step 15), and the current which corres- 
ponds to the preceding step, (Step 14), is maintained at about 
0.3dB over most of the dynamic range. The difference bet- 
ween the ratios of full scale current to chord endpoint cur- 
rents of adjacent chords is similarly maintained at approxi- 
mately 6dB over most of the dynamic range. Resulting 
signal-to-quantizing distortions due to non-uniform quantiz- 
ing levels maintain an acceptably low value over a 40dB 
range of input speech signals. Note that the 72dB output 
dynamic range for the Am6070 corresponds to the dynamic 
range of a sign plus 12-bit linear, binary D/A converter. 

In order to achieve a smoother transition between adja- 
cent chords, the step size between these chord end points 
is equal to 1.5 times the step size of the lower chord. 
Monotonic operation is guaranteed by the internal device 
design over the entire output dynamic range by specify- 
ing and maintaining the chord end points and step size 
deviations within the allowable limits. 

Operating Modes 

The basic converter function is conversion of digital input 
data into a corresponding analog current signal, i.e., the 
basic function is digital-to-analog decoding. The basic de- 
coder connection for a sign plus 7-bit input configuration is 
shown in Figure 1. The corresponding dynamic range is 
72dB, and input-output characteristics conform to the stan- 
dard decoder transfer function with output current values 
specified in Table 1. The E/D input enables switching bet- 
ween the encode, Ioe(+) or Ioe(-). and the decode, Iod(+) or 
'od(-). outputs. Atypical encode/decode test circuit is shown 
in Figure 2. This circuit is used for output current measure- 
ments. When the E/D input is high, (a logic 1 ), the converter 
will assume the encode operating mode and the output cur- 
rent will flow into one of the Iqe outputs (as determined by 
the SB input). When operating in the encode mode as shown 
in Figure 3, an offset current equal to a half step in each chord 
is required to obtain the correct encoder transfer characteris- 
tic. Since the size of this step varies from one chord to 
another, it cannot easily be added externally. As indicated in 
the block diagram this required half step of encode current, 



Figure 1. Detailed Decoder Connections. 



DIGITAL INPUTS 



B 7 B 6 B 5 B 4 B 3 B 2 B l SB E/D 



p r F 





Rl » R2 ■ R3 - R4 ■ 2.5kn ±0.1% 

LINE SELECTION TABLE 




TEST 






OUTPUT 


GROUP 


E/D 


SB 


MEASUREMENT 


1 






'OE ( + ) 


(Eot/H,) 


2 


1 





lOE ("I 


IEoi'R 2 > 


3 





1 


lOD <+> 


IE02/R3) 


4 








iod'-I 


iE 02 R 4 ! 



Figure 2. Output Current DC Test Circuit. 



3-31 



Am6070 



l EN , is automatically added to the I e output through the 
internal chip design. This additional current will, for exam- 
ple, make the ideal full scale current in the encode mode 
larger than the same current in the decode mode by 32/j.A. 
Similarly, the current levels in the first chord near the origin 
will be offset by 0.25/iA, which will bring the ideal encode 
current value for step on chord to ±0.25/n.A with respect to 
the corresponding decode current value of O.OjuA. This addi- 
tional encode half step of current can be used for extension 
of the output dynamic range from 72dB to 78dB, when the 
converter is performing only the decode function. The cor- 
responding decoder connection utilizes the E/D input as a 
ninth digital input and has the outputs I d(+) a nd 'oem and 
the outputs l 0D (-) and loE(-) tied together, respectively. 



input signal of the Am2502 to its MSB output, and transfers it 
to the SB input of the Am6070. Depending upon the SB input 
level, current will flow into the Ioe(+) or 'oe(-) output of the 
Am6070. 

Nine total clock pulses are required to obtain a digital binary 
representation of the incoming analog signal at the eight 
Am2502 digital outputs. The resulting Am6070 analog out- 
put signal is compared with the analog input signal after 
each of the nine successive clock pulses. The analog signal 
should not be allowed to change its value during the data 
conversion time. In high speed systems, fast changes of the 
analog signals at the AID system input are usually prevented 
by using sample and hold circuitry. 



When encoding or compression of an analog signal is re- 
quired, the Am6070 can be used together with a Successive 
Approximation Register (SAR), comparator, and additional 
SSI logic elements to perform the AID data conversion, as 
shown in Figure 3. The encoder transfer function, shown on 
page 1 , characterizes this AID converter system. The f i rst task 
of this system is to determine the polarity of the incoming 
analog signal and to generate a corresponding SB input 
value. When the proper Start, S, and Conversion Complete, 
CC, signal levels are set, the first clock pulse sets the MSB 
output of the SAR, Am2502, to a logic and sets all other 
parallel digital outputs to logic 1 levels. At the same time, the 
flip-flop is triggered, and its output provides the E/D input 
with a logic level. No current flows into the I e outputs. This 
disconnects the converter from the comparator inputs, and 
the incoming analog signal can be compared with the 
ground applied to the opposite comparator input. The result- 
ing comparator output is fed to the Am2502 serial data input, 
D, through an exclusive-or gate. At the same time, the sec- 
ond input to the same exclusive-or gate is held at a logic 
level by the additional successive approximation logic 
shown in Figure 3. This exclusive-or gate inverts the com- 
parator's outputs whenever a negative signal polarity is de- 
tected. This maintains the proper output current coding, i.e., 
all ones for full scale and all zeros for zero scale. 

The second clock pulse changes the E/D input back to a logic 
1 level because the CC signal changed. It also clocks the D 



Additional Considerations and Recommendations 

In Figure 1, an optional operational amplifier converts the 
Am6070 output current to a bipolar voltage output. When the 
SB input is a logic 1, sink current appears at the amplifier's 
negative input, and the amplifier acts as a current to voltage 
converter, yielding a positive voltage output. With the SB 
value at a logic 0, sink current appears at the amplifier's 
positive input. The amplifier behaves as a voltage follower, 
and the true current outputs will swing below ground with 
essentially no change in output current. The SB input steers 
current into the appropriate (+) or (-) output of the Am6070. 
The resulting operational amplifier's output in Figure 1 
should ideally be symmetrical with resistors R1 and R2 
matched. 

In Figure 2, two operational amplifiers measure the cur- 
rents of each of the four Am6070 analog outputs. Resistor 
tolerances of 0.1% give 0.1% output measurement error 
(approximately 2/xA at full scale). The input offset currents 
of the A1 and A2 devices also increase output measure- 
ment error and this error is most significant near zero 
scale. The Am101A and 308 devices, for example, may be 
used for A1 and A2 since their maximum offset currents, 
which would add directly to the measurement error, are 
only 10nA and 1nA, respectively. The input offset voltages 
of the A1 and A2 devices, with output resistor values of 



ANALOG INPUT 




CLOCK START +S.0V 

O 



J 




1 



* SERIAL 
— O DATA 
OUTPUT 



Am2502 

SUCCESSIVE APPROXIMATION 
REGISTER (SAR) 




2 3 4 5 6 7 



1 



E/D SB Bi By B, B, Be Be B , 



Am6070 

COMPANDING 
D TO A CONVERTER 



131 18 I 

0-15V O 

Figure 3. Detailed Encoder Connections. 




15V 



PARALLEL 

DATA 

OUTPUT 



R REF(+) 



R REF(-I 



LIC-248 



3-32 



Am6070 



2.5kfl, also contribute to the output measurement error by 
a factor of 400nA for every mV of offset at the A1 and A2 
outputs. Therefore, to minimize error, the offset voltages 
of A1 and A2 should be nulled. 



The recommended operating range for the reference cur- 
rent Iref is from 0.1mA to 1.0mA. The full scale output 
current, l F g, is a linear function of the reference current, 
and may be calculated from the equation l FS = 3.8 l REF . 
This tight relationship between l REF and l FS alleviates the 
requirement for trimming the l REF current if the R REF re- 
sistors values are within ±1% of the calculated value. 
Lower values of l REF will reduce the negative power sup- 
ply current, (I-), and will increase the reference amplifier 
negative common mode input voltage range. 

The ideal value for the reference current l REF = V REF /R REF is 
528/xA. The corresponding ideal full scale decode and en- 
code current values are 2007.75/u.A and 2039.75/u.A, respec- 
tively. A percentage change from the ideal l REF value pro- 
duced by changes in V REF or R REF values produces the same 
percentage change in decode and encode output current 
values. The positive voltage supply, V+, may be used, with 
certain precautions, for the positive reference voltage V REF . 
In this case, the reference resistor R REF(+) should be split into 
two resistors and their junction bypassed to ground with a 
capacitor of 0.01 /uF. The total resistor value should provide 
the reference current l REF = 528^A. The resistor R REF( _) 
value should be approximately equal to the R REF(+) value in 
order to compensate for the errors caused by the reference 
amplifier's input offset current. 



An alternative to the positive reference voltage applications 
shown in Figures 1, 2 and 3 is the application of a negative 
voltage to the V R( _) terminal through the resistor R REF( _) 
with the R REF (+) resistor tied to ground. The advantage of 
this arrangement is the presence of very high impedance at 
the V R( _) terminal while the reference current flows from 
ground through R REF(+) into the V R(+) terminal. 



The Am6070 has a wide output voltage compliance suit- 
able for driving a variety of loads. With l REF = 528/iA and 
V- = -15V, positive voltage compliance is +18V and 
negative voltage compliance is -5.0V. For other values of 
l REF and V-, the negative voltage compliance, V c(-)< 
may be calculated as follows: 



Voc(-) = (V-) + (2.| REF . 1.5kfl) 

The following table contains V c(- 
specific V-, l REF , and l FS values. 



8.4V. 

values for some 



Negative Output Voltage Compliance Vqc(— ) 



'ref 

v _\<!fs> 


264*iA 
(1mA) 


528mA 
(2mA) 


1056/iA 
(4mAj 


-12V 


-2.8V 


-2.0V 


-0.4V 


-15V 


-5.8V 


-5.0V 


-3.4V 


-18V 


-8.8 V 


-8.0V 


-6.4V 



The V LC input can accommodate various logic input 
switching threshold voltages allowing the Am6070 to in- 
terface with various logic families. This input should be 
placed at a potential which is 1.4V below the desired logic 
input switching threshold. Two external discrete circuits 
which provide this function for non-TTL driven inputs are 
shown in Figure 4. For TTL-driven logic inputs, the V LC 
input should be grounded. If negative voltages are 
applied at the digital logic inputs, they must have a value 
which is more positive than the sum of the chosen V- 
value and +10V. 

With a V- value chosen between -15V and -11V, the 
V c( ), the input reference common mode voltage range, 
and the logic input negative voltage range are reduced by an 
amount equivalent to the difference between —15V and the 
V- value chosen. 

With a V+ value chosen between +5V and +15V, the refer- 
ence amplifier common mode positive voltage range and the 
V LC input values are reduced by an amount equivalent to the 
difference between +15V and the V+ value chosen. 



ECL 



CMOS, HTL, NMOS 







■13MI 


ZM3904 


1 391.1! 








(See Notes 2 and 3) 

Figure 4. Interfacing Circuits for ECL, CMOS, HTL, 

and NMOS Logic Inputs. lic-249 



DIGITAL INPUTS 



ooooooooo 



B 6 B S B 4 B 3 B 2 B, SB E/D | QE( ^ 



i13 I 18 I 10 

-15V 0+'5V 




4.98 ^ 

ua ; , 



INPUT CODE 
(E/D.SB, Bt B 7 > 


OUTPUT VOLTAGE (V) 


"A" 


"B" 


"C" 


DIFF 


10 111 1111 

10 110 1111 
10 000 0000 



+ 5.02 
+10.00 


N/A 


N/A 


N/A 


01 1111111 
01 110 1111 
01 000 0000 
00 000 0000 
OO 110 1 1 11 
00 11 1 1111 


N/A 


-5.00 
+0 02 
+5.00 
+5.00 

+ 5.00 

♦5 00 


+ 5 00 
+5.00 
+5.00 
+S.00 
♦0 02 
-5.00 


-10.00 
-4.98 



+498 
+ 10.00 



Figure 5. Resistive Output Connections. 



Notes: 2. Set the voltage "A" to the desired logic input switching threshold. 

3. Allowable range of logic threshold is typically — 5V to +13.5V when operating the companding DAC on +1 5V supplies. 



Am6070 









ADDITIONAL DECODE OUTPUT CURRENT TABLES 














Table 3 

Normalized Decoder Output (Sign Bit Excluded) 














Chord (C) 





1 


2 


3 


4 


5 


6 


7 








Step (S) 






000 


001 


010 


011 


100 


101 


110 


111 







1 
2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 


0000 
0001 
0010 
0011 
0100 
0101 
0110 
0111 
1000 
1001 
1010 
1011 
1100 
1101 
1110 

1111 



2 
4 
6 
8 
1 
12 
14 
16 
18 
20 
22 
24 
26 
28 
30 


33 
37 
41 
45 
49 
53 
57 
61 
65 
69 
73 
77 
81 
85 
89 
93 


99 
107 
115 
123 
131 
1 39 
147 
155 
163 
171 
179 
187 
195 
203 
211 
219 


231 
247 
263 
279 
295 
31 1 
327 
343 
359 
375 
391 
407 
423 
439 
455 
471 


495 
527 
559 
591 
623 
655 
687 
719 
751 
783 
815 
847 
879 
91 1 
943 
975 


1023 
1087 
1151 
1215 
1279 
1 343 
1407 
1471 
1535 
1599 
1663 
1727 
1791 
1855 
1919 
1983 


2079 
2207 
2335 
2463 
2591 
2719 
2847 
2975 
3103 
3231 
3359 
3487 
3615 
3743 
3871 
3999 


4191 
4447 
4703 
4959 
5215 
5471 
5727 
5983 
6239 
6495 
6751 
7007 
7263 
7519 
7775 
8031 






Step Size 


2 


4 


8 


16 


32 


64 


128 


256 




The normalized decode current, Oc,s>. is calculated using: where l c ,s is tn e corresponding normalized current. To ob- 
l CiS = 2(2 C (S + 16.5) - 16.5) tain normalized encode current values the corresponding 
where C = chord number; S = step number. The ideal de- normalized half-step value should be added to all entries in 
code current, (I d). in a<A is calculated using: Table 3. 

bo = ('c, s'l?, 15(norm.)) * 'fS <M-A) 










Table 4 

Normalized Encode Level (Sign Bit Excluded) 














CHORD 





1 


2 


3 


4 


5 


6 


7 






STEP 






000 


001 


010 


011 


100 


101 


110 


111 







1 
2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 


0000 
0001 
0010 
0011 
0100 
0101 
0110 
0111 
1000 
1001 
1010 
1011 
1100 
1101 
1110 

1111 


1 

3 
5 
7 
9 
11 
13 
15 
17 
19 
21 
23 
25 
27 
29 
31 


35 
39 
43 
47 
51 
55 
59 
63 
67 
71 
75 
79 
83 
87 
91 
95 


103 
111 
119 
127 
135 
143 
151 
159 
167 
175 
183 
191 
199 
207 
215 
223 


239 
255 
271 
287 
303 
319 
335 
351 
367 
383 
399 
415 
431 
447 
463 
479 


511 
543 
575 
607 
639 
671 
703 
735 
767 
799 
831 
863 
895 
927 
959 
991 


1055 
1119 
1183 
1247 
1311 
1375 
1439 
1503 
1567 
1631 
1695 
1759 
1823 
1887 
1951 
2015 


2143 
2271 
2399 
2527 
2655 
2783 
2911 
3039 
3167 
3295 
3423 
3551 
3679 
3807 
3935 
4063 


4319 
4575 
4831 
5087 
5343 
5599 
5855 
6111 
6367 
6623 
6879 
7135 
7391 
7647 
7903 
8159 






Step Size 


2 


4 


8 


16 


32 


64 


128 


256 




l c ,s = 2[2 C (S + 17) - 16.5] 
C = chord no. (0 through 7) 
S = step no. (0 through 15) 



















3-34 



Am6070 



ADDITIONAL DECODE OUTPUT CURRENT TABLES (Cont.) 



Decoder Step Size Summary 



Chord 


Step Size 
Normalized 
to Full Scale 


Step Size 
in /j A with 
2007.75mA FS 


Step Size 
as a % of 
Full Scale 


Step Size in 
dB at Chord 
Endpoints 


Step Size as a % 
of Reading at 
Chord Endpoints 


Resolution & 
Accuracy of 
Equivalent 
Binary DAC 







2 


0.5 


0.025% 


0.60 


6.67% 


Sign + 12 Bits 




1 


4 


1.0 


0.05% 


0.38 


4.30% 


Sign + 11 Bits 




2 


8 


2.0 


0.1% 


0.32 


3.65% 


Sign + 10 Bits 




3 


16 


4.0 


0.2% 


0.31 


3.40% 


Sign + 9 Bits 




4 


32 


8.0 


0.4% 


0.29 


3.28% 


Sign + 8 Bits 




5 


64 


16.0 


0.8% 


0.28 


3.23% 


Sign + 7 Bits 




6 


128 


32.0 


1.6% 


0.28 


3.20% 


Sign + 6 Bits 




7 


256 


64.0 


3.2% 


0.28 


3.19% 


Sign + 5 Bits 



Table 6 

Decoder Chord Size Summary 



Chord 


Chord Endpoints 
Normalized to 
Full Scale 


Chord Endpoints 

in juA with 
2007.75/iA FS 


Chord Endpoints 
as a % of 
Full Scale 


Chord Endpoints 

in dB Down 
from Full Scale 





30 


7.5 


0.37% 


-48.55 


1 


93 


23.25 


1.16% 


-38.73 


2 


219 


54.75 


2.73% 


-31.29 


3 


471 


117.75 


5.86% 


-24.63 


4 


975 


243.75 


12,1% 


-18.32 


5 


1983 


495.75 


24.7% 


-12.15 


6 


3999 


999.75 


49.8% 


-6.06 


7 


8031 


2007.75 


100% 






3-35 



Am6070 



BASIC CIRCUIT CONNECTIONS 



±10V RANGE ENCODER/DECODER 
CONNECTIONS 



ooooooooo 




DIGITAL INPUTS 



) *10V INPUT 
* S.OM1 



6 5 4 3 2 1 < | T~~ 

j—WV 





■±r 6 -15V 6*15V — 



COMPLIANCE EXTENSION 
USING AC COUPLED OUTPUT 




— 6 -12V 6+12V — 



IDEAL VALUES: 

IrEF " 528/jA 
l FS = 2007.75/xA 



LOW INPUT IMPEDANCE CONNECTION 



HIGH INPUT IMPEDANCE CONNECTION 



Z IN = n ,N 




DIGITAL INPUTS 



V IN t> 



I 13 Tib Tio 



!ref = Vin/Rin + Vref/Rref 

l FS «.4« Iref 




Iref - (Vref - V|N>/RreF 

l FS = 4. I REF 



LIC-253 



LOGARITHMIC DIGITAL GAIN CONTROL 

s4 & 5) 



REFERENCE AMPLIFIER DYNAMIC TEST CIRCUIT 



ATTENUATION 
* BdB/CHOftD CHANNEI 
■ ,3dB/STEP SELECT 




Q o o o o o o 



B 7 B 6 B 5 B 4 B 3 &2 B, SB E/D ,,j< 

Am«070 



>20kn 1 '3 I 18 I 11 

— O -15V O +15V — 





Notes: 4. Low distortion outputs are provided over a 72dB range. 

5. Up to 4 channels of output may be selected by E/D and SB logic inputs. 



3-36 



Am6070 



TYPICAL PERFORMANCE CURVES 



Reference Amplifier 
Total Harmonic Distortion 
Versus Frequency (80kHz Filter) 
(Notes 6, 7, 8) 



! 

• 0.05 

> 

I 0.02 
: 0.01 
: 0.005 











































See 


m 


e 8 


















































f 










































































L 


.R( 


E 


>1C 


NA 








1 




. INPUT +5V PEAK 
(50% MODULATION 
1 i I n i i i ii i 























10 100 1.0k 10k 

FREQUENCY - Hi 



Power Supply Currents 
Versus Power Supply Voltages 

8.0 ■ 

7.0 - 













1 1 1 


















































































































A 


.LB 


TS 
1 


HI 

s- 


SH' 
2.0 


OR 

TlA 


"LOW 

i 








2.0 4.0 6.0 8.0 10 12 14 16 18 20 
POSITIVE OR NEGATIVE POWER SUPPLY - V 



Bit Transfer Characteristics 
(Note 10) 



0.35 
0.30 



0.25 
0.20 
0.15 
0.10 
0.05 



I 1 I I I I 
IrEF = 0-5mA 



a 



0.055 
0.023 



-12 -8 -4 4 8 12 16 
LOGIC INPUT VOLTAGE - V 



Reference Amplifier 
Input Frequency Response 




1k 10k 1O0k 1M 
FREQUENCY - Hi 



Power Supply Currents 
Versus Temperature 



















I 

1- 




























































' F 


-2 


m 




































































A 


LL BITS 

V+-H 
1 


"H 
15\ 


GH 

,v- 




' OF 



"L 
-15 



OW 







100 

-°c 



Logic Input Current 
Versus Input Voltage 
and Logic Input Range 
(Note 11) 



1 1 

- 'ref 


= 


1 1 

).5mA 


















V- 




15V 






















'L 


























































































1 























































































-12 -8 -4 4 8 12 16 
LOGIC INPUT VOLTAGE - V 



Reference Amplifier 
Input Common-Mode Range 
(Note 9) 



T A" T MIN to T MAX 
























V- 


= -15V 






V 


+ » + 


15V 








'REF = 


0.5mA 1 




















i 






|r 


F - 


>.25i 


A } 










-o - 











-14 -10 -6 -2 2 6 10 14 18 



REFERENCE COMMON-MODE VOLTAGE 
ATV REF PIN-V 



Output Current Versus 
Output Voltage 
(Output Voltage Compliance) 











] I I 






I 




>F 


EF " 


1.0mA 




















" 'min to 'max 
































if 


E F = 


0.5mA 










































'REF - 






f 




















- - 

I 











-14 -10 -6 -2 2 6 10 14 18 
OUTPUT VOLTAGE — V 



Output Full Scale Current 
Versus Reference Input Current 




REFERENCE CURRENT, l REF - mA 



Notes: 6. THD is nearly independent of the logic input code. 

7. Similar results are obtained for a high input impedance connection using V R( _) as an input. 

8. Increased distortion above 60kHz is due to a slew rate limiting effect which determines the large signal bandwidth. For an input of ±2.5V peak (25% 
modulation), the bandwidth is 100kHz 

9. Positive common mode range is always (V+) -1.6V. 

10. All bits are fully switched with less than a half step error at switching points which are guaranteed to lie between 0.8V and 2.0V over the operating 
temperature range. 

11. The logic input voltage range is independent of the positive power supply and logic inputs may swing above the supply. 



3-37 



Am6070 



APPLICATIONS 

The companding D/A converter is particularly suited for ap- 
plications requiring a wide dynamic range. 
Systems requiring fine control resulting in a constant rate of 
change or set point controls are economically achieved 
using these devices. 

Instrumentation, Control and /i-Processor based applica- 
tions include: 

Digital data recording 

PCM telemetry systems 

Servo systems 

Function generation 

Data acquisition systems 



Telecommunications applications include 
PCM Codec telephone systems 
Intercom systems 

Military voice communication systems 
Radar systems 
Voice Encryption 



Audio Applications: 
Recording 

Multiplexing of analog signals 
Voice synthesis 





3-38 



Am6070 



SERIAL DATA TRANSCEIVING CONVERTER 
(1/2 OF SYSTEM SHOWN) 



GROUND FOR 
NON-DIFFERENTIAL 
INPUTS 




5 V+ GND 

Am2502 
ISAR) _ 
SUCCESSIVE CC 



"1 



TIME SHARED 
BI-DIRECTIONAL 
SERIAL DATA 
BUS 



-O END 6F CON 1 ". "" \_ 



E/D SB Bi B2 B3 B4 B5 B6 B7 



OUTPUT 
RECEIVE OUTPUT 



Notes: 

1. Complementary send/receive commands are required for the 
two end s. 

2. START must be held low for one clock cycle to begin a send 
or receive cycle. 



12 

Vref<-i 1 

v - vt VLC I I 

71 iBl ^ ^ 

6 -15V 6 ~r 



3. The SAR is used as a serial-in/parallel out register in the re- 
ceive mode. 

4. CLOCK and START may be connected in parallel at both ends. 

5. Conversion is completed in 9 clock cycles. 

6. Receive output is available for one full clock cycle. 



Metallization and Pad Layout 



5 «3 




» 'OEM 



80 X 114 Mils 



3-39 



Am 6071 

Companding D-to-A Converter for Control Systems 



Distinctive Characteristics 

• Tested to A-law tracking specification 

• Absolute accuracy specified - includes all errors over 
temperature range 

• Settling time 300ns typical 

• Ideal for multiplexed PCM, audio, and 8-bit /u.-P 



systems 



• Output dynamic range of 62 dB 

• Microprocessor controlled operations 

• Multiplying operation 

• Negligible output noise 

• Monotonicity guaranteed over entire dynamic range 

• Wide output voltage compliance 

• Low power consumption 



GENERAL 

The Am6071 is a monolithic 8-bit, companding digital-to- 
analog (D/A) converter with true current outputs and large 
output voltage compliance for fast driving a variety of loads. 
The transfer function of the Am6071 consists of 13 linear 
segments or chords. A particular chord is identified with the 
sign bit input, (SB) and three chord select input bits. Each 
chord contains 16 uniformly spaced linear steps which are 
determined by four step select input bits. The resulting 
dynamic range achieved with this format is 62 dB. Accuracy 



DESCRIPTION 

and monotonicity are assured by the internal circuit design 
and are guaranteed over the full temperature range. The 
Am6071 is tested to the A-law tracking specification. Applica- 
tions for the Am6071 include digital audio recording, servo 
motor controls, electro-mechanical positioning, voice 
synthesis, secure communications, microprocessor con- 
trolled sound and voice systems, log sweep generators, and 
various data acquisition systems. 



FUNCTIONAL BLOCK DIAGRAM 



CHORD BITS 



B 4 B 5 B 6 B 7 

9 9 9 9 

6 7 6 9 



SELECTOR 



HI-) 



i r 



CHORO AND 
PEDESTAL 
SOURCES 



13 IB 



CONNECTION DIAGRAM 
Am6072 



ENCODE/DECODE SELECT: 1 = ENCODE 
SIGN BIT INPUT: 1 = POSITIVE 
MOST SIGNIFICANT CHORD BIT INPUT 
SECOND CHORD BIT INPUT 
LEAST SIGNIFICANT CHORD BIT INPUT 
MOST SIGNIFICANT STEP BIT INPUT 
SECOND STEP BIT INPUT 
THIRD STEP BIT INPUT 
LEAST SIGNIFICANT STEP BIT INPUT 




POSITIVE POWER SUPPLY 
DECODER OUT: E/DSB = 00 
DECODER OUT: E/DSB = 01 
ENCODER OUT: E/D SB -10 
ENCODER OUT: E/DSB = 11 
NEGATIVE POWER SUPPLY 
NEGATIVE REFERENCE INPUT 
POSITIVE REFERENCE INPUT 
THRESHOLD CONTROL 



Top View 
Pin 1 is marked for orientation. 



ORDERING INFORMATION 



SIMPLIFIED CONVERSION TRANSFER FUNCTIONS 



Decoder 
Characteristic 



Encoder 
Characteristic 



Part Number 


Temperature 


Accuracy 


Am6071ADM, 


-55°C to + 125T 


±1/2 step 


Am6071DM 


-55°Cto +125X 


±1 step 


Am6071ADC 


0°C to +70°C 


±1/2 step 


Am6071DC 


0°C to +70°C 


±1 step 




ANALOG 

outputi-i LIC-261 




3-40 



Am6071 

MAXIMUM RATINGS above which useful life may be impaired 



V+ Supply to V- Supply 


36V 


Operating Temperature 


Vlc Swing 


V- plus 8V to V+ 


MIL Grade 


-55°Cto+125°C 


Output Voltage Swing 


V- plus 8V to V- plus 36V 


COM'L Grade 


0°Cto+70°C 


Reference Inputs 


V- to V+ 


Storage Temperature 


-65°Cto +150°C 


Reference Input Differential Voltage 


+ 18V 


Power Dissipation Ta < 100°C 


500mW 


Reference Input Current 


1.25mA 


For Ta > 100°C derate at 


10mW/°C 


Logic Inputs 


V- plus 8V to V- plus 36V 


Lead Soldering Temperature 


300° C (60 sec) 



GUARANTEED FUNCTIONAL SPECIFICATIONS 



Resolution 


+ 128 Steps 


Monotonicity 


For both groups of 1 28 steps and over full operating temperature range 


Dynamic Range 


62dB, (20 log (| 7( 15 /l , 1)) 



ELECTRICAL CHARACTERISTICS 

These specifications apply for V+ = +15V, V- = -15V, l REF = 512(U.A,0°C s T A « +70°C, for the commercial grade, -55°C sT A s 
+ 125C, for the military grade, and for all 4 outputs unless otherwise specified. Am6071 ADM Am6071DM 



Am6071ADC Am6071DC 

Parameter Description Test Conditions Min. Typ. Max. Min. Typ. Max. Units 





Settling Time 


To within ±1/2 step at T A = 25°C 
output switched from 
!zs to Ifs 




300 


500 




300 


500 


ns 


!fS(D) 
'fS(E) 


Chord Endpoint Accuracy 


Guaranteed by output 
current error specified 
below. 






±1/2 






±1 


Step 


Step Nonlinearity 






±1/2 






±1 


Step 


Full Scale Current Deviation 
From Ideal 






±1/2 






±1 








±1/2 






±1 




AIq 


Output Current Error 


V BEF = 10.000V 

R REF+ = 19.53k 

Rref— = 20kfl 

— r nv ,t < + 1 rv 

o.uv :: VQyy ::: T IOV 

Error referred to nominal values 
in Table 1. 






±1/2 






+ 1 


Step 


'oi+j-'oi-i 


Full Scale Symmetry Error 


V REF = 10.000V 
Rr E f— = 19.53k 
R REF = 20kfl 

-5.0V s V 0U T s +18V 

Error referred to nominal values 

in Table 1 




1/40 
1/40 


1/8 
1/8 




1/20 
1/20 


1/4 
1/4 


Step 
Step 


Ien 


Encode Current 


Additional output 
Encode/Decode = 1 


3/8 


1/2 


5/8 


1/4 


1/2 


3/4 


Step 


'zs 


Zero Scale Current 


Measured at selected output 
with 000 0000 input 




1/40 


1/4 




1/20 


1/2 


Step 


AIfs 


Full Scale Drift 


Operating temperature range 




±1/20 


±1/4 




±1/10 


±1/2 


Step 


Voc 


Output Voltage Compliance 


Full scale current change 
S1/2 step 


-5.0 




+ 18 


-5.0 




+ 18 


Volts 


bis 


Disable Current 


Output leakage 

Output disabled by E/D and SB 




5.0 


50 




5.0 


50 


nA 


'fsr 


Output Current Range 







2.0 


4.2 





2.0 


4.2 


mA 


V|L 
V,H 


Logic Input Levels 


Logic "0" 


V LC = OV 


2.0 




0.8 


2.0 




0.8 


Volts 


Logic "1" 


'in 


Logic Input Current 


V m = -5.0V to +18V 






40 






40 


MA 


Vis 


Logic Input Swing 


V- = -15V 


-5.0 




+ 18 


-5.0 




+ 18 


Volts 


'b ref- 


Reference Bias Current 






-1.0 


-4.0 




-1.0 


-4.0 


MA 


di/dt 


Reference Input Slew Rate 




0.12 


0.25 




0.12 


0.25 




mA//xs 


PSSI FS+ 
PSSI FS - 


Power Supply Sensitivity 
Over Supply Range (Refer 
to Characteristic Curves) 


V+ = 4.5 to 18V, V- = -15V 

V- = -10.8 to -18V, V+ = 15V 


±1/20 
±1/10 


±1/2 
±1/2 




±1/20 
±1/10 


±1/2 
±1/2 




Step 
Step 


I- 


Power Supply Current 


V+ = +5.0 to +15V, V- = -15V 
l F S = 2.0mA 




2.7 

-6.7 


4.0 
-8.8 




2.7 
-6.7 


4.0 

-8.8 


mA 


P D 


Power Dissipation 


V- = -15V, V OU T = 
l FS = 2.0mA 


V+ = 5.0V 




114 
141 


152 
192 




114 
141 


152 
192 


mW 


V+ = +15V 



3-41 



Am6071 



ELECTRICAL CHARACTERISTICS (Cont.) 






















TABLE 1 














NOMINAL DECODER OUTPUT CURRENT LEVELS IN 








STEP 


CHORD 













1 


2 


3 


4 


5 


6 


7 






o 


.500 


16.500 


33.000 


66.000 


132.00 


264.00 


528.00 


1056.00 






1 


1.500 


17.500 


35.000 


70.000 


140.00 


280.00 


560.00 


1120.00 






2 


2.500 


18.500 


37.000 


74.000 


148.00 


296.00 


592.00 


1184.00 






3 


3 500 


19 500 




78 000 


1 56 00 


312 00 


624 00 


1248 00 






4 


4.500 


20.500 


41.000 


82.000 


164.00 


328.00 


656.00 


1312.00 






5 


5.500 


21.500 


43.000 


86.000 


172.00 


344.00 


688.00 


1376.00 






6 


6.500 


22.500 


45.000 


90.000 


180.00 


360.00 


720.00 


1440.00 






7 


7.500 


23.500 


47.000 


94.000 


188.00 


376.00 


752.00 


1504.00 






8 


8.500 


24.500 


49.000 


98.000 


196.00 


392.00 


784.00 


1 568.00 






9 


a.Duu 


ZD.DUU 


51 .000 


I VZ .UUU 


ZU4.UU 


408.00 


81 6.00 


1632.00 






10 


10.500 


26.500 


53.000 


106.000 


212.00 


424.00 


848.00 


1696.00 






11 


11.500 


27.500 


55.000 


110.000 


220.00 


440.00 


880.00 


1760.00 






12 


12.500 


28.500 


57.000 


114.000 


228.00 


456.00 


912.00 


1824.00 






13 


13.500 


29.500 


59.000 


118.000 


236.00 


472.00 


944.00 


1888.00 






14 


14.500 


30.500 


61.000 


122.000 


244.00 


488.00 


976.00 


1952.00 






15 


15.500 


31.500 


63.000 


126.000 


252.00 


504.00 


1008.00 


2016.00 






STEP 
SIZE 


1 


1 


2 


4 


8 


16 


32 


64 


































TABLE 2 










IDEAL DECODER OUTPUT VALUES EXPRESSED IN dB DOWN FROM OVERLOAD LEVEL (+ 3dBmo) 




STEP 


CHORD 









1 


2 


3 


4 


5 


6 


7 









72.11 


41.74 


35.72 


29.70 


23.68 


17.66 


11.64 


5.62 








1 


62.57 


41.23 


35.21 


29.19 


23.17 


17.15 


11.13 


5.11 






2 


58.13 


40.75 


34.73 


28.71 


22.68 


16.66 


10.64 


4.62 






3 


55.21 


40.29 


34.27 


28.25 


22.23 


16.21 


10.19 


4.17 






4 


53.03 


39.85 


33.83 


27.81 


21.79 


15.77 


9.75 


3.73 






5 


51.28 


39.44 


33.42 


27.40 


21.38 


15.36 


9.34 


3.32 






6 


49.83 


39.05 


33.03 


27.00 


20.98 


14.96 


8.94 


2.92 






7 


48.59 


38.67 


32.65 


26.63 


20.61 


14.59 


8.57 


2.54 






8 


47.50 


38.31 


32.29 


26.27 


20.24 


14.22 


8.20 


2.18 






9 


46.54 


37.96 


31.94 


25.92 


19.90 


13.88 


7.86 


1.84 






10 


45.67 


37.62 


31.60 


25.58 


19.56 


13.54 


7.52 


1.50 






11 


44.88 


37.30 


31.28 


25.26 


19.24 


13.22 


7.20 


1.18 






12 


44.15 


36.99 


30.97 


24.95 


18.93 


12.91 


6.89 


0.87 






13 


43.48 


36.69 


30.67 


24.65 


18.63 


12.61 


6.59 


0.57 






14 


42.86 


36.40 


30.38 


24.38 


18.34 


12.32 


6.30 


0.28 








42.28 


36.12 


30.10 


24.08 


18.06 


12.04 


6.02 


0.00 





























3-42 



Am6071 



THEORY OF OPERATION 

Functional Description 

The Am6071 is an 8-bit, nonlinear, digital-to-analog conver- 
ter with high impedance current outputs. The output current 
value is proportional to the product of the digital inputs and 
the input reference current. The full scale output current, l FS , 
is specified by the input binary code 111 1 1 1 1 , and is a linear 
function of the reference current, l REF . There are two operat- 
ing modes, encode and decode, which are controlled by the 
Encode/Decode, (E/D), input signal. A logic 1 applied to the 
E/D input places the Am6073 in the encode mode and current 
will flow into the Ioe(+) or 'oe(-) output, depending on the 
state of the Sign Bit (SB) input. A logic at the E/D input 
places the Am6073 in the decode mode. 

The transfer characteristic is a piece-wise linear approxima- 
tion to the CCITT A-87.6 logarithmic law which can be written 
as follows: 

Y = 0.18 (1 + In (A |X| )) sgn (X), 1/A « |X| s 1 

Y = 0.18 (AlXl)sgn (X), =s IXl « 1/A 

where: X = analog signal level normalized to unity 
(encoder input or decoder output) 

Y = digital signal level normalized to unity 
(encoder output or decoder input) 

A = 87.6 

The current flows from the external circuit into one offour 
possible analog outputs determined by the SB and E/D in- 
puts. The output current transfer function can be represented 
by a total of 16 segments or chords addressable through the 
SB input and three chord select bits. The two chords closest 
to the origin of the transfer function, chord and chord 1, are 
made colinear and contiguous. The beginning of chord 0, 
specified by the input binary code 000 0000, is offset by 
+0.5/xA. Each chord can be further divided into 16 steps, all 
of the same size. The step size changes from one chord to 
another, with the smallest step of 1 .0/j.A found in the first two 
chords near zero output current, and the largest step of 64/iA 
found in the last chord near full scale output current. This 
nonlinear feature provides exceptional accuracy for small 
signal levels. The accuracy for signal amplitudes corres- 



ponding to chords and 1 is very close to that of an 1 1-bit 
linear, binary D/A converter. The ratio (in dB) between the 
chord endpoint current, (Step 15), and the current which 
corresponds to the preceding step, (Step 14), is maintained 
at about 0.3dB over the entire dynamic range, with the excep- 
tion of chord 0. The difference between the ratios of full scale 
current to chord endpoint currents of adjacent chords is 
similarly maintained at 6dB over the entire dynamic range. 
Resulting signal-to-quantizing distortions due to non- 
uniform quantizing levels maintain an acceptably low value 
over a 40dB range of input speech signals. Note thatthe 62dB 
output dynamic range for the Am6071 is very close to the 
dynamic range of a sign plus 11 -bit linear, binary D/A conver- 
ter. 

In order to achieve a smoother transition between adjacent 
chords, the step size between these chord end points is equal 
to 1 .5 times the step size of the lower chord. Note that this 
does not apply to chord and chord 1 where adjacent end 
points differ by only one step, because these two chords are 
colinear and have the same step sizes. Monotonic operation 
is guaranteed by the internal device design over the entire 
output dynamic range by specifying and maintaining the 
chord end points and step size deviations within the allow- 
able limits. 

Operating Modes 

The basic converter function is conversion of digital input 
data into a corresponding analog current signal, i.e., the 
basic function is digital-to-analog decoding. The basic de- 
coder connection for a sign plus 7-bit input configuration is 
shown in Figure 1. The corresponding dynamic range is 
62dB, and input-output characteristics conform to the stan- 
dard decoder transfer function with output current values 
specified in Table 1. The E/D input enables switching be- 
tween the encode, Ioe<+) or 'oei-i- and tne decode, Iod(+) or 
'oD(-)- outputs. A typical encode/decode test circuit is shown 
in Figure 2. This circuit is used for output current measure- 
ments. When the E/D input is high, (a logic 1), the converter 
will assume the encode operating mode and the output cur- 
rent will flow into one of the I e outputs (as determined by 
the SB input). When operating in the encode mode as shown 



DIGITAL INPUTS 




— -15V 



!rEF " Vref/ r REF 

IDEAL VALUES: l REF = 512mA, l FS = 2016mA 





E/D 


SB 


B1 


B 2 


B 3 


B 4 


B 5 


b 6 


e 7 


EO 


POSITIVE FULL SCALE 







1 




I 


1 


1 


i 


i 


5.040 V 


(+] ZERO SCALE +1 STEP 













a 













0.004V 


l*l ZERO SCALE 


| 1 








□ 














0.0012V 


i-l ZERO SCALE 

















□ 











0012V 


(-(ZERO SCALE +1 STEP 


























1 


-0.004 V 


NEGATIVE FULL SCALE 








1 


1 


1 


1 


1 


1 


1 


-5.040V 



Figure 1. Detailed Decoder Connections. 




R 1 = R 2 = R 3 " R 4 " 2.5 kfl ±0.1% 

LINE SELECTION TABLE 



T EST 






OUTPUT 


GROUP 


E/D 


SB 


MEASUREMENT 


1 






"OE M 


(Eoi/RiI 


2 







lOE(-) 


!E 1/R2> 


3 





1 


lOD l + > 


(E02/R3} 


4 








i d(-> 


IE02/R4I 



Figure 2. Output Current DC Test Circuit. 



3-43 



Am6071 



in Figure 3, an offset current equal to a half step in each chord 
is required to obtain the correct encoder transfer characteris- 
tic. Since the size of this Step varies from one chord to 
another, it cannot easily be added externally. As indicated in 
the block diagram this required half step of encode current, 
l EN , is automatically added to the I e output through the 
internal chip design. This additional current will, for exam- 
ple, make the ideal full scale current in the encode mode 
larger than the same current in the decode mode by 32/j.A. 
Similarly, the current levels in the first chord near the origin 
will be offset by 0.5/j.A, which will bring the ideal encode 
current value for step on chord to 1 .0/xA with respect to 
the corresponding decode current value of 0.5/xA. This addi- 
tional encode half step of current can be used for extension 
of the output dynamic range from 62dB to 66dB, when the 
converter is performing only the decode function. The cor- 
responding decoder connection utilizes the E/D input as a 
ninth digital input and has the outputs Iod(+) a nd Ioe(+) a nd 
the outputs Iod(-) and bE(-) tied together, respectively. 
When encoding or compression of an analog signal is re- 
quired, the Am6071 can be used together with a Successive 
Approximation Register (SAR), comparator, and additional 
SSI logic elements to perform the AID data conversion, as 
shown in Figure 3. The encoder transfer function, shown on 
page 1 , characterizes this AD converter system. The first task 
of this system is to determine the polarity of the incoming 
analog signal and to generate a corr esponding SB input 
value. When the proper START, (S), and CONVERSION COM- 
PLETE, (CC), signal levels are set, the first clock pulse sets 
the MSB output of the SAR, Am2502, to a logic and sets all 
other parallel digital outputs to logic 1 levels. At the same 
time, the flip-flop is triggered, and its output provides the E/D 
input with a logic level. No current flows into the I e out- 
puts. This disconnects the converter from the comparator 
inputs, and the incoming analog signal can be compared 
with the ground applied to the opposite comparator input. 
The resulting comparator output is fed to the Am2502 serial 
data input, D, through an exclusive-or gate. At the same time, 
the second input to the same exclusive-or gate is held at a 
logic level by the additional successive approximation 
logic shown in Figure 3. This exclusive-or gate inverts the 
comparator's outputs whenever a negative signal polarity is 
detected. This maintains the proper output current coding, 
i.e., all ones for full scale and all zeros for zero scale. 



The second clock pulse changes the E/D input back to a logic 
1 level because the CC signal changed. It also clocks the D 
input signal of the Am2502 to its MSB output, and transfers it 
to the SB input of the Am6071. Depending upon the SB input 
level, current will flow into the I e(+) or I ei-) output of the 
Am6071. 

Nine clock pulses are required to obtain a digital binary 
representation of the incoming analog signal at the eight 
Am2502 digital outputs. The resulting Am6071 analog out- 
put signal is compared with the analog input signal after 
each of the nine successive clock pulses. The analog signal 
should not be allowed to change its value during the data 
conversion time. In high speed systems, fast changes of the 
analog signals at the AID system input are usually prevented 
by using sample and hold circuitry. 



Additional Considerations and Recommendations 

In Figure 1, an optional operational amplifier converts the 
Am6071 output current to a bipolar voltage output. When the 
SB input is a logic 1, sink current appears at the amplifier's 
negative input, and the amplifier acts as a current to voltage 
converter, yielding a positive voltage output. With the SB 
value at a logic 0, sink current appears at the amplifier's 
positive input. The amplifier behaves as a voltage follower, 
and the true current outputs will swing below ground with 
essentially no change in output current. The SB input steers 
current into the appropriate (+) or (-) output of the Am6071. 
The resulting operational amplifier's output in Figure 1 
should ideally be symmetrical with resistors Rl and R2 
matched. 

In Figure 2, two operational amplifiers measure the currents 
of each of the four Am6071 analog outputs. Resistor toler- 
ances of 0.1% give 0.1% output measurement error (approx- 
imately 2/j.A at full scale). The input offset currents of the A1 
and A2 devices also increase output measurement error and 
this error is most significant near zero scale. The Am101A 
and 308 devices, for example, may be used for A1 and A2 
since their maximum offset currents, which would add di- 
rectly to the measurement error, are only 10nA and 1 
respectively. The input offset voltages of the A1 and 
devices, with output resistor values of 2.5kfl, also contribute 
to the output measurement error by a factor of 400nA for 



ANALOG INPUT 



(GROUNDED FOR 
SINGLE-ENDED | 
INPUTS) I 



2 Ski! > > 2 5kfi 




-1SV *isv 

Figure 3. Detailed Encoder Connections. 



3-44 



Am6071 



every mV of offset. Therefore, to minimize error, the offset 
voltages of A1 and A2 should be nulled. 

The recommended operating range for the reference current 
l REF is from 0.1mA to 1.0mA. The full scale output current, 
l FS , is a linear function of the reference current, and may be 
calculated from the equation l FS = 3.94 I 

ref- This tight re- 
lationship between l REF and l FS alleviates the requirement 
for trimming the l REF current if the R REF resistor values 
are within ±1% of the calculated value. Lower values of 
l REF will reduce the negative power supply current, (I-), 
and will increase the reference amplifier negative com- 
mon mode input voltage range. 

The ideal value for the reference current l REF = V REF /R REF is 
512^A. The corresponding ideal full scale decode and en- 
code current values are 2016/iA and 2048ju.A, respectively. A 
percentage change from the ideal l REF value produced by 
changes in V REF or R REF values produces the same percen- 
tage change in decode and encode output current values. 
The positive voltage supply, V+, may be used, with certain 
precautions, for the positive reference voltage V REF . In this 
case, the reference resistor R REF(+ | should be split into two 
resistors and their junction bypassed to ground with a 
capacitor of 0.01/u.F. The total resistor value should provide 
the reference current l REF = 512/j.A. The resistor R REF( _j 
value should be approximately equal to the R REF(+ ) value in 
order to compensate for the errors caused by the reference 
amplifier's input offset current. 

An alternative to the positive reference voltage applications 
shown in Figures 1, 2 and 3 is the application of a negative 
voltage to the V R( -j terminal through the resistor R REF( _) 
with the R REF(+) resistor tied to ground. The advantage of 
this arrangement is the presence of very high impedance at 
the V R( _) terminal while the reference current flows from 
ground through R REF(+) into the V R(+) terminal. 

The Am6071 has a wide output voltage compliance suitable 
for driving a variety of loads. With l REF = 512aiA and V- = 
-15V, positive voltage compliance is +18V and negative 



voltage compliance is -5.0V. For other values of I ref and 
V-, the negative voltage compliance, V c(-). may be calcu- 
lated as follows: 

Voci-] = (V-) + 2(l REF .1.55kn) + 8.4V, 
where 1 .55kft and 8.4V are equivalent worst case values for 
the Am6071. 

The following table contains V c<-) values for some specific 
V-, I reF' and l FS values. 

Negative Output Voltage Compliance V QC (_) 





'ref"fs> 


V- 


256 M A 
(1mA) 


512ju.A 
(2mA) 


1024 M A 
(4mA) 


-12V 


-2.8V 


-2.0V 


-0.4V 


-15V 


-5.8V 


-5.0V 


-3.4V 


-18V 


-8.8V 


-8.0V 


-6.4V 



The V L c input can accommodate various logic input switch- 
ing threshold voltages allowing the Am6071 to interface with 
various logic families. This input should be placed at a poten- 
tial which is 1.4V below the desired logic input switching 
threshold. Two external discrete circuits which provide this 
function for non-TTL driven inputs are shown in Figure 4. For 
TTL-driven logic inputs, the V L c input should be grounded. If 
negative voltages are applied at the digital logic inputs, they 
must have a value which is more positive than the sum of the 
chosen V- value and +10V. 

With a V- value chosen between -15V and -11V, the 
V oc( _), the input reference common mode voltage range, 
and the logic input negative voltage range are reduced by an 
amount equivalent to the difference between -15V and the 
V- value chosen. 

With a V+ value chosen between +5V and +15V, the refer- 
ence amplifier common mode positive voltage range and the 
V LC input values are reduced by an amount equivalent to the 
difference between +15V and the V+ value chosen. 



ECL 



CMOS, HTL, NMOS 




(See Notes 2 and 3) 

Figure 4. Interfacing Circuits for ECL, CMOS, HTL, 
and NMOS Logic Inputs. 



DIGITAL INPUTS 




♦10 V +5.0 V 



**7 65 Bg B 4 Bg B 2 6, SB E/D 1q£ (+) 

*R(+> 




INPUT CODE 
<E/D, SB, B 1 B7) 


OUTPUT VOLTAGE (V) 


"A" 


"B" 


"C" 


DIFF 


10 111 1111 
10 110 1111 
10 000 0000 




+5.00 
+10.00 


N/A 


N/A 


N/A 


01 111 1111 




-5.00 


+5.00 


-10.00 


oi no mi 




+0.00 


+5.00 


-5.00 


01 000 0000 




+5.00 


+ 5.00 





00 000 0000 


N/A 


+ 5.00 


+6.00 





00 110 1111 




+5.00 


+0.00 


+5.00 


00 111 1111 




+5.00 


-5.00 


+10.00 



Figure 5. Resistive Output Connections. 



3-45 



Am6071 



ADDITIONAL DECODE OUTPUT CURRENT TABLES 

Table 3 



Normalized Decoder Output (Sign Bit Excluded) 









CHORD (C) 











1 


2 


3 


4 


5 


6 


7 


STEP (S) 


000 


001 


010 


011 


100 


101 


110 


111 




1 

2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 


0000 
0001 
0010 
0011 
0100 
0101 
0110 
0111 
1000 
1001 
1010 
1011 
1100 
1101 
1110 

1111 


1 

3 
5 
7 
9 
11 
13 
15 
17 
19 
21 
23 
25 
27 
29 
31 


33 
35 
37 
39 
41 
43 
45 
47 
49 
51 
53 
55 
57 
59 
61 
63 


66 
70 
74 
78 
82 
86 
90 
94 
98 
102 
106 
110 
114 
118 
122 
126 


1 T5 

140 
148 
156 
164 
172 
180 
188 
196 
204 
212 
220 
228 
236 
244 
252 


264 
280 
296 
312 
328 
344 
360 
376 
392 
408 
424 
440 
456 
462 
488 
504 


528 
560 
592 
624 
656 
688 
720 
752 
784 
816 
848 
880 
912 
944 
976 
1008 


1 056 
1120 
1184 
1248 
1312 
1376 
1440 
1504 
1568 
1632 
1696 
1760 
1824 
1888 
1952 
2016 


2112 
2240 
2368 
2496 
2624 
2752 
2880 
3008 
3136 
3264 
3392 
3520 
3648 
3776 
3904 
4032 


STEP SIZE 


2 


2 


4 


8 


16 


32 


64 


128 



The normalized decode current, dc,s)> where C is chord number and S is step number, is calculated 
using: l C s = 2 °( s + 16.5) for C s 1, and l C)S = 2S + 1 forC = 0. The ideal decode current, (I d). in is 
calculated using: l OD = (lc,s' | 7,i5(norm.))*lFsO x A), where l c , s is the corresponding normalized current. 



Table 4 

Normalized Encoder Output (Sign Bit Excluded) 



STEP (S) 


CHORD (C) 





1 


2 


3 


4 


5 


6 


7 


000 


001 


010 


011 


100 


101 


110 


111 





0000 


2 


34 


68 


136 


272 


544 


1088 


2176 


1 


0001 


4 


36 


72 


144 


288 


576 


1152 


2304 


2 


0010 


6 


38 


76 


152 


304 


608 


1216 


2432 


3 


0011 


8 


40 


80 


160 


320 


640 


1280 


2560 


4 


0100 


10 


42 


84 


168 


336 


672 


1344 


2688 


5 


0101 


12 


44 


88 


176 


352 


704 


1408 


2816 


6 


0110 


14 


46 


92 


184 


368 


736 


1472 


2944 


7 


0111 


16 


48 


96 


192 


384 


768 


1536 


3072 


8 


1000 


18 


50 


100 


200 


400 


800 


1600 


3200 


9 


1001 


20 


52 


104 


208 


416 


832 


1664 


3328 


10 


1010 


22 


54 


108 


216 


432 


864 


1728 


3456 


11 


1011 


24 


56 


112 


224 


448 


896 


1792 


3584 


12 


1100 


26 


58 


116 


232 


464 


928 


1856 


3712 


13 


1101 


28 


60 


120 


240 


480 


960 


1920 


3840 


14 


1110 


30 


62 


124 


248 


496 


992 


1984 


3968 


15 


1111 


32 


64 


128 


256 


512 


1024 


2048 


4096 


STEP SIZE 


2 


2 


4 


8 


16 


32 


64 


128 



3-46 





Am6071 




ADDITIONAL DECODE OUTPUT CURRENT TABLES (Cont ) 



Table 5 
Decoder Step Size Summary 











Step Size 


Step Size as 


Resolution 




Step Size 


Step Size 


Step Size 


in dB at 


a % of Reading 


& Accuracy 




Normalized 


in fj.fi, with 


as a % of 


Chord 


at Chord 


of Equivalent 


Chord 


to Full Scale 


2016/^A F. S. 


Full Scale 


Endpoints 


Endpoints 


Binary DAC 





2 


1.0 


0.05% 


0.58 


6.45% 


Sign + 11 Bits 


1 


2 


1.0 


0.05% 


0.28 


3.17% 


Sign + 11 Bits 


2 


4 


2.0 


0.1% 


0.28 


3.17% 


Sign + 10 Bits 


3 


8 


4.0 


0.2% 


0.28 


3.17% 


Sign + 9 Bits 


4 


16 


8.0 


0.4% 


0.28 


3.17% 


Sign + 8 Bits 


5 


32 


16.0 


0.8% 


0.28 


3.17% 


Sign + 7 Bits 


6 


64 


32.0 


1.6% 


0.28 


3.17% 


Sign + 6 Bits 


7 


128 


64.0 


3.2% 


0.28 


3.17% 


Sign + 5 Bits 



Table 6 

Decoder Chord Size Summary 



Chord 


Chord Endpoints 
Normalized 
to Full Scale 


Chord Endpoints 
in /jlA with 
2016/xA F. S. 


Chord Endpoints 
as a % 
of Full Scale 


Chord Endpoints 

in dB Down 
from Full Scale 





31 


15.5 


0.77% 


-42.28 


1 


63 


31.5 


1.56% 


-36.12 


2 


126 


63.0 


3.13% 


-30.10 


3 


252 


126.0 


6.25% 


-24.08 


4 


504 


252.0 


12.5% 


-18.06 


5 


1008 


504.0 


25.0% 


-12.04 


6 


2016 


1008.0 


50.0% 


-6.02 


7 


4032 


2016.0 


100% 






3-47 



Am6071 



BASIC CIRCUIT CONNECTIONS 



+10V RANGE ENCODER/DECODER 
CONNECTIONS 



DIGITAL INPUTS 




COMPLIANCE EXTENSION 
USING AC COUPLED OUTPUT 




DIGITAL INPUTS 



■l eU«li|g[t"^ " 




113 M8 fl 

-12V C"12V — 



IDEAL VALUES: 

'ref = 512^ 
l FS = 2016/iA 



LOW INPUT IMPEDANCE CONNECTION 



HIGH INPUT IMPEDANCE CONNECTION 



DIGITAL INPUTS 



DIGITAL INPUTS 




A -15V A+15V -± 




O -1SV O *15V •= 



!REF = v in/ r in + v ref/ r ref 

'FS ~ 4 • Iref 



•ref ■ ( V REF - V|N>/RREF 
lFS " 4 • 'REF 



LOGARITHMIC DIGITAL GAIN CONTROL 
(Notes 4 & 5) 



REFERENCE AMPLIFIER DYNAMIC TEST CIRCUIT 



ATTENUATION 
■ 6d8/CHORD CHANNEL 
* WB/STEP SELECT 




FREQUENCY 
RESPONSE 
TEST 



9 Vref ? 
I MOV I 



— 6 -15V 




RF VOLTMETER 



Notes: 4. Low distortion outputs are 

5. Up to 4 channels of output may 



over a 72dB range, 
be selected by E/D and SB logic inputs. 



3-48 



Am6071 



TYPICAL PERFORMANCE CURVES 



Reference Amplifier 
Total Harmonic Distortion 
Versus Frequency (80kHz Filter) 
(Notes 6, 7, 8) 



0.2 
0.1 
0.05 



: 0.005 

; 0.002 























4 












































See Note u 








































































\ 






































































> 




LARGE SIGNAL 










INPUT +5V PEAK 
(50% MODULATION 























100 1.0k 10k 
FREQUENCY - Hz 



Reference Amplifier 
Input Frequency Response 













































































>MA 


LLSIGr 


A 


L 








\ 






100mV PEAK 
(1% MODULATION I 


\ 














































\ 






LARGE SIGNAL/ 




\ 






L 


[SLEW HA 1 b L1MI 1 fcU) 
5V PEAK 










(50% MODULATION 

Mil 1 Mil I Mil 










II 



< 10k 100k 1M 
FREQUENCY - Hz 



Reference Amplifier 
Input Common-Mode Range 
(Note 9) 



T A" T MIN to T MAX 
























V- 


■ -i 


>v 






V 


+■ = + 


15V 










EF " 


D.In 


a] 










































|R 


F " 


3.25n 




-f 














-o - 

I 











REFERENCE COMMON-MODE VOLTAGE 
ATV REF PIN-V 



Power Supply Currents 
Versus Power Supply Voltages 













1 I 1 
1 vs. V- 


















































































































A 

.. 


L B 


ITS 


'HI 
S " 
. 


□ H' 
2 
1 


OR "LOW 

TlA 







2.0 4.0 6.0 8.0 10 12 14 16 18 20 
POSITIVE OR NEGATIVE POWER SUPPLY - V 



Power Supply Currents 
Versus Temperature 





















1 














































= 2 


Qui 


ft 




























1 








































LL 
V 


JITS 

► » -i 


"H 
15\ 


GH 
, V 


'Of 


"L 
-15 


OW 







1.0 


-75 -50 50 100 
TEMPERATURE — °C 



Output Current Versus 
Output Voltage 
(Output Voltage Compliance) 











1 1 1 






1 




'REF = 1-OmA 


















T A" T MIN to 'MAX 










V— 




IV 


















if 


EF = 0.5mA 












































-f 




















- - 











-14 -10 -6 -2 2 6 10 14 18 
OUTPUT VOLTAGE - V 



Bit Transfer Characteristics 
(Note 10) 



0.35 
0.30 
0.25 
020 
0.15 
0.10 
0.06 




I I I I I I 
IrEF = 0.5mA- 



15V 
V 12V 



0.055 
0.023 



4 8 12 16 
LOGIC INPUT VOLTAGE - V 



Logic Input Current 
Versus Input Voltage 
and Logic Input Range 
(Note 11) 



_ 20 



MM 

l REF - 0.5mA 
V- = -15V 

v LC -ov 



IT 



-8 -4 4 8 12 1 
LOGIC INPUT VOLTAGE - V 



Output Full Scale Current 
Versus Reference Input Current 




0.5 1.0 

REFERENCE CURRENT. I REF - mA 



Notes: 6. THD is nearly independent of the logic input code. 

7. Similar results are obtained for a high input impedance connection using Vci(-) as an input. 

8. Increased distortion above 50kHz is due to a slew rate limiting effect which determines the large signal bandwidth. For an input of ±2.5V peak (25* 
modulation), the bandwidth is 100kHz. 

9. Positive common mode range Is always (V+) -1.5V. 

10. All bits are fully switched with less than a half step error at switching points which are guaranteed to lie between 0.8V and 2.0V over the operating 
temperature range. 

1 1 . The logic input voltage range is independent of the positive power supply and logic inputs may swing above the supply. 



3-49 



_ ^.uswoiif 0UILCU IUI dp* 

plications requiring a wide dynamic range. 

Systems requiring fine control resulting in a constant rate of 
change or set point controls are economically achieved 
using these devices. 

Instrumentation, Control and ^-Processor based applica- 
tions include: 

Digital data recording 

PCM telemetry systems 

Servo systems 

Function generation 

Data acquisition systems 



leiecommunications applications include: 
PCM Codec telephone systems 
Intercom systems 

Military voice communication systems 
Radar systems 
Voice Encryption 



Audio Applications: 
Recording 

Multiplexing of analog signals 
Voice synthesis 



Other companding converters offered by Advanced Micro Devices: 



If particular interest lies in a companding D/A converter 
operating to the D3 compandor tracking specification and 
meeting the Bell System /_,-255 companding law, see the 
Am6072 data sheet. 

For a CCITT unit having an A-law characteristic see the 
Am6073 data sheet. 

Haw applications other than telecommunications systems 
are described in the Am6070 data sheet. 





SERIAL DATA TRANSCEIVING CONVERTER 
(1/2 OF SYSTEM SHOWN) 



Am6071 



TRANSMIT INPUT 
■5V ANALOG IN 

9 



TIME SHARED 
BI-DIRECTIONAL 
SERIAL DATA 




RECEIVE OUTPUT 



Notes: 

1. Complementary send/receive commands are required for the 
two end s, 

2. START must be held low for one clock cycle to begin a send 
or receive cycle. 



13| TbI loj 

ivi .15V 6 4r 



3. The SAR is used as a serial-in/parallel out register in the re- 
ceive mode. 

4. CLOCK and START may be connected in parallel at both ends. 

5. Conversion is completed in 9 clock cycles. 

6. Receive output is available for one full clock cycle. 



Metallization and Pad Layout 




80 X 114 Mils 



3-51 



Am6072 

Companding D-to-A Converter for PCM Communication Systems 

PRELIMINARY INFORMATION 



Distinctive Characteristics 

• Tested to D3 compandor tracking specification 

Absolute accuracy specified - includes all errors over 
temperature range 
Settling time 300ns typical 
Ideal for multiplexed PCM systems 
Output dynamic range of 72 dB 



• Improved pin-for-pin replacement for DAC-86 

• Microprocessor controlled operations 

• Multiplying operation 

• Negligible output noise 

• Monotonicity guaranteed over entire dynamic range 

• Wide output voltage compliance 

• Low power consumption 



GENERAL DESCRIPTION 



The Am6072 is a monolithic 8-bit, companding digital-to- 
analog (D/A) data converter with true current outputs and 
large output voltage compliance for fast driving a variety of 
loads. The transfer function of the Am6072 complies with the 
Bell System u-255 companding law, Y = 0.18 In (1 + /jx>, and 
consists of 15 linear segments or chords. A particular chord is 
identified with the sign bit input, (SB), and three chord select 
input bits. Each chord contains 16 uniformly spaced linear 
steps which are determined by four step select input bits. The 
resulting dynamic range achieved with this 8-bit format is 
72dB. Accuracy and monoticity are assured by the internal 
circuit design and are guaranteed over the full temperature 



range. The Am6072 is tested to the Bell D3 channel bank com- 
pandor tracking specification for pulse code modulation 
(PCM) transmission systems. The application of the Am6072 
in communication systems provides an increased signal-to- 
noise ratio, reduces system signal distortion, and stimulates 
wider usage of computerized channel switching. Other appli- 
cation areas include digital audio recording, voice synthesis, 
and secure communications. When used in PCM communica- 
tion systems, the Am6072 functions as a complete PCM de- 
coder with additional encoding capabilities which make it ideal 
for implementation in CODEC circuits. 



FUNCTIONAL BLOCK DIAGRAM 



CHORD BITS 



^ a 5 s 6 

9 9 9 9 



CHORO AND 
PEDESTAL 
SOURCES 



CONNECTION DIAGRAM 
Am6072 



ENCODE/DECODE SELECT: 1 

SIGN BIT INPUT: 1 = POSITIVE 2 ^ 

MOST SIGNIFICANT CHORD BIT INPUT 3 Q 

SECOND CHORD BIT INPUT 4 

LEAST SIGNIFICANT CHORD BIT INPUT 5 Q 

MOST SIGNIFICANT STEP BIT INPUT 6^ 

SECOND STEP BIT INPUT 7 Q 

THIRD STEP BIT INPUT B 

LEAST SIGNIFICANT STEP BIT INPUT 9 Q 



E/D*^ V 



'OD(-) 
'OD(+J 
'OEI-I 
'OE(+l 
V- 
V R(-I 
V RM 



3 '» 



POSITIVE POWER SUPPLY 
DECODER OUT: E/D SB " 00 
DECODER OUT: E/D SB - 01 
ENCODER OUT: E/D SB -10 
ENCODER OUT: E/D SB - 11 
NEGATIVE POWER SUPPLY 
NEGATIVE REFERENCE INPUT 
POSITIVE REFERENCE INPUT 
THRESHOLD CONTROL 



Top View 
Pin 1 is marked for orientation. 



ORDERING INFORMATION 



ED CONVERSION TRANSFER FUNCTIONS 



Part Number 


Temperature 


Accuracy 


T.6072DM 


-55°Cto +125°C 


Conforms to D3 Spec. 


C S072DC 


0°C to +70° C 


Conforms to D3 Spec. 



Decoder 
Characteristic 



Encoder 
Characteristic 




ipH— I r 



Am6072 

MAXIMUM RATINGS above which useful life may be impaired 



V+ Supply to V- Supply 


36V 


Operating Temperature 


V|_C Swing 


V— plus 8V to v+ 


MIL Grade 


—55 C to +125 C 


Output Voltage Swing 


\/ nliir QW *n \f nine *3fi\/ 

V— piUS OV TO V— piUS ODV 


COWL Grade 


0°Cto+70°C 


Reference Inputs 


V- to V+ 


Storage Temperature 


-65°Cto +150°C 


Reference Input Differential Voltage 


±18V 


Power Dissipation T/\ < 100°C 


500mW 


Reference Input Current 


1.25mA 


For Ta> 100°C derate at 


10mW/°C 


Logic Inputs 


V-plus 8V to V- plus 36V 


Lead Soldering Temperature 


300° C (60 sec) 



GUARANTEED FUNCTIONAL SPECIFICATIONS 



Resokmon 


±128 Steps 


Monotonicity 


For both groups of 128 steps and over full operating temperature range 


Dynamic Range 


72 dB, (20 log (l 7j i 5 /t , 1 }) 



ELECTRICAL CHARACTERISTICS (Note 1) 

These specifications apply for V+ = +15V, V- = -15V, Iref = 528/iA, 0°C<Ta <+70°C, forthe commercial grade, -55°C<Ta 
< +1 25°C, for the military grade, and for all 4 outputs unless otherwise specified. 

Parameter Description Test Conditions Min. Typ. Max. Unit 



<s 


Settling Time 


To within +1/2 step at T^ = 25° C, 
Output switched from |£S to Ips 




300 


500 


ns 




Chord Endpoint Accuracy 


V REF = +1 0,000V 
R RE F+ = 18.94kn 
RrEF- " 20kI2 
-5V < VOUT < +18v 


See Table 1 for absolute accuracy 
limits which cover all errors related 
to the transfer characteristic. 




Step Nonlinearity 


'EN 


Encode Current 


IFSID) 
l FS (EI 


Full Scale Current Deviation from Ideal 


•o<+)— "o'-> 


Full Scale Current Symmetry Error 


izs 


Zero Scale Current 




Full Scale Current Drift 


voc 


Output Voltage Compliance 


Output within limits specified by Table 1 


-5 




+18 


Volts 


Idis 


Disable Current 


Leakage of output disabled by E/D or SB 




5.0 


50 


nA 


Ifsr 


Output Current Range 







2.0 


4.2 


mA 


V|L 


Logic Input 
Levels 


Logic "0" 


v LC = OV 






0.8 


Volts 


V| H 


Logic "1" 


2.0 






Volts 


l|N 


Logic Input Current 


V| N = -5V to+18V 






40 


MA 


V| S 


Logic Input Swing 


V- = -15V 


-5 




+18 


Volts 


'BREF- 


Reference Bias Current 






-1.0 


^t.O 


HA 


di/dt 


Reference Input Slew Rate 




0.12 


0.25 




mA/MS 


PSSI FS+ 
PSSI FS _ 


Power Supply Sensitivity Over Supply Range 
(Refer to Characteristic Curves} 


V+ - +4.5 to +18V, V- = -1 5V 




0.005 


0.1 


dB 


V- = -10.8V to -18V, V+ s +1 5V 




0.01 


0.1 


1+ 


Power Supply Current 


V+ = +5V to +15V, V- = -15V, 
Ips " 2.0mA 




2.7 


4.0 


mA 




-6.7 


-8.8 


PD 


Power Dissipation 


V- = -15V, V UT = OV 
Ips = 2.0mA 


V+ = +5V 




114 


152 


mW 


V+ = +15V 




141 


192 



Note 1 . In a companding DAC the term LSB is not used because the step size within each chord is different. For example, in the first chord around zero (Cq) 
the step size is 0.5^A, while in the last chord near full scale (C7) the step size is 64/iA. 



3-53 



Am6072 



ELECTRICAL CHARACTERISTICS (Cont.) 
















TABLE 1 

ABSOLUTE DECODER OUTPUT CURRENT LEVELS IN uA 








STEP 


CHORD NO. 






NO. 





1 


2 


3 

















-.250 
.000 
.250 


7.789 
8.250 
8.739 


24.048 
24.750 
25.473 


56.112 
57.750 
59.436 


120.24 
123.75 
127.36 


248.49 
255.75 
263.22 


505.00 
519.75 
534.93 


1018.02 
1047.75 
1078.34 






1 


.250 
.500 
.750 


8.733 
9.250 
9.798 


25.991 
26.750 
27.531 


59.998 
61.750 
63.553 


128.01 

1 31 .75 
135.60 


264.04 
271.75 
279.69 


536 10 
551 .75 
567.86 


1080.21 
1111.75 
1144.21 






2 


.750 
1.000 
1.250 


9.677 
10.250 
10.857 


27.934 
28.750 
29.590 


63.885 
65.750 
67.670 


135.79 
139.75 
143.83 


279.59 
287,75 
296.1 5 


567.19 
583.75 
600.80 


1142.39 
1175.75 
1210.08 






3 


1.250 
1.500 
1 .750 


10.621 
1 1 .250 
11.917 


29.878 
30.750 
31 .648 


67.771 
69.750 
71.787 


143.56 
147.75 
152.06 


295.13 
303.75 
312.62 


598.28 
615.75 
633.73 


1204.58 
1239.75 
1275.95 






4 


1 .750 
2.000 
2.2 50 


1 1 .565 
12.250 
12.976 


31.821 
32.750 
33.706 


71 .658 
73.750 
75.904 


1 51 .33 
155.75 
160.30 


310.68 
319.75 
329.09 


629.37 
647.75 
666.66 


1266.75 
1303.75 
1341.82 






5 


2.250 
2.500 
2.750 


12.509 
1 3.250 
14.035 


33.764 
34.750 
35.765 


75.544 
77.750 
80.020 


159.10 
163.75 
168.53 


326.22 
335.75 
345.55 


660.46 
679.75 
699.60 


1328.94 
1367.75 
1407.69 






6 


2.750 
3.000 
3.250 


13.453 
14.250 
15.094 


35.707 
36.750 
37.823 


79.431 
84.137 


166.88 
176.77 


341.77 
362.02 


691.56 
732.53 


1391.13 
1473.56 






7 


3.250 
3.750 


14.397 
16.154 


37.651 
39.882 


83.317 
88.254 


174.65 
185.00 


357.32 
378.49 


722.65 
765.47 


1453.31 

1539.4:.; 






8 


3.750 
4.250 


15.341 
17.213 


39.594 
4 l .940 


87.204 
92.371 


182.42 
193.23 


372.86 
394.96 


753.74 
798.40 


1515.50 
1605.30 






9 


4 248 
4.767 


16.285 
18.272 


41.537 
43.998 


91 .090 
96.488 


190.20 
201 .47 


388.41 
411.42 


784.83 
831.34 


1577.68 
1671.16 






10 


4.720 
5.000 
5.296 


17.229 
18.250 
19.331 


43.480 
44.750 

46.057 


94.977 
97.750 
100.604 


197.97 
203.75 
209.70 


40355 
415.75 
427.89 


815.92 
839.75 
864.27 


1639.87 
1687.75 
1737.03 






11 


5.192 
5.500 
5,826 


18.173 
19.250 
19.812 


45.424 
46.750 
48.115 


98.863 
101.750 
104.721 


205.74 
211.75 
21 /.93 


419.50 
431 .75 

444.36 


847.02 
871.75 
897.21 


1702.05 
1751.75 
1802.90 






12 


5.664 
6.000 
6.356 


19.675 
20.250 
20.841 


47.367 
48.750 

50.174 


102.750 
105.750 
108.838 


213.52 
219.75 
226.1 7 


435.05 
447.75 
460.82 


878.11 
903.75 
930.14 


1 764.23 
1815.75 
1868.77 






13 


6.136 
6.500 
6.885 


20.647 
21.250 
21.871 


49.310 
50.750 
52.232 


1 06.636 
109.750 
112.955 


221 .29 
227.75 
234.40 


450.59 
463.75 
477.29 


909.20 
935.75 
963.07 


1826.42 
1879.75 
1934.64 






14 


6.608 
7,000 
7.415 


21.619 
22.250 
22.900 


51.253 
52.750 
54.290 


110.523 
113.750 
117.072 


229.06 
235.75 
242.63 


466.14 
479.75 

4 93.713 


940.29 
967.75 
996.01 


1888.60 
1943.75 
2000.51 






15 


7.080 
7.500 
7.944 


22.590 
23.250 
23.929 


53.197 
54.750 
56.349 


1 14.409 
117.750 
121.188 


236.83 
243.75 
250.87 


48 1 .68 
495.75 

510.23 


971.39 
999.75 
1 028.94 


1950.79 
2007.75 
2066.38 






STEP 
SIZE 


.5 


1 


2 


4 


8 


16 


32 


64 




Minimum, ideal and maximum values are specified for each step. The minimum and maximum values are 
specified to comply with the Bell D3 compandor tracking requirements. All four outputs are guaranteed, 
the encode outputs being specified to limits a half step higher than those shown above. This takes into 
account the combined effects of chord endpoint accuracy, step nonlinearity, encode current error, full 
scale current deviation from ideal, full scale symmetry error, zero scale current, full scale drift, and output 
impedance over the specified output voltage compliance range. Note that the guaranteed monotonicity 
ensures that adjacent step current levels will not overlap as might otherwise be implied from the minimum 
and maximum values shown in the above table. 


TABLE 2 

IDEAL DECODER OUTPUT VALUES EXPRESSED IN dB DOWN FROM OVERLOAD LEVEL (+3dBmo) 




^\CHORD 
STEP^^ 





1 


2 


3 


4 


5 


6 


7 







1 
2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 


-69.07 
-63.05 
-59.53 
-57.03 
-55.10 
-53.51 
-52.17 
-51 .01 
-49.99 
-49.07 
-48.25 
-47.49 
-46.80 
-46.15 
-45.55 


-44.73 
-43.73 
-42.84 
-42.03 
-41.29 
-40.61 
-39.98 
-39.39 
-38.84 
-38.32 
-37.83 
-37.37 
-36.93 
-36.51 
-36.1 1 
-35.73 


-35.18 
-34.51 
-33.88 
-33.30 
-32.75 
-32.24 
-31.75 
-31 .29 
-30.85 
-30.44 
-30.04 
-29.66 
-29.29 
-28.95 
-28.61 
-28.29 


-27 82 
-27.24 
-26.70 
-26.18 
-25.70 
-25.24 
-24.80 
-24.39 
-23.99 
-23.61 
-23.25 
-22.90 
-22.57 
-22.25 
-21 .94 
-21 .63 


■21.20 
-20,66 
-20.15 
-19.66 
-19.21 
-18.77 
-18.36 
-17.96 
-17.58 
-17.22 
-16.87 
-16.54 
-16.22 
-15.91 
-15.61 
-15.32 


-14.90 
-14.37 
-13.87 
-13.40 
-12.96 
-12.53 
-12.13 
-11.74 
-1 1 .37 
-11.02 
-10.68 
-10.35 
-10.03 
-9.73 
-9.43 
-9.15 


-B.74 
-8.22 
-7.73 
-7.27 
-6.83 
-6.41 
-6.01 
-5.63 
-5.26 
-4.91 
-4.57 
-4.25 
-3.93 
-3.63 
-3.34 
-3.06 


-2.65 
-2.13 
-1.65 
-1.19 
-0.75 
-0.33 
+0.06 
+0.44 
+0.81 
+ 1.16 
+ 1.49 
+ 1.82 
+2.13 
+2.43 
+2.72 
+3.00 




The —37 dBmo and -50 dBmo output points significant for the Belt D3 system specification can be found 
between steps 1 1 and 1 2 on chord 1 , and steps 8 and 9 on chord 0, respectively. Outputs corresponding to 
points below -50dB are specified in Table 1 for an accuracy of ± a half step. 



3-54 



Am6072 



THEORY OF OPERATION 
Functional Description 

The Am6072 is an 8-bit, nonlinear, digital-to-analog conver- 
ter with high impedance current outputs. The output current 
value is proportional to the product of the digital inputs and 
the input reference current. The full scale output current, \f$, 
is specified by the input binary code 111 1111, and is a linear 
function of the reference current, l REF . There are two operat- 
ing modes, encode and decode, which are controlled by the 
Encode/Decode, (E/D), input signal. A logic 1 applied to the 
E/D input places the Am6072 in the encode mode and current 
will flow into the Ioe(+) or 'oei-i output, depending_on the 
state of the Sign Bit (SB) input. A logic at the E/D input 
places the Am6072 in the decode mode. 

The transfer characteristic is a piece-wise linear approxi- 
mation to the Bell System /x-225 logarithmic law which 
can be written as follows: 



endpoint current, (Step 15), and the current which corres- 
ponds to the preceding step, (Step 14), is maintained at about 
0.3dB over most of the dynamic range. The difference bet- 
ween the ratios of full scale current to chord endpoint cur- 
rents of adjacent chords is similarly maintained at approxi- 
mately 6dB over most of the dynamic range. Resulting 
signal-to-quantizing distortions due to non-uniform quantiz- 
ing levels maintain an acceptably low value over a 40dB 
range of input speech signals. Note that the 72dB output 
dynamic range for the Am6072 corresponds to the dynamic 
range of a sign plus 12-bit linear, binary D/A converter. 

In order to achieve a smoother transition between adja- 
cent chords, the step size between these chord end points 
is equal to 1.5 times the step size of the lower chord. 
Monotonic operation is guaranteed by the internal device 
design over the entire output dynamic range by specify- 
ing and maintaining the chord end points and step size 
deviations within the allowable limits. 



Y = 0.188n (1 + m IXI ) sgn (X) 

where: X = analog signal level normalized to unity 
(encoder input or decoder output) 
Y = digital signal level normalized to unity 

(encoder output or decoder input) 
At = 255 

The current flows from the external circuit into one offour 
possible analog outputs determined by the SB and E/D in- 
puts. The output currenttransferfunctioncan be represented 
by a total of 16 segments or chords addressable through the 
SB input and three chord select bits. Each chord can be 
further divided into 16 steps, all of the same size. The step 
size changes from one chord to another, with the smallest 
step of 0.5aiA found in the first chord near zero output cur- 
rent, and the largest step of 64aiA found in the last chord near 
full scale output current. This nonlinear feature provides 
exceptional accuracy for small signal levels near zero output 
current. The accuracy for signal amplitudes corresponding 
to chord is equivalent to that of a 12-bit linear, binary D/A 
converter. However, the ratio (in dB) between the chord 



Operating Modes 

The basic converter function is conversion of digital input 
data into a corresponding analog current signal, i.e., the 
basic function is digital-to-analog decoding. The basic de- 
coder connection for a sign plus 7-bit input configuration is 
shown in Figure 1. The corresponding dynamic range is 
72dB, and input-output characteristics conform to the stan- 
dard decoder transfer function with output current values 
specified in Table 1. The E/D input enables switching bet- 
ween the encode, Ioe(+) or Ioe(-)> and the decode, Iod(+) or 
loo(-)' outputs. A typical encode/decode test circuit is shown 
in Figure 2. This circuit is used for output current measure- 
ments. When the E/D input is high, (a logic 1), the converter 
will assume the encode operating mode and the output cur- 
rent will flow into one of the l 0E outputs (as determined by 
the SB input). When operating in the encode mode as shown 
in Figure 3, an offset current equal to a half step in each chord 
is required to obtain the correct encoder transfer characteris- 
tic. Since the size of this step varies from one chord to 
another, it cannot easily be added externally. As indicated in 
the block diagram this required half step of encode current, 




ANALOG 
OUTPUT 

15.0V 



6 *15V — 



|REF=V REF /R REF L'C-278 
IDEAL VALUES: I ref = 528M, IfS " 2007.75uA 





E/D 


SB 


Bl 


B 2 


B 3 


B 4 


B5 


Bd 


B 7 


E 


POSITIVE FULL SCALE 





1 




1 


1 




1 


1 


1 


5.019V 


( + ) ZERO SCALE +1 STEP 



























0.0012V 


(+) ZERO SCALE 





1 























ov 


(-)ZERO SCALE 




o 


o 














o 





ov 


I-) ZERO SCALE +1 STEP 


























1 


■0.0012V 


NEGATIVE FULL SCALE 








1 


1 


1 


i 




1 


1 


-5.019V 



Figure 1. Detailed Decoder Connections. 



DIGITAL INPUTS 



vst. wwwx 



B 7 B 6 B S 8 4 B 3 B 2 B l SB E ' D 

'HI*) 




R-l » R 2 = R3 = R4 = 2.5kS2 ±0.1 % 

LINE SELECTION TABLE 



TEST 






OUTPUT 


GROUP 


E/D 


SB 


MEASUREMENT 




1 


1 


lOE M 


(Ec/n,) 


2 


1 





<OE (-1 


<E ,/R 2 » 


3 





1 


lOD (+1 


IE 2/R3> 


4 








loo (-1 


<E02 /R 4> 



Figure 2. Output Current DC Test Circuit. 



3-55 



Am6072 



l EN , is automatically added to the I e output through the 
internal chip design. This additional current will, for exam- 
ple, make the ideal full scale current in the encode mode 
larger than the same current in the decode mode by 32/xA. 
Similarly, the current levels in the first chord near the origin 
will be offset by 0.25/xA, which will bring the ideal encode 
current value for step on chord to ±0.25aiA with respect to 
the corresponding decode current value of O.O^iA. This addi- 
tional encode half step of current can be used for extension 
of the output dynamic range from 72dB to 78dB, when the 
converter is performing only the decode function. The cor- 
responding decoder connection utilizes the E/D input as a 
ninth digital input and has the outputs Iod(+) and 'oe(+) and 
the outputs Iod(-) and 'oei-i tied together, respectively. 

When encoding or compression of an analog signal is re- 
quired, the Am6072 can be used together with a Successive 
Approximation Register (SAR), comparator, and additional 
SSI logic elements to perform the A/D data conversion, as 
shown in Figure 3. The encoder transfer function, shown on 
page 1 , characterizes this A/D converter system. The fi rst task 
of this system is to determine the polarity of the incoming 
analog signal and to generate a corresponding SB input 
value. When the proper Start, S, and Conversion Complete, 
CC, signal levels are set, the first clock pulse sets the MSB 
output of the SAR, Am2502, to a logic and sets all other 
parallel digital outputs to logic 1 levels. At the same time, the 
flip-flop is triggered, and its output provides the E/D input 
with a logic level. No current flows into the I e outputs. This 
disconnects the converter from the comparator inputs, and 
the incoming analog signal can be compared with the 
ground applied to the opposite comparator input. The result- 
ing comparator output is fed to the Am2502 serial data input, 
D, through an exclusive-or gate. At the same time, the sec- 
ond input to the same exclusive-or gate is held at a logic 
level by the additional successive approximation logic 
shown in Figure 3. This exclusive-or gate inverts the com- 
parator's outputs whenever a negative signal polarity is de- 
tected. This maintains the proper output current coding, i.e., 
all ones for full scale and all zeros for zero scale. 

The second clock pulse changes the E/D input back to a logic 
1 level because the CC signal changed. It also clocks the D 



input signal of the Am2502 to its MSB output, and transfers it 
to the SB input of the Am6072. Depending upon the SB input 
level, current will flow into the Ioe{+) ° r bE(-) output of the 
Am6072. 

Nine total clock pulses are required to obtain a digital binary 
representation of the incoming analog signal at the eight 
Am2502 digital outputs. The resulting Am6072 analog out- 
put signal is compared with the analog input signal after 
each of the nine successive clock pulses. The analog signal 
should not be allowed to change its value during the data 
conversion time. In high speed systems, fast changes of the 
analog signals at the A/D system input are usually prevented 
by using sample and hold circuitry. 



Additional Considerations and Recommendations 

In Figure 1, an optional operational amplifier converts the 
Am6072 output current to a bipolar voltage output. When the 
SB input is a logic 1, sink current appears at the amplifier's 
negative input, and the amplifier acts as a current to voltage 
converter, yielding a positive voltage output. With the SB 
value at a logic 0, sink current appears at the amplifier's 
positive input. The amplifier behaves as a voltage follower, 
and the true current outputs will swing below ground with 
essentially no change in output current. The SB input steers 
current into the appropriate ( + ) or (-) output of the Am6072. 
The resulting operational amplifier's output in Figure 2 
should ideally be symmetrical with resistors R1 and R2 
matched. 

In Figure 2, two operational amplifiers measure the cur- 
rents of each of the four Am6072 analog outputs. Resistor 
tolerances of 0.1% give 0.1% output measurement error 
(approximately 2^tA at full scale). The input offset currents 
of the A1 and A2 devices also increase output measure- 
ment error and this error is most significant near zero 
scale. The Am101A and 308 devices, for example, may be 
used for A1 and A2 since their maximum offset currents, 
which would add directly to the measurement error, are 
only 10nA and 1nA, respectively. The input offset voltages 
of the A1 and A2 devices, with output resistor values of 



ANALOG INPUT 



(GROUNDED FOR 

SINGLE-ENDED | 

INPUTS) | 



T 



START +5.0 V 



— 2.5 kn> >Z5 




r^E> 



1 





12 3 4 



1 



E« SB !, B, B, !, % >, B, 
Am«072 V " 6FW 

I 

TER v 



6 ' « 8 -4-REFH 
► 18.94kfi 



D TO A CONVERTER 



13 I Tel 10 I j 

A-15V O +15V -±r 

Figure 3. Detailed Encoder Connections. 



«REF(-> 
20kfi 



3-56 



Am6072 



2.5kfi, also contribute to the output measurement error by 
a factor of 400nA for every mV of offset at the A1 and A2 
outputs. Therefore, to minimize error, the offset voltages 
of A1 and A2 should be nulled. 



The recommended operating range for the reference cur- 
rent Ir EF is from O.lrriA to 1.0mA. The full scale output 
current, l F s, is a linear function of the reference current, 
and may be calculated from the equation l FS = 3.8 l REF . 
This tight relationship between l REF and l FS alleviates the 
requirement for trimming the l REF current if the R REF re- 
sistors values are within ±1% of the calculated value. 
Lower values of l REF will reduce the negative power sup- 
ply current, (I-), and will increase the reference amplifier 
negative common mode input voltage range. 

The ideal value for the reference current l REF = V ref /Rr EF is 
528/xA. The corresponding ideal full scale decode and en- 
code current values are 2007.75^tA and 2039.75/xA, respec- 
tively. A percentage change from the ideal l REF value pro- 
duced by changes in V REF or R REF values produces the same 
percentage change in decode and encode output current 
values. The positive voltage supply, V+, may be used, with 
certain precautions, for the positive reference voltage V REF . 
In this case, the reference resistor R REF(+) should be split into 
two resistors and their junction bypassed to ground with a 
capacitor of 0.01/iF. The total resistor value should provide 
the reference current l REF = 528/xA. The resistor Rref(-) 
value should be approximately equal to the R REF(+) value in 
order to compensate for the errors caused by the reference 
amplifier's input offset current. 

An alternative to the positive reference voltage applications 
shown in Figures 1, 2 and 3 is the application of a negative 
voltage to the V R( _) terminal through the resistor Rref(-) 
with the Rr EF ( + ) resistor tied to ground. The advantage of 
this arrangement is the presence of very high impedance at 
the V R( _) terminal while the reference current flows from 
ground through Rr E f(+) into the V R(+) terminal. 





The Am6072 has a wide output voltage compliance suit- 
able for driving a variety of loads. With l REF = 528/u.A and 
V- = -15V, positive voltage compliance is +18V and 
negative voltage compliance is -5.0V. For other values of 
l RE F and V-, the negative voltage compliance, V c(-). 
may be calculated as follows: 

Voc(-) = (V-) + (2 • I REF • 1.5kfi) + 8.4V. 

The following table contains V oc( _) values for some 
specific V-, l REF , and l FS values. 



Negative Output Voltage Compliance Vqc(— ) 



'ref 


264/jA 
(1mA) 


528juA 
(2mA) 


1056/uA 
(4mA) 


-12V 


-2.8V 


-2.0V 


-0.4V 


-15V 


-5.8V 


-5.0V 


-3.4 V 


-18V 


-8.8 V 


-8.0 V 


-6.4V 



The V LC input can accommodate various logic input 
switching threshold voltages allowing the Am6072 to in- 
terface with various logic families. This input should be 
placed at a potential which is 1.4V below the desired logic 
input switching threshold. Two external discrete circuits 
which provide this function for non-TTL driven inputs are 
shown in Figure 4. For TTL-driven logic inputs, the V LC 
input should be grounded. If negative voltages are 
applied at the digital logic inputs, they must have a value 
which is more positive than the sum of the chosen V- 
value and +10V. 



a V- value chosen between -15V and -11V, the 
j, the input reference common mode voltage range, 



With 

V 0C ( 

and the logic input negative voltage range are reduced by an 
amount equivalent to the difference between -15V and the 
V- value chosen. 

With a V+ value chosen between +5V and +15V, the refer- 
ence amplifier common mode positive voltage range and the 
V LC input values are reduced by an amount equivalent to the 
difference between +15V and the V+ value chosen. 



ECL 



CMOS, HTL, NMOS 





(See Motes 2 and 3) 

Figure 4. Interfacing Circuits for ECL, CMOS, HTL, 
and NMOS Logic Inputs. 



DIGITAL INPUTS 



OOOOOOOOO 



B, B„ Ik, B, B 3 Bj B, SB E/5 



113 Ha 1 10 

-lev o*i5v ~= 




INPUT CODE 
(E/D.SB, B1 B 7 ) 


OUTPUT VOLTAGE (V) 


"A" 


"B" 


"C" 


D1FF 


10 111 1111 
io no mi 
10 0000000 




+5.02 
+10.00 


N/A 


N/A 


N/A 


01 lit 1111 
01 110 1111 

01 0000000 

00 000 0000 
00 1 1 1 1 1 1 
00 1 1 1 1111 


N/A 


-5.00 
+0.02 
+5.00 
+5.00 
+5.00 
♦5.00 


+ 5.00 
+5.00 
+5.00 
+5.00 
+0.02 
-5.00 


-10.00 
-4.98 


+4.98 
+ 10.00 



Figure 5. Resistive Output Connections. 



Notes: 2. Set the voltage "A" to the desired logic input switching threshold. 

3. Allowable range of logic threshold is typically -5V to +13.5V when operating the companding DAC on ±15V supplies. 



3-57 



Am6072 



ADDITIONAL DECODE OUTPUT CURRENT TABLES 



Table 3 

Normalized Decoder Output (Sign Bit Excluded) 



Step (S) 


Chord (C) 





1 


2 


3 


4 


5 


6 


7 


000 


001 


010 


011 


100 


101 


110 


111 


Q 


0000 


o 


33 


99 


231 


495 


1 023 


2079 


41 91 


1 


0001 


2 


37 


1 Qy 


247 


527 


1 087 


2207 


4447 












263 




1151 


2335 


4703 




001 1 


g 




123 








2463 


4959 




01 00 


o 
o 


49 


131 


295 


623 


1 279 


2591 


521 5 


E 
D 


U I U I 


1 n 


53 


1 39 


31 1 


655 


1 343 


271 9 


5471 


6 


0110 


1 2 


57 


147 


327 


687 


1 407 


2847 


5727 


7 


0111 


14 


61 


155 


343 


719 


1471 


2975 


5983 


8 


1000 


16 


65 


163 


359 


751 


1535 


3103 


6239 


9 


1001 


18 


69 


171 


375 


783 


1599 


3231 


6495 


10 


1010 


20 


73 


179 


391 


815 


1663 


3359 


6751 


11 


1011 


22 


77 


187 


407 


847 


1727 


3487 


7007 


12 


1100 


24 


81 


195 


423 


879 


1791 


3615 


7263 


13 


1101 


26 


85 


203 


439 


911 


1855 


3743 


7519 


14 


1110 


28 


89 


211 


455 


943 


1919 


3871 


7775 


15 


1111 


30 


93 


219 


471 


975 


1983 


3999 


8031 


Step Size 


2 


4 


8 


16 


32 


64 


128 


256 



The normalized decode current, (l c s ), is calculated using: 

l c , s = 2(2 C (S + 16.5) - 16.5) 
where C = chord number; S = step number. The ideal de- 
code current, (Iqd). in mA is calculated using: 

IqD = Oc, s"7, 15(norm.)) * 'fS (M) 



where l CiS is the corresponding normalized current. To ob- 
tain normalized encode current values the corresponding 
normalized half-step value should be added to all entries in 
Table 3. 



Table 4 
Decoder Step Size Summary 



Chord 


Step Size 
Normalized 
to Full Scale 


Step Size 
in iiA with 


Step Size 
as a % of 
Full Scale 


Step Size in 
dB at Chord 
Endpoints 


Step Size as a % 
of Reading at 
Chord Endpoints 


Resolution & 
Accuracy of 
Equivalent 





2 


0.5 


0.025% 


0.60 


6.67% 


Sign + 12 Bits 


1 


4 


1.0 


0.05% 


0.38 


4.30% 


Sign + 11 Bits 


2 


8 


2.0 


0.1% 


0.32 


3.65% 


Sign + 10 Bits 


3 


16 


4.0 


0.2% 


0.31 


3.40% 


Sign + 9 Bits 


4 


32 


8.0 


0.4% 


0.29 


3.28% 


Sign + 8 Bits 


5 


64 


16.0 


0.8% 


0.28 


3.23% 


Sign + 7 Bits 


6 


128 


32.0 


1.6% 


0.28 


3.20% 


Sign + 6 Bits 


7 


256 


64.0 


3.2% 


0.28 


3.19% 


Sign + 5 Bits 








Table 


5 







Decoder Chord Size Summary 



Chord 


Chord Endpoints 
Normalized to 
Full Scale 


Chord Endpoints 

in juA with 
2007.75/jA FS 


Chord Endpoints 
as a % of 
Full Scale 


Chord Endpoints 

in dB Down 
from Full Scale 





30 


7.5 


0.37% 


-48.55 


1 


93 


23.25 


1.16% 


-38.73 


2 


219 


54.75 


2.73% 


-31.29 


3 


471 


117.75 


5.86% 


-24.63 


4 


975 


243.75 


12.1% 


-18.32 


5 


1983 


495.75 


24.7% 


-12.15 


6 


3999 


999.75 


49.8% 


-6.06 


7 


8031 


2007.75 


100% 






3-58 



Am6072 



BASIC CIRCUIT CONNECTIONS 



±10V RANGE ENCODER/DECODER 
CONNECTIONS 



) ±10V INPUT 



DIGITAL INPUTS 



99999999? 



Bj Bfl B 5 B 4 Ba 82 a, SB E/5 [»J 

Am6072 

V B (-] 



15V 6 +1BV — 




COMPLIANCE EXTENSION 
USING AC COUPLED OUTPUT 



DIGITAL INPUTS 




h U 5 4 3 Z |l 




6 -i2v 6+i;v — 



I DEAL VALUES: 
I bef = 528mA 
l FS = 2007.75M 



LOW INPUT IMPEDANCE CONNECTION 



HIGH INPUT IMPEDANCE CONNECTION 




DIGITAL INPUTS 



999999999 



DIGITAL INPUTS 



B 7 Be B 4 B 3 B 2 B, SB E/D 

Am8072 



T= tt— TJ 

O-lsv 6*16V 





Iii I 18 111 

-15V O *16V 



IREF " V| N /R| N + V REF /R REF 
l FS ~4» IREF 



<REF " (VREF - V| N )/R REF 
l FS ~4. I REF 



LOGARITHMIC DIGITAL GAIN CONTROL 
(Notes 4 & 5) 



REFERENCE AMPLIFIER DYNAMIC TEST CIRCUIT 



ATTENUATION 
■ BdB/CHORD 
> ,3dB/STEP 




FREQUENCY 
ESPON! 
TEST 




Notes: 4. Low distortion outputs are provided over a 72dB range. 

5. Up to 4 channels of output may be selected by E/D and SB logic inputs. 



3-59 



Am6072 



TYPICAL PERFORMANCE CURVES 



Reference Amplifier 
Total Harmonic Distortion 
Versus Frequency (80kHz Filter) 
(Notes 6, 7, 8) 





1.0 








0.5 


z 




g 






0.2 


BE 




o 


0.1 


f 


t/i 
Q 


0.05 


U 




z 


0.02 


o 




a: 


0.01 


< 




x 005 






< 




hr 0.002 


o 




(E 


0.001 



LARGE SIGNAL 
INPUT *5V PEAK 
(50* MODULATION! 

100 1.0k 10k 

FREQUENCY - Hz 



Reference Amplifier 
Input Frequency Response 




LARGE SIGNAL s 
(SLEW RATE LIMITED! 
5V PEAK 
(50% MODULATION! 

I III I II I 



lk 



10k 100k 1M 10M 
FREQUENCY - Hz 



Reference Amplifier 
Input Common-Mode Range 
(Note 9) 





3.2 




2.3 


< 




E 
I 


2.4 


z 


2.0 


CC 






1.6 






CJ 




r- 


1.2 


□ 
E 




D 


0.8 


O 






0.4 










" T MIN ,oT MAX 
























V- 


■ -1 


>V 






V 


+ " + 


1E.V 










EF ■ 


0.5mA 1 












































F" 


).Z5n 




f 






|R 














-o - 

| 











6 10 14 18 



REFERENCE COMMON-MODE VOLTAGE 



Power Supply Currents 
Versus Power Supply Voltages 



TTT 

-I- vs. V-_ 



ALL BITS "HIGH" OR "LOW" 
l FS - 2.0mA 

J 1 |_| 1 L_l 1_ 

10 12 



2.0 4.0 6.0 8.0 10 12 14 16 18 20 
POSITIVE OR NEGATIVE POWER SUPPLY - 



Power Supply Currents 
Versus Temperature 



















1 














































-2 


0m 


X 




























1 






































- A 


LL 
V 


JITS 


"HIGH 
15V, V 


' O 


"L 
-15 


OW 

J 







50 100 
TEMPERATURE - 'C 



Output Current Versus 
Output Voltage 
(Output Voltage Compliance) 



l REF = 1.0mA 



1 MIN TO 1 MAX 



IreF = 0.5mA 



-14 -10 -6 -2 2 6 10 14 
OUTPUT VOLTAGE -V 




Notes: 6. THD is nearly independent of the logic input code. 

7. Similar results are obtained for a high input impedance connection using Vr(_) as an input. 

8. Increased distortion above 50kHz is due to a slew rate limiting effect which determines the large signal bandwidth. For an input of ±2.5V peak (25% 
modulation), the bandwidth is 100kHz. 

9. Positive common mode range is always (V+) -1.5V. 

10. All bits are fully switched with less than a half step error at switching points which are guaranteed to lie between 0.8V and 2.0V over the operating 
temperature range. 

1 1 . The logic input voltage range is independent of the positive power supply and logic inputs may swing above the supply. 



3-60 



Am6072 



TIME SHARED CONVERTER CONNECTIONS 



PCM CODEC - PARALLEL DATA I/O 




APPLICATION INFORMATION 



1. To perform a transmit operation cycle the START pulse 
must be held low for one clock cycle; the receive opera- 
tion is performed without the successive approximation 
regis ter, SAR. 

2. XMT and RECEIVE command signals are mutually exclu- 
sive. 

3. Duration of the RECEIVE command signal must 
accommodate the Am6072 settling time plus the sam- 
pling time required by the sample and hold, (S & H), 
circuit used at the CODEC'S analog output. The receiving 
d ata mu st not change during this time. 

4. A XMT command si gnal must be issued after a high-to- 
low transition of the CONVERSION COMPLETE, CC, sig- 
nal. Its duration depends on the time required by the 
digital time division switch circuitry to sample the 8-bit 
parallel transmit data bus. 



5. Data conversion for a transmit operation is completed in 9 
clock cycles because the SAR must be initialized before 
every new conversion. Data conversion for a receive op- 
eration corresponds to the Am6072 settling time; the re- 
ceiving and transmit data transfers can be done simul- 
taneously by employing separate transmit and receive 
data buses and utilizing data storage devices for the re- 
ceive data. 

6. A sample comm and puls e for a transmit operation can 
coincide with the START pulse; its duration depends on 
the sample and hold circuit used at the CODEC'S analog 
input. 

7. A sample command pulse for a receive operation must be 
delayed from a low-to-high transition of the RECEIVE 
command signal by an amount equal to the Am6072 set- 
tling time. Its termination can coincide with a high-to-low 
transition of the RECEIVE command signal. 



3-61 



Am6072 



TIME SHARED CONVERTER CONNECTIONS (Cont.) 



SINGLE CHANNEL PCM CODEC - SERIAL DATA I/O 




APPLICATION INFORMATION 

1 . Before beginning ei 



the STAI 
cycle. 



r a transmit or a receive operation, 
t be held low for one complete clock 



2. XMT and RECEIVE command signals are mutually exclu- 
sive. Their durations must accommodate the time required 
for conversion of an outgoing or an incoming series of 8 di- 
gital bits, respectively. 

3. Data conversion for either operation, transmit or receive, is 
completed in 9 clock cycles. 



4. During the receive cycle the successive approximation re- 
gister, SAR, is acting as a serial-in to parallel-out shift re- 
gister, with data supplied from data storage devices. 

5. A sample command pulse for a transmit cycle must be is- 
sued before a XMT command signal; its duration depends 
on the sample and hold, S & H, circuit used. 

6. A sample command pulse for a receive cycle must be de- 
layed by a time equal to the Am6072 settling time after a 
high-to-low transition of the CONVERSION COMPLETE, 
CC, signal occurs. 



8 LINE CODEC TDM PCM/PABX SYSTEM - BLOCK DIAGRAM 



CHANNEL 
ANALOG 
MUX 



CHANNEL 

ANALOG 
MUX 






1 



SUCCESSIVE 
APPROXIMATION 
LOGIC 



FROM TDMS 



TIME- 
DIVISION 

MUX 
SWITCH 



3-62 



Am6072 



COMPANDOR TRACKING SPECIFICATION 



I BELL D3 SYSTEM 
I SPECIFICATION 
I (MAXIMUM) 



Am6072 
SPECIFICATION 
(MAXIMUM! 



-40 -37 -30 -20 
INPUT SIGNAL LEVEL - 



-10 +3 



COMPANDOR TRACKING TEST BLOCK DIAGRAM 



© 



MP-200CD 
OSCILLATOR 
OR EQUIVALENT 



HP-4O0D 
VOLTMETER 
Ofl EQUIVALENT 



ATTENUATOR 



© 




FILTER 







ENCODER 

(Am6072) 



DECODER 

(Am6072) 



D3 NOISE AND DISTORTION SPECIFICATION 



The Am6072 has a negligible idle channel noise contribution. Signal-to-quantizing-distortion ratio, (S/D), is 
guaranteed to exceed the minimum values specified for D3 channels as follows: 



Input Level 1020 Hz Sinewave 


S/D, C-Message Weighting 


to -30 dBmo 
At -40 dBmo 
At -45 dBmo 


33 dB 
27 dB 
22 dB 



DECODER OPERATION DURING SIGNALLING FRAME 




DIGITAL INPUTS 



B 7 B 6 6 5 B 4 B 3 B 2 B, SB E/D 



V R(+) 




The Am6072 can perform the decoding function in a D3 channel bank system. During signalling frames the 
least significant bit, B7, of each 8-bit word is used for signalling messages and only seven bits are used for 
sample coding. In order to minimize the quantizing error during these signalling frames, the Am6072 output 
is increased by a half step from its corresponding decode output value by switching the E/D input from a 
logic level to a logic 1. 



Metallization and Pad Layout 



=4 



=3 
»1 



17 'ODI-I 

IB loDl+l 

15 'OEI-I 

14 'OE(+) 




3-63 



Am6073 



Companding D-to-A Converter for PCM Communication Systems 




Distinctive Characteristics 

• Tested to CCITT A-law tracking specification 

• Absolute accuracy specified - includes all errors over 
temperature range 

• Settling time 300ns typical 

• Ideal for multiplexed PCM systems 

• Output dynamic range of 62 dB 



• Improved pin-for-pin replacement for DAC-87 

• Microprocessor controlled operations 

• Multiplying operation 

• Negligible output noise 

• Monotonicity guaranteed over entire dynamic range 

• Wide output voltage compliance 

• Low power consumption 



GENERAL DESCRIPTION 



The Am6073 is a monolithic 8-bit, companding digital-to- 
analog (D/A) data converter with true current outputs and 
large output voltage compliance for fast driving a variety of 
loads. The transfer function of the Am6073 complies with the 
CCITT A-87.6 companding law, and consists of 13 linear seg- 
ments or chords. A particular chord is identified with the sign 
bit input, (SB), and three chord select input bits. Each chord 
contains 16 uniformly spaced linear steps which are deter- 
mined by four step select input bits. The resulting dynamic 
range achieved with this 8-bit format is 62dB. Accuracy and 
monoticity are assured by the internal circuit design and are 
guaranteed over the full temperature range. The Am6073 is 



tested to the CCITT A-law compandor tracking specification 
for pulse code modulation (PCM) transmission systems. The 
application of the Am6073 in communication systems pro- 
vides an increased signal-to-noise ratio, reduces system sig- 
nal distortion, and stimulates wider usage of computerized 
channel switching. Other application areas include digital 
audio recording, voice synthesis, and secure communica- 
tions. When used in PCM communication systems, the 
Am6073 functions as a complete PCM decoder with addi- 
tional encoding capabilities which make it ideal for im- 
plementation in CODEC circuits. 



FUNCTIONAL BLOCK DIAGRAM 



B 5 B R B 
6 7 



1 C 



CHORD AND 



CONNECTION DIAGRAM 
Am6073 



ENCODE/DECODE SELECT: 1 = ENCODE 1 

SIGN BIT INPUT: t - POSITIVE 2 

MOST SIGNIFICANT CHORD BIT INPUT 3 Q 

SECOND CHORD BIT INPUT 4 Q 

LEAST SIGNIFICANT CHORD BIT INPUT 5 Q 

MOST SIGNIFICANT STEP BIT INPUT 6 Q 

SECOND STEP BIT INPUT 7 £ 

THIRD STEP BIT INPUT 8 £ 

LEAST SIGNIFICANT STEP BIT INPUT 9 \Z 



'OD(-) 
'OD(*l 



18 POSITIVE POWER SUPPLY 

^17 DECODER OUT: E/D SB = 00 

^16 DECODER OUT: E/D SB = 01 

QE( _ t ^ 15 ENCODER OUT: E/D SB =10 

'OE|+) ^ 1" ENCODER OUT: E/D SB = 11 

V- 13 NEGATIVE POWER SUPPLY 

V RM D 12 NEGATIVE REFERENCE INPUT 

V R(+ , n POSITIVE REFERENCE INPUT 

V LC ~3 10 THRESHOLD CONTROL 



Top View 
Pin 1 is marked for orientation. 



LIC-297 



ORDERING INFORMATION 



Part Number 


Temperature 


Accuracy 


Am6073DM 


-55°C to +125X 


Conforms to CCITT 
A-law specification 


Am6073DC 


0°C to +70°C 



SIMPLIFIED CONVERSION TRANSFER FUNCTIONS 
Decoder Characteristic Encoder Characteristic 



Other AMD Companding D/A Converters 


Am6070DM, DC 


Conforms to industrial ft-law spec. 


Am6071DM, DC 


Conforms to industrial A-law spec. 


AM6072DM, DC 


Conforms to Bell D3 spec. 





3-64 



Am6073 



MAXIMUM RATINGS above which useful life may be impaired 



V+ Supply to V- Supply 36V 


Operating Temperature 


V|_q Swing 


V- plus 8V to V+ 


ivil L urade 


cc°p to +19>i c r 

— OO \j LO ' 1 \j 


Output Voltage Swing V- plus 8V to V- plus 36V 


COM'L Grade 


0°Cto +70° C 


Reference Inputs V— to V+ 


Storage Temperature 


-65°Cto +150°C 


Reference Input Differential Voltage ±18V 


Power Dissipation Ta< 100°C 


500mW 


Reference Input Current 1.25mA 


For Ta > 100 C derate at 




Logic Input 


s V- plus 8V to V- plus 36V 


Lead Soldering Temperature 


300°C (60 sec) 



















GUARAN1 


fEED FUNCTIONAL SPECIFICATIONS 







Resolution 


±128 Steps 


Monotonic 


ty 


For both groups of 128 steps and over full operating temperature range 


Dynamic Range 


62 dB, (20 log <l 7f 15 /l , i)> 



ELECTRICAL CHARACTERISTICS (Note 1) 

These specifications apply for V+ = +15V, V- = -15V, Iref = 512/jA, 0°C<Ta <+70°C, forthe commercial grade, -55°C<Ta 
< +1 25°C, for the military grade, and for all 4 outputs unless otherwise specified. 

Parameter Description Test Conditions Min. Typ. Max. Unit 





Settling Time 


To within ±1/2 step at Ta " 25°C, 
Output switched from Izs to ' FS 




300 


500 


ns 




Chord Endpoint Accuracy 


V REF = +10,000V 
RrEF+ = 19-53kfi 
RrEF- = 20kn 
-5V < V 0UT < +18V 


See Table 1 for absolute accuracy 
limits which cover all errors related 
to the transfer characteristic. 




Step Nonlinearity 


Ien 


Encode Current 


ifs(d) 

IFS(E) 


Full Scale Current Deviation from Ideal 


i (+)-io(-) 


Full Scale Current Symmetry Error 
Decode or Encode Pair 


izs 


Zero Scale Current 


AlFS 


Full Scale Current Drift 


voc 


Output Voltage Compliance 


Output within limits specified by Table 1 


-5 




+ 18 


Volts 


Idis 


Disable Current 


Leakage of output disabled by E/D or SB 




5.0 


50 


nA 


Ifsr 


Output Current Range 







2.0 


4.2 


mA 


V|L 


Logic Input 
Levels 


Logic "0" 


v LC = ov 






0.8 


Volts 


V|H 


Logic "1 " 


2.0 






Volts 


I IN 


Logic Input Current 


V| N = -5V to +18V 






40 


MA 


V|S 


Logic Input Swing 


V-= -15V 


-5 




+18 


Volts 


'bref- 


Reference Bias Current 






-1.0 


-4.0 


M A 


dl/dt 


Reference Input Slew Rate 




0.12 


0.25 




mA/MS 


PSSI FS + 
PSSI FS _ 


Power Supply Sensitivity Over Supply Range 
(Refer to Characteristic Curves) 


V+ = +4.5 to +18V, V- = -1 5V 




0.005 


0.1 


dB 


V- = -10.8V to -18V, V+ = +15V 




0.01 


0.1 


l + 


Power Supply Current 


V+ = +5V to +15V, V- = -1 5V, 
lps = 2.0mA 




2.7 


4.0 


mA 


I- 




-6.7 


-8.8 


pd 


Power Dissipation 


V- = -15V, V 0UT " 0V 
l FS = 2.0mA 


V+ = +5V 




114 


152 


mW 


V+ - +15V 




141 


192 



Note 1 . In a companding DAC the term LSB is not used because the step size within each chord is different. For example, in the first cnord around zero (Cq> 
the step size is 1 ,0>A, while in the last chord near full scale (Cy) the step size is 64/jA. 



3-65 





CHORD 


STEP 





1 


2 


3 


4 


5 


6 


7 





.000 
.500 
1.000 


16.032 
16.500 
16.982 


32.064 
33.000 
33.964 


64.127 
66.000 
67.927 


128.25 
132.00 
135.85 


256.51 
264.00 
271.71 


513.02 
528.00 
543.42 


1026.04 
1056.00 
1086.84 


1 


1.000 
1.500 
2.000 


17.003 
17.500 
18.011 


34.007 
35.000 
36.022 


68.014 
70.000 
72.044 


136.03 
14O.00 
144.09 


272.06 
280.00 
288.18 


544.11 

560.00 
576.35 


1088.22 
1120.00 
1152.70 


2 


2.103 
2.500 
2.971 


17.975 
18.500 
19.040 


35.950 
37.000 
38.080 


71.900 
74.000 
76.161 


143.80 
148.00 
152.32 


287.60 
296.00 
304.64 


575.20 
592.00 
609.29 


1150.41 
1184.00 
1218.57 


3 


2.945 
3.500 
4.160 


18.947 
19.500 
20.069 


37.893 
39.000 
40.139 


75.787 
78.000 
80.278 


151.57 
156.00 
160.56 


303.15 
312.00 
321.11 


606.30 
624.00 
642.22 


1212.59 
1248.00 
1284.44 


4 


4.248 
4.500 
4.767 


19.918 
20.500 
21.099 


39.837 
41.000 
42.197 


79.673 
82.000 
84.394 


159.35 
164.00 
168.79 


318.69 
328.00 
337.58 


637.39 
656.00 
675.16 


1274.78 
1312.00 
1350.31 


5 


5.192 
5.500 
5.826 


20.890 
21.500 
22.128 


41.780 
43.000 
44.256 


83.560 
86.000 
88.511 


167.12 
172.00 
177.02 


334.24 
344.00 
354.04 


668.48 
688.00 
708.09 


1336.96 
1376.00 
1416.18 


6 


6.136 
6.500 
6.885 


21.862 
22.500 
23.157 


43.723 
45.000 
46.314 


87.447 
90.000 
92.628 


174.39 
180.00 
185.26 


349.79 
360.00 
370.51 


699.57 
720.00 
741.02 


1399.14 
1440.00 
1482.05 


7 


7.080 
7.500 
7.944 


22.833 
23.500 
24.186 


45.667 
47.000 
48.372 


91.333 
94.000 
96.745 


182.67 
188.00 
1 93.49 


365.33 
376.00 
386.98 


730.66 
752.00 
773.96 


1461.33 
1504.00 
1547.92 


8 


8.025 
8.500 
9.004 


23.805 
24.500 
25.215 


47.610 
49.000 
50.431 


95.220 
98.000 
100.862 


190.44 
196.00 
201.72 


380.88 
392.00 
403.45 


761.76 
784.00 
806.89 


1523.51 
1568.00 
1613.79 


9 


8.969 
9.500 
10.063 


24.777 
25.500 
26.245 


49.553 
51.000 
52.489 


99.106 
102.000 
104.978 


198.21 
204.00 
209.96 


396.42 
408.00 
419.91 


792.85 
816.00 
839.83 


1585.70 
1632.00 
1679.66 


10 


9.913 
10.500 
11.122 


25.748 
26.500 
27.274 


51.496 
53.000 
54.548 


102.993 
106.000 
109.095 


205.99 
212.00 
218.19 


411.97 
424.00 
436.38 


823.94 
848.00 
872.76 


1647.88 
1696.00 
1745.52 


11 


10.857 
1 1 .500 
12.181 


26.720 
27.500 
28.303 


53.440 
55.000 
56.606 


106.879 
110.000 
113.212 


213.76 
220.00 
226.42 


427.52 
440.00 
452.85 


855.03 
880.00 
905.70 


1710.07 
1760.00 
1811.39 


12 


11.801 
12.500 
13.241 


27.691 
28.500 
29.332 


55.383 
57.000 
58.664 


110.766 
114.000 
117.329 


221.53 
228.00 
234.66 


443.06 
456.00 
469.32 


886.12 
912.00 
938.63 


1722.25 
1824.00 
1877.26 


13 


12.745 
13.500 
13.894 


28.663 
29.500 
30.361 


57.326 
59.000 
60.723 


114.652 
118.000 
121.446 


229.30 
236.00 
242.89 


458.61 
472.00 
485.78 


917.22 
944.00 
971.57 


1834.43 
1888.00 
1943.13 


14 


14.089 
14.500 
14.923 


29.635 
30.500 
31.391 


59.269 
61.000 
62.781 


118.539 
122.000 
125.562 


237.08 
244.00 
251.12 


474.15 
488.00 
502.25 


948.31 
976.00 
1004.50 


1896.62 
1952.00 
2009.00 


15 


15.060 
15.500 
15.953 


30.606 
31.500 
32.420 


61.231 
63.000 
64.840 


122.425 
126.000 
129.679 


244.85 

252.00 
259.36 


489.70 
504.00 
518.72 


979.40 
1008.00 
1037.43 


1958.80 
2016.00 
2074.87 


STEP 
SIZE 


1 


1 


2 


4 


8 


16 


32 


64 



Minimum, ideal and maximum values are specified for each step. The minimum and maximum values 
are specified to comply with the CCITT A-law compandor tracking requirements. All four outputs are 
guaranteed, the encode outputs being specified to limits a half step higher than those shown above. This 
takes into account the combined effects of chord endpoint accuracy, step nonlinearity, encode current 
error, full scale current deviation from ideal, full scale symmetry error, zero scale current, full scale drift, 
and output impedance over the specified output voltage compliance range. Note that the guaranteed 
monotonicity ensures that adjacent step current levels will not overlap as might otherwise be implied 
from the minimum and maximum values shown in the above table. 



TABLE 2 

IDEAL DECODER OUTPUT VALUES EXPRESSED IN dB DOWN FROM OVERLOAD LEVEL (+3dBmo) 



STEP 


CHORD 





1 


2 


3 


4 


5 


6 


7 





-69.11 


-38.74 


-35.72 


-26.70 


-20.68 


-14.66 


-8.64 


-2.62 


1 


-59.57 


-38.23 


-32.21 


-26.19 


-20.17 


-14.15 


-8.13 


-2.11 


2 


-55.13 


-37.75 


-31.73 


-25.71 


-19.68 


-13.66 


-7.64 


-1.62 


3 


-52.21 


-37.29 


-31.27 


-25.25 


-19.23 


-13.21 


-7.19 


-1.17 


4 


-50.03 


-36.85 


-30.83 


-24.81 


-18.79 


-12.77 


-6.75 


-0.73 


5 


-48.28 


-36.44 


-30.42 


-24.40 


-18.38 


-12.36 


-6.34 


-0.32 


6 


-46.83 


-36.05 


-30.03 


-24.00 


-17.98 


-11.96 


-5.94 


+0.08 


7 


-45.59 


-35.67 


-29.65 


-23.63 


-17.61 


-11.59 


-5.57 


+0.46 


B 


-44.50 


-35.31 


-29.29 


-23.27 


-17.24 


-11.22 


-5.20 


+0.82 


9 


-43.54 


-34.96 


-28.94 


-22.92 


-16.90 


-10.88 


-4.86 


+ 1.16 


10 


-42.67 


-34.62 


-28.60 


-22.58 


-16.56 


-10.54 


-4.52 


+ 1.50 


11 


-41.88 


-34.30 


-28.28 


-22.26 


-16.24 


-10.22 


-4.20 


+ 1.82 


12 


-41.15 


-33.99 


-27.97 


-21.95 


-15.93 


-9.91 


-3.89 


+2.13 


13 


-40.48 


-33.69 


-27.67 


-21 .65 


-15.63 


-9.61 


-3.59 


+2.43 


14 


-39.86 


-33.40 


-27.38 


-21.36 


-15.34 


-9.32 


-3.30 


+2.72 


15 


-39.28 


-33.12 


-27.10 


-21.08 


- 1 5.06 


-9.04 


-3.02 


+3.00 



The -40dBmo, -50dBmo, and -55dBmo output points significant for the CCITT A-87.6 PCM system 
specification can be found between steps 13 and 14 on chord 0, steps 4 and 5 on chord 0, and steps 2 and 
3 on chord 0, respectively. Outputs corresponding to points below -55dBmo are specified in Table 1 for 
an accuracy of ± a half step. 



3-66 



Am6073 



THEORY OF OPERATION 

Functional Description 

The Am6073 is an 8-bit, nonlinear, digital-to-analog conver- 
ter with high impedance current outputs. The output current 
value is proportional to the product of the digital inputs and 
the input reference current. The full scale output current, Ips. 
is specified by the input binary code 111 1111, and is a linear 
function of the reference current, l R £ F . There are two operat- 
ing modes, encode and decode, which are controlled by the 
Encode/Decode, (E/D), input signal. A logic 1 applied to the 
E/D input places the Am6073 in the encode mode and current 
will flow into the Ioe(+) ° r Ioeh output, depending on the 
state of the Sign Bit (SB) input. A logic at the E/D input 
places the Am6073 in the decode mode. 

The transfer characteristic is a piece-wise linear approxima- 
tion to the CCITT A-87.6 logarithmic law which can be written 
as follows: 

Y = 0.18 (1 + In (A |X| )) sgn (X), 1/A m. |X| « 1 

Y = 0.18(AlX|)sgn(X), s |X| s 1/A 

where: X = analog signal level normalized to unity 
(encoder input or decoder output) 
Y = digital signal level normalized to unity 

(encoder output or decoder input) 
A = 87.6 

The current flows from the external circuit into one of four 
possible analog outputs determined by the SB and E/D in- 
puts. The output current transfer function can be represented 
by a total of 16 segments or chords addressable through the 
SB input and three chord select bits. The two chords closest 
to the origin of the transfer function, chord and chord 1, are 
made colinear and contiguous. The beginning of chord 0, 
specified by the input binary code 000 0000, is offset by 
+0.5fiA. Each chord can be further divided into 16 steps, all 
of the same size. The step size changes from one chord to 
another, with the smallest step of 1.0(iA found in the first two 
chords near zero output current, and the largest step of 64/iA 
found in the last chord near full scale output current. This 
nonlinear feature provides exceptional accuracy for small 
signal levels. The accuracy for signal amplitudes corres- 



ponding to chords and 1 is very close to that of an 11-bit 
linear, binary D/A converter. The ratio (in dB) between the 
chord endpoint current, (Step 15), and the current which 
corresponds to the preceding step, (Step 14), is maintained 
at about 0.3dB over the entire dynamic range, with the excep- 
tion of chord 0. The difference between the ratios of full scale 
current to chord endpoint currents of adjacent chords is 
similarly maintained at 6dB over the entire dynamic range. 
Resulting signal-to-quantizing distortions due to non- 
uniform quantizing levels maintain an acceptably low value 
overa40dB range of input speech signals. Notethatthe62dB 
output dynamic range for the Am6073 is very close to the 
dynamic range of a sign plus 1 1-bit linear, binary D/A conver- 
ter. 

In order to achieve a smoother transition between adjacent 
chords, the step size between these chord end points is equal 
to 1.5 times the step size of the lower chord. Note that this 
does not apply to chord and chord 1 where adjacent end 
points differ by only one step, because these two chords are 
colinear and have the same step sizes. Monotonic operation 
is guaranteed by the internal device design over the entire 
output dynamic range by specifying and maintaining the 
chord end points and step size deviations within the allow- 
able limits. 

Operating Modes 

The basic converter function is conversion of digital input 
data into a corresponding analog current signal, i.e., the 
basic function is digital-to-analog decoding. The basic de- 
coder connection for a sign plus 7-bit input configuration is 
shown in Figure 1. The corresponding dynamic range is 
62dB, and input-output characteristics conform to the stan- 
dard decoder transfer function with output current values 
specified in Table 1. The E/D input enables switching be- 
tween the encode, Ioe(+) or 'oe(-)> anc l * ne decode, Iod(+) or 
'od(-)' outputs. Atypical encode/decode test circuit is shown 
in Figure 2. This circuit is used for output current measure- 
ments. When the E/D input is high, (a logic 1), the converter 
will assume the encode operating mode and the output cur- 
rent will flow into one of the I e outputs (as determined by 
the SB input). When operating in the encode mode as shown 



DIGITAL INPUTS 



B, ^ a, B, B 3 B 2 B, SB E/0 ^> 





!rEF = V BEF' R REF 

IDEAL VALUES: I REF = 512»iA, IpS = 2016mA 





E/D 


SB 


B1 


B 2 


B 3 


B 4 


B5 


Be 


B 7 


Eo 


POSITIVE FULL SCALE 







i 


1 


1 


1 


1 


i 


l 


5.O40V 


f+) ZERO SCALE +1 STEP 





1 






















0.O04V 


( + 1 ZERO SCALE 

























0.0012V 


(-) ZERO SCALE 




















~0 








-0.001 2V 


(_] 7EHO SCALE -ij STEP 


o 
























u.uo4v 


NEGATIVE FULL SCALE 





o 


i 


1 


1 


1 


1 


1 


I 


-5.040V 



Figure 1. Detailed Decoder Connections. 




R 1 = R 2 = R 3 = R 4 =2.5kS2 ±0.1% 



LINE SELECTION TABLE 



TEST 






OUTPUT 


GROUP 


E/D 


SB 


MEASUREMENT 


1 


1 


1 


l E < + > 


(Eqi/R,) 


2 


1 





lOE 


.E ,/n 2 l 


3 


o 


1 


'OD M 


(E 02 /R 3 . 


4 








'oo H 


IE 02 m 4 ) 



Figure 2. Output Current DC Test Circuit. 



Am6073 



in Figure 3, an offset current equal to a half step in each chord 
is required to obtain the correct encoder transfer characteris- 
tic. Since the size of this step varies from one chord to 
another, it cannot easily be added externally. As indicated in 
the block diagram this required half step of encode current, 
l EN , is automatically added to the l 0E output through the 
internal chip design. This additional current will, for exam- 
ple, make the ideal full scale current in the encode mode 
larger than the same current in the decode mode by 32^A. 
Similarly, the current levels in the first chord near the origin 
will be offset by 0.5juA, which will bring the ideal encode 
current value for step on chord to ± 1 .OjxA with respect to 
the corresponding decode current value of 0.5/iA. This addi- 
tional encode half step of current can be used for extension 
of the output dynamic range from 62dB to 66dB, when the 
converter is performing only the decode function. The cor- 
responding decoder connection utilizes the E/D input as a 
ninth digital input and has the outputs Iod(+) and 'oei-h and 
the outputs Iod(-) and 'oe(-) tied together, respectively. 
When encoding or compression of an analog signal is re- 
quired, the Am6072 can be used together with a Successive 
Approximation Register (SAR), comparator, and additional 
SSI logic elements to perform the AD data conversion, as 
shown in Figure 3. The encoder transfer function, shown on 
page 1 , characterizes this AID converter system. The first task 
of this system is to determine the polarity of the incoming 
analog signal and to generat e _a corr esponding SB input 
value. W hen the proper START, (S), and CONVERSION COM- 
PLETE, (CC), signal levels are set, the first clock pulse sets 
the MSB output of the SAR, Am2502, to a logic and sets all 
other parallel digital outputs to logic 1 levels. At the same 
time, the flip-flop is triggered, and its output provides the E/D 
input with a logic level. No current flows into the l 0E out- 
puts. This disconnects the converter from the comparator 
inputs, and the incoming analog signal can be compared 
with the ground applied to the opposite comparator input. 
The resulting comparator output is fed to the Am2502 serial 
data input, D, through an exclusive-or gate. At the same time, 
the second input to the same exclusive-or gate is held at a 
logic level by the additional successive approximation 
logic shown in Figure 3. This exclusive-or gate inverts the 
comparator's outputs whenever a negative signal polarity is 
detected. This maintains the proper output current coding, 
i.e., all ones for full scale and all zeros for zero scale. 



The second clock pulse changes the E/D input back to a logic 
1 level because the CC signal changed. It also clocks the D 
input signal of the Am2502 to its MSB output, and transfers it 
to the SB input of the Am6073. Depending upon the SB input 
level, current will flow into the Ioe(+) or 'oe(-) output of the 
Am6073. 

Nine clock pulses are required to obtain a digital binary 
representation of the incoming analog signal at the eight 
Am2502 digital outputs. The resulting Am6073 analog out- 
put signal is compared with the analog input signal after 
each of the nine successive clock pulses. The analog signal 
should not be allowed to change its value during the data 
conversion time. In high speed systems, fast changes of the 
analog signals at the AID system input are usually prevented 
by using sample and hold circuitry. 



Additional Considerations and Recommendations 

In Figure 1, an optional operational amplifier converts the 
Am6073 output current to a bipolar voltage output. When the 
SB input is a logic 1, sink current appears at the amplifier's 
negative input, and the amplifier acts as a current to voltage 
converter, yielding a positive voltage output. With the SB 
value at a logic O. sink current appears at the amplifier's 
positive input. The amplifier behaves as a voltage follower, 
and the true current outputs will swing below ground with 
essentially no change in output current. The SB input steers 
current into the appropriate ( + ) or (-) output of the Am6073. 
The resulting operational amplifier's output in Figure 1 
should ideally be symmetrical with resistors R1 and R2 
matched. 

In Figure 2, two operational amplifiers measure the currents 
of each of the four Am6073 analog outputs. Resistor toler- 
ances of 0.1% give 0.1 % output measurement error (approx- 
imately 2(xA at full scale). The input offset currents of the A1 
and A2 devices also increase output measurement error and 
this error is most significant near zero scale. The Am101A 
and 308 devices, for example, may be used for A1 and A2 
since their maximum offset currents, which would add di- 
rectly to the measurement error, are only 10nA and 1nA 
respectively. The input offset voltages of the A1 and A2 
devices, with output resistor values of 2.5kn, also contribute 
to the output measurement error by a factor of 400nA for 



ANALOG INPUT 



(GROUNDED FOR 

SINGLE-ENDED | 

INPUTS) 




CLOCK START +5.0V 



J 



1 



SERIAL 

DATA 

OUTPUT 




1 2 3 4 5 6 



1 



> PARALLEL 
DATA 
OUTPUT 



E/D SB B, B 2 B 3 B 4 B 5 B 6 B-, 



Figure 3. Detailed Encoder Connections. 



3-68 



Am6073 



every mV of offset at the A1 and A2 outputs. Therefore, to 
minimize error, the offset voltages of A1 and A2 should be 
nulled. 

The recommended operating range for the reference current 
Iref is from 0.1mA to 1.0mA. The full scale output current, 
l FS , is a linear function of the reference current, and may be 
calculated from the equation l FS = 3.94 l REF . This tight re- 
lationship between l REF and l FS alleviates the requirement 
for trimming the l REF current if the R REF resistor values 
are within ±1% of the calculated value. Lower values of 
l REF will reduce the negative power supply current, (I-), 
and will increase the reference amplifier negative com- 
mon mode input voltage range. 

The ideal value for the reference current l REF = V REF /R REF is 
512ju.A. The corresponding ideal full scale decode and en- 
code current values are 2016mA and 2048>A, respectively. A 
percentage change from the ideal l REF value produced by 
changes in V REF or R REF values produces the same percen- 
tage change in decode and encode output current values. 
The positive voltage supply, V+, may be used, with certain 
precautions, for the positive reference voltage V REF . In this 
case, the reference resistor R REF(+) should be split into two 
resistors and their junction bypassed to ground with a 
capacitor of 0.01/j.F- The total resistor value should provide 
the reference current l REF = 512^A. The resistor R REF( _) 
value should be approximately equal to the R REF(+) value in 
order to compensate for the errors caused by the reference 
amplifier's input offset current. 

An alternative to the positive reference voltage applications 
shown in Figures 1, 2 and 3 is the application of a negative 
voltage to the V R (_j terminal through the resistor R REF (_) 
with the R REF(+ ) resistor tied to ground. The advantage of 
this arrangement is the presence of very high impedance at 
the V R( _) terminal while the reference current flows from 
ground through R REF(+i into the V R(+) terminal. 

The Am6073 has a wide output voltage compliance suitable 
for driving a variety of loads. With l REF = 512/xA and V- = 
-15V, positive voltage compliance is +18V and negative 



voltage compliance is -5.0V. For other values of l REF and 
V-, the negative voltage compliance, V oc( _), may be calcu- 
lated as follows: 

Voc(-) = (V-) + 2(l REF .1.55kn) + 8.4V, 
where 1 .55kfi and 8.4V are equivalent worst case values for 
the Am6073. 

The following table contains V c<-) values for some specific 
V-, l REF , and l F s values. 

Negative Output Voltage Compliance VqC( — ) 





'ref "fs 1 


V- 


256/xA 
(1mA) 


512 M A 
(2mA) 


1024 M A 
(4mA) 


-12V 


-2.8V 


-2.0V 


-0.4V 


-15V 


-5.8V 


-5.0V 


-3.4V 


-18V 


-8.8V 


-8.0V 


-6.4V 



The V LC input can accommodate various logic input switch- 
ing threshold voltages allowing the Am6073 to interface with 
various logic families. This input should be placed at a poten- 
tial which is 1.4V below the desired logic input switching 
threshold. Two external discrete circuits which provide this 
function for non-TTL driven inputs are shown in Figure4. For 
TTL-driven logic inputs, the V LC input should be grounded. If 
negative voltages are applied at the digital logic inputs, they 
must have a value which is more positive than the sum of the 
chosen V- value and +10V. 

With a V- value chosen between -15V and -11V, the 
Vqc(-)/ the mput reference common mode voltage range, 
and the logic input negative voltage range are reduced by an 
amount equivalent to the difference between -15V and the 
V- value chosen. 

With a V+ value chosen between +5V and +15V, the refer- 
ence amplifier common mode positive voltage range and the 
V L c input values are reduced by an amount equivalent to the 
difference between +15V and the V+ value chosen. 



ECL 



CMOS, HTL, NMOS 




(See Notes 2 and 31 

Figure 4. Interfacing Circuits for ECL, CMOS, HTL, 
and NMOS Logic Inputs. 



DIGITAL INPUTS 




— -15V 



| 13 plS | 10 



INPUT CODE 
(E/D.SB, B-) B 7 ) 


OUTPUT VOLTAGE (V) 


"A" 


"B" 


"C" 


DIFF 


10 111 1111 
10 110 11 11 
10 000 0000 




+5.00 
♦10.00 


N/A 


N/A 


N/A 


01 111 1111 




-5.00 


+5.00 


-10.00 


01 110 1111 




+0.00 


+5.00 


-5.00 


01 000 0000 




+5.00 


+5.00 







N/A 








00 000 0000 




+5.00 


+5.00 





00 1 1 1 1 1 1 




+5.00 


+0.00 


+5.00 


00 11 1 1111 




+5.00 


-5.00 


+ 10,00 



Figure 5. Resistive Output Connections. 



Notes: 2. Set the voltage "A" to the desired logic input switching threshold. 

3. Allowable range of logic threshold is typically — 5V to +13. 5V when operating the companding DAC on +15V supplies. 



3-69 



Am6073 



ADDITIONAL DECODE OUTPUT CURRENT TABLES 
Table 3 

Normalized Decoder Output (Sign Bit Excluded) 



STEP (S) 


CHORD (C) 





1 


2 


3 


4 


5 


6 


7 


TT7 

000 


^T. 

001 


— „-„ — 
010 


01 1 


100 


1 ni 


1 1U 


in 

ill 





0000 


1 


33 


66 


132 


264 


528 


1056 


2112 


1 


0001 


3 


35 


70 


140 


280 


560 


1120 


2240 


2 


0010 


5 


37 


74 


148 


296 


592 


1184 


2368 


3 


0011 


7 


39 


78 


156 


312 


624 


1248 


2496 


4 


0100 


9 


41 


82 


164 


328 


656 


1312 


2624 


5 


0101 


11 


43 


86 


172 


344 


688 


1376 


2752 


6 


0110 


13 


45 


90 


180 


360 


720 


1440 


2880 


7 


0111 


15 


47 


94 


188 


376 


752 


1504 


3008 


8 


1000 


17 


49 


98 


196 


392 


784 


1568 


3136 


9 


1001 


19 


51 


102 


204 


408 


816 


1632 


3264 


10 


1010 


21 


53 


106 


212 


424 


848 


1696 


3392 


11 


1011 


23 


55 


110 


220 


440 


880 


1760 


3520 


12 


1100 


25 


57 


114 


228 


456 


912 


1824 


3648 


13 


1101 


27 


59 


118 


236 


462 


944 


1888 


3776 


14 


1110 


29 


61 


122 


244 


488 


976 


1952 


3904 


15 


1111 


31 


63 


126 


252 


504 


1008 


2016 


4032 


STEP SIZE 


2 


2 


4 


8 


16 


32 


64 


128 



The normalized decode current, (l c .s). where C is chord number and S is step number, is calculated 
using: l cs = 2 C (S + 16.5) for C s 1,and l c ,s = 2S + 1 forC = 0. The ideal decode current, (l 0D ). in /xA is 
calculated using: I d = (lc,s' l 7,i5(norm.))' l Fs(/ iA ). where l c ,s is the corresponding normalized current. 
To obtain normalized encode values the corresponding normalized half-step value should be added to 
all entries in Table 3. 



Table 4 
Decoder Step Size Summary 











Step Size 


Step Size as 


Resolution 




Step Size 


Step Size 


Step Size 


in dB at 


a % of Reading 


& Accuracy 




Normalized 


in ixA with 


as a % of 


Chord 


at Chord 


of Equivalent 


Chord 


to Full Scale 


2016/xA F. S. 


Full Scale 


Endpoints 


Endpoints 


Binary DAC 





2 


1.0 


0.05% 


0.58 


6.45% 


Sign + 11 Bits 


1 


2 


1.0 


0.05% 


0.28 


3.17% 


Sign + 11 Bits 


2 


4 


2.0 


0.1% 


0.28 


3.17% 


Sign + 10 Bits 


3 


8 


4.0 


0.2% 


0.28 


3.17% 


Sign + 9 Bits 


4 


16 


8.0 


0.4% 


0.28 


3.17% 


Sign + 8 Bits 


5 


32 


16.0 


0.8% 


0.28 


3.17% 


Sign + 7 Bits 


6 


64 


32.0 


1.6% 


0.28 


3.17% 


Sign + 6 Bits 




128 


64.0 


3.2% 


0.28 


3.17% 


Sign + 5 Bits 



Table 5 

Decoder Chord Size Summary 



Chord 


Chord Endpoints 
Normalized 
to Full Scale 


Chord Endpoints 
in /nA with 
2016mA F. S. 


Chord Endpoints 
as a % 
of Full Scale 


Chord Endpoints 

in dB Down 
from Full Scale 





31 


15.5 


0.77% 


-42.28 


1 


63 


31.5 


1.56% 


-36.12 


2 


126 


63.0 


3.13% 


-30.10 


3 


252 


126.0 


6.25% 


-24.08 


4 


504 


252.0 


12.5% 


-18.06 


5 


1008 


504.0 


25.0% 


-12.04 


6 


2016 


1008.0 


50.0% 


-6.02 


7 

' 


4032 


2016.0 


ioo<;; 






3-70 



Am6073 



BASIC CIRCUIT CONNECTIONS 



±10V RANGE ENCODER/DECODER 
CONNECTIONS 



DIGITAL INPUTS 




— -15V *15V 



f — * tlOV 

I OUTPUT 

>2.5kn 



COMPLIANCE EXTENSION 
USING AC COUPLED OUTPUT 



V REF DIGITAL INPUTS 



B 7 B 6 Bg 6 4 B 3 B 2 Bf SB E/D (+; 



111 






' 0E [- 


'ref 




Am6073 




V R«-J 




«o * 








r 


V- 






<20k 


1 | 13 


| IB 


I" 




-12V 


♦12V 






IDEAL VALUES: 
l REF =512»iA 
I PS = 2016mA 



LOW INPUT IMPEDANCE CONNECTION 



HIGH INPUT IMPEDANCE CONNECTION 



DIGITAL INPUTS 



8 7 6 5 4 3 2 



DIGITAL INPUTS 



»; H H »4 >a >z »i SB H o Nf 

Am6073 

'ni-l 'od 
V- v+ v LC <- 

| 13 p8 j 10 

-1SV *1SV — 



IREF = V|n/B|N + V REF /R REF+ 
l FS N 4(I REF ) 

Rref- = [(Rref+)(RinH/(Rref+ + Rin> 








7 |s \b \a \ 


L 1* 


'ref 


B 6 Bg B 4 B 3 B 2 B, 

V RI*I 

Am6G73 


SB E/D (+ 
'OE | 


r ref- < 


•HI-) 

V- 




lOD 

*lc 


1" 




t 




-15V 


*1SV 



'REF " < V REF - V| N )/R REF+ 
l FS ■» 4(I REF ) 



LOGARITHMIC DIGITAL GAIN CONTROL 
(Notes 4, 5) 



REFERENCE AMPLIFIER DYNAMIC TEST CIRCUIT 



ATTENUATION 
= 6dB/CHORD CHANNEL 
= ,3dB/STEP SELECT 



20kfi ! 




9 \3 \7 \6 


5 I' p |? h 




11 




7 B 6 B 5 B 4 a 3 a 2 B l ss £/D (+n 


'REF 








,- 


"'-■^ Hh 

-5.0V 
INPUT 






Am6073 


12 






'OD 1 

V LC 




' 20kli 

'. 


13 


18 1 10 



-15V *15V 





Bj Be Bg B, B 3 B 2 B, SB E/O ,,,\ 







«- 




Am6073 




V R(-I 






V- 




V LC '"V 


1" 


|- 


i" 


-15V 


+16V 





OSCILLOSCOPE 



DISTORTION 
ANALYZER 
OUTPUT THO .001% 




■VvNi— j 



Notes: 4. Low distortion outputs are provided over 62dB range. 

5. Up to 4 channels of output may be selected by E/D and SB logic inputs. 



3-71 



Am6073 



TYPICAL PERFORMANCE CURVES 



Reference Amplifier 
Total Harmonic Distortion 
Versus Frequency (80kHz Filter) 
(Notes 6, 7, 8) 





1.0 


a? 






0.5 


2 




O 






0.2 


oc 




c 


0.1 




5 


0.05 


u 




z 


0.02 


c 






0.01 


< 




I 0.005 






< 






0.002 


5 




r- 


0.001 



LARGE SIGNAL 
INPUT +SV PEAK 
(50% MODULATION) 

100 1.0k 
FREQUENCY - 




Reference Amplifier 
Input Frequency Response 




LARGE SIGNAL 
ISLEW RATE LIMITED) 
5V PEAK 
(50% MODULATION) 

I I III I 



I III 



Ik 10k 100k 1M 10M 
FREQUENCY - Hi 



Reference Amplifier 
Input Common-Mode Range 
(Note 9) 



l REF - 0.5mA 



IrEF = 0.25mA- 
f 



-14 -10 -6 -2 2 6 10 14 18 
REFERENCE COMMON-MODE VOLTAGE 



Power Supply Currents 
Versus Power Supply Voltages 

8.0 r 



ALL BITS "HIGH" OR "LOW" 
IpS - 2.0mA 



2.0 4.0 6.0 8.0 10 12 14 16 18 20 
POSITIVE OR NEGATIVE POWER SUPPLY - ' 



Power Supply Currents 
Versus Temperature 



















1 




























































if; 


-2 


0m 


* 


































































- A 


LL 

V 


JITS 


"H 
15V 


GH 

, V 


of 


"L 

-15 


OW 

/ 







50 100 
TEMPERATURE — ~C 



Output Current Versus 
Output Voltage 
(Output Voltage Compliance) 



















1 




■f 


Ep - 1.0mA 


















'A " 'MIN "° MAX 
































IrEF « 0.5mA 




























EF r 


D.25 
















t 




















- - 

1 











-14 -10 -6 -2 2 6 10 14 18 
OUTPUT VOLTAGE -V 



Bit Transfer Characteristics 
{Note 10) 



0.35 
0.30 
0.25 
0.20 
0.15 
0.10 
0.05 



1 1 1 1 1 1 




















R 


EF " 










































































31 
































































































































V- =-15V 

. \ V— = 






































\l \ 
















32 — 


























33 










1 1 














; 







0.055 
0.023 



-12 -8 -4 



4 8 12 16 
LOGIC INPUT VOLTAGE - V 



Logic Input Current 
Versus Input Voltage 
and Logic Input Range 
(Note 11) 



I I 

- 'ref 


- 


I I 
).5mA 


















V- 




15V 






















L 


























































































I 























































































-12 -8 -4 



Output Full Scale Current 
Versus Reference Input Current 




LOGIC INPUT VOLTAGE - V 



0.5 1.0 
REFERENCE CURRENT. I REF - mA 



Notes: 6. THD is nearly independent of the logic input code. 

7. Similar results are obtained for a high input impedance connection using V R( _j as an input. 

8. Increased distortion above 50kHz is due to a slew rate limiting effect which determines the large signal bandwidth. For an input of ±2.5V peak (25% 
modulation), the bandwidth is 100kHz. 

9. Positive common mode range is always (V+) -1.5V. 

10. All bits are fully switched with less than a half step error at switching points which are guaranteed to lie between 0.8V and 2.0V over the operating 
temperature range. 

1 1 . The logic input voltage range is independent of the positive power supply and logic inputs may swing above the supply. 



3-72 



Am6073 




SINGLE CHANNEL PCM CODEC - PARALLEL DATA I/O 




APPLICATION INFORMATION 



1. To perform a transmit operation cycle the START pulse 
must be held low for one clock cycle; the receive opera- 
tion is performed without the successive approximation 
SAR. 

I RECEIVE command signals are mutually exclu- 

Duration of the RECEIVE command signal must 
accommodate the Am6073 settling time plus the sam- 
pling time required by the sample and hold, (S & H), 
circuit used at the CODEC'S analog output. The receiving 
d ata m ust not change during this time. 
A XMT command si gnal must be issued after a high-to- 
low transition of the CONVERSION COMPLETE, CC, sig- 
nal. Its duration depends on the time required by the 
digital time division switch circuitry to sample the 8-bit 
parallel transmit data bus. 

Data conversion for a transmit operation is completed in 9 
clock cycles because the SAR must be initialized before 



every new conversion. Data conversion for a receive op- 
eration corresponds to the Am6073 settling time; the re- 
ceiving and transmit data transfers can be done simul- 
taneously by employing separate transmit and receive 
data buses and utilizing data storage devices for the re- 
ceive data. 

A sample comm and puls e for a transmit operation can 
coincide with the START pulse; its duration depends on 
the sample and hold circuit used at the CODEC'S analog 
input. 

A sample command pulse for a receive operation must be 
delayed from a low-to-high transition of the RECEIVE 
command signal by an amount equal to the Am6073 set- 
tling time. Its termination can coincide with a high-to-low 
transition of the RECEIVE command signal. 
. The code assignment for outgoing or incoming parallel 
data provides uncomplemented binary values for sig- 
nal sign and magnitude. The data bus, as a result, 
yields "high zeros" density for small signal amplitudes. 



3-73 



Am6073 



TIME SHARED CONVERTER CONNECTIONS (Cont.) 



SINGLE CHANNEL PCM CODEC - SERIAL DATA I/O 




APPLICATION INFORMATION 

1. Be fore beg inning either a transmit or a receive operation, 
the START signal must be held low for one complete clock 
cycle. 

2. XMT and RECEIVE command signals are mutually exclu- 
sive. Their durations must accommodate the time required 
for conversion of an outgoing or an incoming series of 8 di- 
gital bits, respectively. 

3. Data conversion for either operation, transmit or receive, is 
completed in 9 clock cycles. 

4. During the receive cycle the successive approximation re- 
gister, SAR, is acting as a serial-in to parallel-out shift re- 



gister, with data supplied from data storage devices. 

5. A sample command pulse for a transmit cycle must be is- 
sued before a XMT command signal; its duration depends 
on the sample and hold, S & H, circuit used. 

6. A sample command pulse for a receive cycle must be de- 
layed by a time equal to the Am6073 settling time after a 
high-to-low transition of the CONVERSION COMPLETE, 
CC, signal occurs. 

7. The code assignment for outgoing or incoming parallel 
data provides uncomplemented binary values for sig- 
nal sign and magnitude. The data bus, as a result, 
yields "high zeros" density for small signal amplitudes. 



8 LINE CODEC TDM PCM/PABX SYSTEM - BLOCK DIAGRAM 




3-74 



Am6073 



CCITT A-LAW COMPANDOR TRACKING SPECIFICATION 























































CCITT A - 
SPECIFICA 

(MAXiMUfv 


AW 
TION 
1 




























































































































Am6073 
SPECIFICATION 
(MAXIMUM) 





























INPUT SIGNAL LEVEL - dBmo 



COMPANDOR TRACKING TEST BLOCK DIAGRAM 



© 

T 



(HP-200CD 
OSCILLATOR 
OR EQUIVALENT) 



ATTENUATOR 



ENCODER 
{Am6073l 




(PCMI 


DECC 
(Ami 


DER 
1073) 



© 



(HP-400D 
VOLTMETER 
OR EQUIVALENT) 



CCITT NOISE AND DISTORTION SPECIFICATION 

The Am6073 has a negligible idle channel noise contribution. Signal-to-quantizing-distortion ratio, (S/D), 
is guaranteed to exceed the minimum values specified for PCM channels at audio frequencies as 
follows: 



Input Level 1020 Hz Sinewave 


S/D, C Message Weighting 


to -30 dBmo 
At -40 dBmo 
At -45 dBmo 


33 dB 
27 dB 
22 dB 



Metallization and Pad Layout 




80 X 114 Mils 



3-75 



Am6080 

Microprocessor System Compatible 8-Bit High Speed Multiplying D/A Converter 



DISTINCTIVE CHARACTERISTICS 

• 8-Bit D/A with 8-Bit input data latch 

• Compatible with most popular microprocessors including the 
Am9080A-4 and the Am2900 

• Write, Chip Select and Data Enable logic on chip 

• DAC appears as memory location to microprocessor 

• MSB inversion under logic control 

• Differential current output 

• Choice of 6 coding 1 



• Fast settling current output -160ns 

• Nonlinearity to ±0.1% max over temperature range 

• Full scale current pre-matched to ±1 LSB 

• High output impedance and voltage compliance 

• Low full scale current drift - ±5ppm/°C 

• Wide range multiplying capability -2.0MHz bandwidth 

• Direct interface to TTL, CMOS, NMOS 

• High speed data latch - 80ns min write time 



GENERAL DESCRIPTION 

The Am6080 is a monolithic 8-bit multiplying Digital-to-Analog 
converter with an 8-bit data latch, chip select and other control 
signal lines which allow direct interface with microprocessor 
buses. 

The converter allows a choice of 6 different coding formats. The 
most significant bit (D 7 ) can be inverted or non-inverted under the 
control of the code select input. The code control also provides a 
zero differential current output for 2's complement coding. A high 
voltage compliance, complementary current output pair is pro- 
vided. The data latch is very high speed which makes the 
Am6080 capable of interfacing with high speed microprocessors. 

Monotonic multiplying performance is maintained over a more 
than 40 to 1 reference current range. Matching within ±1 LSB 



between reference and full scale current eliminates the need for 
full scale trimming in most applications. 

The Am6080 guarantees full 8-bit monotonicity. Nonlinearities as 
tight as 0.1% over the entire operating temperature range are 
available. Device performance is essentially unchanged over the 
full power supply voltage and temperature range. 

Applications for the Am6080 include microprocessor compatible 
data acquisition systems and data distribution systems, 8-bit A/D 
converters, servo-motor and pen drivers, waveform generators, 
programmable attenuators, analog meter drivers, programmable 
power supplies, CRT display drivers and high speed modems. 



EQUIVALENT CIRCUIT 



LSB MSB CODE 

D Dt D 2 D 3 D 4 D 5 D 6 Dy SEL V+ 

o o o o o o o 




CONNECTION DIAGRAM 
Top View 



CODE SELECT 1 Q 


CODE S 


EL V + 


□ 20 POSITIVE POWER SUPPLY 


(MSB) D 7 INPUT 2 Q 


°7 


k> 


2] 19 OUTPUT 


D 6 INPUT 3 \Z 


°6 


■o 


^ 18 OUTPUT 


D 5 INPUT 4 


D 5 A(| 


V- 


17 NEGATIVE POWER SUPPLY 


D 4 INPUT 5 □ 


°4 


COMP 


□ 16 COMPENSATION 


D 3 INPUT 6 Q 


D - 


V REF(-) 


2] 15 NEGATIVE REFERENCE 


D 2 INPUT 7 


D 2 


VREF(+) 


2\ 14 POSITIVE REFERENCE 


Df INPUT 8 Q 


Dl 


DE 


13 DATA LATCH ENABLE 


(LSB) D INPUT 9 Q 


D 


W 


2\ 12 WRITE 


GND 10 □ 


GND 


CS 


□ 11 CHIP SELECT 



Pin 1 marked for orientation. 



ORDERING INFORMATION 



Package 
Type 


Temperature 
Range 


Nonlinearity 


Order 
Number 


Hermetic 
DIP 


-55°Cto +125°C 


.1% 
.19% 


Am6080ADM 
Am6080DM 


Hermetic 
DIP 


0°C to +70°C 


.1% 
.19% 


Am6080ADC 
Am6080DC 


Molded 
DIP 


.1% 
.19% 


Am6080APC 
Am6080PC 



3-76 



Am6080 

MAXIMUM RATINGS 



Operating Temperature 





Power Supply Voltage 


±18V 


Am6080ADM, Am6080DM 


-55°C to +125°C 


Logic Inputs 


-5Vto +18V 


Am6080ADC, Am6080DC 


0°C to +70°C 


Analog Current Outputs 


-12V to +18V 


Am6080APC, Am6080PC 


Reference Inputs (V 14 V 15 ) 


V- to V+ 


Storage Temperature 


-65°Cto +150°C 


Reference Input Differential Voltage (V 14 to V 15 ) 


±18V 


Lead Temperature (Soldering, 60 sec) 


300°C 


Reference Input Current (l 14 ) 


1.25mA 



ELECTRICAL CHARACTERISTICS 

These specifications apply for V + = +5V, V_ = -15V, l REF = 0.5mA, over the operating temperature range unless otherwise specified. 
Output characteristics refer to all outputs. 



Am6080A Am6080 
Parameter Description Conditions Min. Typ. Max. Min. Typ. Max. Unit 





Resolution 




8 


8 


8 


8 


8 


8 


bits 




Monotonicity 




8 


8 


8 


8 


8 


8 


bits 


D.N.L. 


Differential 
Nonlinearity 




- 


- 


±0.19 


- 


- 


±0.39 


%FS 


N.L. 


Nonlinearity 




- 


- 


±0.1 


- 


- 


±0.19 


%FS 


Ifs 


Full Scale Current 


Vrpp = 10.000V 

Htr * 

R14 = R15 = 20.000kn 
T A = 25°C 


1.984 


1.992 


2.000 


1.976 


1.992 


2.008 


mA 


TCI FS 


Full Scale Tempco 




— 


±5 


±20 


— 


±10 


±40 


ppm/°C 




.0005 


±.002 


— 


.001 


±.004 


%FS/°C 


v OC 


Output Voltage 
Compliance 




-10 




+ 18 


-10 


_ 


+ 18 


Volts 


!fss 


Full Scale 
Symmetry 


'fsi - 'fsi 


- 


-01 


±1.0 


- 


±0.2 


±2.0 


MA 


!zs 


Zero Scale Current 






0.01 


0.4 




0.01 


0.8 


mA 


'RR 


Reference Current 
Range 


V- = -5V 





0.5 


0.55 





0.5 


0.55 


mA 


V— — —15V 





0.5 


1 .1 





0.5 


1.1 


V|L 


Logic 
Input 
Levels 


Logic "0" 








0.8 






0.8 


Volts 


V| H 


Logic "1" 




2.0 






2.0 






1... 

'in 


Logic Input Current 


Vjn — OV TO + 10V 






40 






40 




Vis 


Logic Input Swing 


V- = -15V 


-5 




+ 18 


-5 




+ 18 


Volts 


ht 


Reference Bias 
Current 






-0.5 


-2.0 




-0.5 


-2.0 


mA 


dl/dt 


Reference Input 
Slew Rate 


R 14(EQ) = 800fi 
CC = OpF 


4.0 


8.0 




4.0 


8.0 




mA/ius 


PSSI FS+ 


Power Supply 
Sensitivity 


V+ = +4.5V to +5.5V, V- = -15V 
V- = -13.5V to - 16.5V, V+ = +5V 




±0.0003 


±0.01 




±0.0005 


±0.01 


%FS 


PSSI FS _ 




±0.0005 


±0.01 




±0.0005 


+0.01 


V+ 


Power Supply 
Range 


'ref = 0.5mA, V 0uT = 0V 


4.5 




18 


4.5 




18 


Volts 


V- 


-18 




-4.5 


-18 




-4.5 


1+ 


Power Supply 
Current 


V+ = +5V, V- = -5V 




9.8 


14.7 




9.8 


14.7 


mA 


1- 




-7.4 


-9.9 




-7.4 


-9.9 


1+ 


V+ = + 5V, V- = -15V 




9.8 


14.7 




9.8 


14.7 


1- 




-7.4 


-9.9 




-7.4 


-9.9 


1+ 


V+ = +15V, V- = -15V 




9.8 


14.7 




9.8 


14.7 


1- 




-7.4 


-9.9 




-7.4 


-9.9 


Po 


Power 
Dissipation 


V+ = +5V, V- = -5V 




86 


123 




86 


123 


mW 


V+ = +5V, V- = -15V 




160 


222 




160 


222 


V+ = +15V, V- = -15V 




258 


369 




258 


369 



3-77 



Am6080 FUNCTIONAL PIN DESCRIPTION 

Symbol Function 

D -D 7 D -D 7 are the input bits 1-8 to the input data latch. 

Data is transferred to the data latch when CS, DE, 
and W are active and is latched when any of the 
enable signals go inactive. 

CS Chip Select - This active low input signal enables 
the Am6080. Writing into the data latch occurs only 
when the device is selected. 

W Write - This active low control signal enables the 
data latch when the CS and DE inputs are active. 



DE Data Latch Enable - This active l ow input _is used 
to enable the data latch. The CS, DE, and W must 
be active in order to write into the data latch. 

CODE Code Select - When CODE SEL = 0, the MSB (D 7 ) is 
SEL inverted and 1 LSB balance current is added to the 
l output. 

Vp EF ( + ) Positive and negative reference voltage to the ref- 
Vp£p(_) erence bias amplifier. These differential inputs allow 
the use of positive, negative and bipolar references. 

COMP Compensation - Frequency compensating terminal 
for the reference amplifier. 

'o 'o These are high impedance complementary current out- 
puts. The sum of these currents is always equal to l FS 



FUNCTION TABLES 



DATA LATCH CONTROL 
CS W DE Data Latch 












Transparent 


X 


X 


1 


Latched 


X 


1 


X 


Latched 


1 


X 


X 


Latched 



CODE 
SEL 



CODE SELECT 



Function 






MSB Inverted (Note 1) 


1 


MSB Non-inverted 



Don't Care 



Note 1 . LSB balance current is added to the l output. 



AC CHARACTERISTICS 

V + = +5V, V_ = -15V, l REF = 0.5mA, R L < 500ii, C L < 15pF over the operating temperature range unless otherwise specified 











Commercial 
Temp. Grades 


Military 
Temp. Grac 


les 




Parameter 


Description 


Conditions 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Unit 




Settling Time, All Bits Switched 


T A = 25°C 
Settling to ±'/ 2 LSB 




160 






160 




ns 


( PLH 


Propagation 


Each bit 


T A = 25"C 




80 


160 




80 


160 


ns 


•PHL 


Delay 


All bits switched 


50% to 50% 




80 


160 




80 


160 


( DH 


Data Hold Time 


See timing diagram 


10 


-30 




10 


-30 




ns 


'ds 


Data Set Up Time 


See timing diagram 


80 


35 




100 


35 




ns 


tow 


Data Write Time 


See timing diagram 


80 


35 




100 


35 




ns 



Notes: 1 . t DW is the overlap of W low, CS low, and DE low. All three signals must be low to enable the latch. Any signal going inactive latches the data. 

2. t s is measured with the latches open from the time the data becomes stable on the inputs to the time when the outputs are settled to within 
±1/2 LSB. All bits switched on or off. 

3. The internal time delays from CS, W and DE inputs to the enabling of the latches are all equal. 



(NOTES 1, 3) 



DATA 

(D0-O7I 



(NOTE 2) : 



TIMING DIAGRAM 



1 / 



XXXXXX^- 



DATA IN STABLE 



xxxxxxxxxx 













3-78 



Am6080 



APPLICATION HINTS: 

1. Reference current and reference resistor. 

There is a 1 to 4 scale up between the reference current (l REF ) 
and the full scale output current (l FS ). If V REF = +1 OV and l FS 
= 2mA, the value of the R 14 is: 



R-14 -- 



4 x 10 Volt 



2mA 



20K(1 



COMP 

V REF< + ) 




2. Reference amplifier compensation. 

For AC reference applications, a minimum value compensa- 
tion capacitor (C c ) is normally used. The value of this 
capacitor depends on R 15 . The minimum values to maximize 
bandwidth without oscillation are as follows: 

Reference Amplifier 
Frequency Response 



Table 2 
Compensation Capacitor 
(l FS = 2mA, l REF = 0.5mA) 



REF (■«") 


C C (PF) 


20 


100 


10 


50 


5 


25 


2 


10 


1 


5 


.5 






8 

i 



"REF (EO) - 2kn 
- C c - 10pF 



LARGE SIGNAL -50', 
MODULATION OF 2mA 
FULL SCALE CURRENT 

I III I III 



SMALL SIGNAL ±\% 
MODULATION OF 2mA 
FULL SCALE CURRENT 

I II I L_LL 




0.1 1.0 
FREQUENCY - MHz 



A 0.01 ixF capacitor is recommended for the fixed reference operation. 



Output Voltage 
Compliance 

ALL BITS ON 







































15V 






REF ta 0.5mA 












5V 














- | R 


EF 


0.25mA 


I- 




"I 













































-14 -10 -6 -2 2 6 10 14 18 
OUTPUT VOLTAGE - VOLTS 



Reference Amplifier Biasing 




Reference Configuration 


R 14 


R15 


V- 

R IN 


c c 


■ref 


Positive Reference 


Vr + 


OV 


N/C 


.01 /xF 


V R+ /R14 


Negative Reference 


ov 


Vr- 


N/C 


.01 nF 


-V R -/R,4 


Lo Impedance Bipolar 
Reference 


Vr+ 


ov 


V,N 


(Note 1) 


(V R+ /R 14 ) + (V IN /R IN ) 
(Note 2) 


Hi Impedance Bipolar 
Reference 


Vr+ 


V|N 


N/C 


(Note 1) 


(V R+ - V IN )/R 14 
(Note 3) 


Pulsed Reference (Note 4) 


Vr+ 


OV 


v, N 


No 
Cap 


(V R+ /R 14 ) + (V IN /R IN ) 



Notes: 1. The compensation capacitor is a function of the impedance seen at the +V REF input and must be at least C = 5pFX Ri4( eg | in 
kfl. For R 14 < 80011 no capacitor is necessary. 

2. For negative values of V|n, V R+ /R-j4 must be greater than -V (N Max/R JN so that the amplifier is not turned off. 

3. For positive values of V| N , V R+ must be greater than V| N Max so the amplifier is not turned off. 

4. For pulsed operation, V R+ provides a DC offset and may be set to zero in some cases. The impedance at pin 1 4 should be 800U or less 
and an additional resistor may be connected from pin 1 4 to ground to lower the impedance. 




Do 




V UT 



CODE FORMAT 



CODE 
SEL 



CONNECTIONS 



OUTPUT SCALE 



OUT MSB LSB 
SEL D7 D6 DS D4 D3 D2 D1 DO 



(mA) 



(mA) 



Straight binary: one 
polarity with true input 
code, true zero output. 



a-c 
b-e 



Positive full scale 
Positive full scale - LSB 
Zero scale 



X 11111111 
X 11111110 
X 000000 



1.992 
1.984 
.000 



9.960 
9.920 
.000 



Complementary binary: 
one polarity with 
complementary input 
code, true zero output. 



Positive full scale 
Positive full scale 
Zero scale 



X 000000 
X 000000 1 
X 11111111 



1.992 
1.984 
.000 



9.960 
9.920 
.000 



Straight offset binary: 
offset half scale, 
symmetrical about zero, 
no true zero output. 



LSB 



a-c 
b-d 



Positive full scale 
Positive full scale 
( + } Zero scale 
(-) Zero scale 
Negative full scale - LSB 
Negative full scale 



1.992 
1.984 
1.000 
.992 
.008 
.000 



.000 
.008 
.992 
1.000 
1.984 
1.992 



9.880 
.040 

-.040 
-9.880 
-9.960 



1 s complement: 
offset half scale, 
symmetrical about zero, 
no true zero output 



LSB 



(Note 1 



a-c 
b-d 



(need inverter at D 7 ) 



Positive full scale 
Positive full scale 
( + ) Zero scale 
(-) Zero scale 
Negative full scale - LSB 
Negative full scale 



1.992 
1.984 
1.000 
.992 
.008 
.000 



.000 
.008 
.992 
1.000 
1.984 
1.992 



9.960 
9.980 
.040 
-.040 
-9.880 
-9.960 



OFFSET 
WITH 
TRUE 
ZERO 



Offset binary: 
offset half scale, 
true zero output 
MSB complemented 
remainder add to l . 
(need inverter at D 7 ) 



LSB 





(Note 1) 



a-c 
b-d 



Positive full scale 
Positive full scale 
+ LSB 
Zero scale 
- LSB 

Negative full scale + LSB 
Negative full scale 



1.992 
1.984 
1.008 
1.000 
1.992 
.008 
.000 



.008 
.016 
.992 
1.000 
1.008 
1.992 
2.000 



9.920 
9.840 
080 
.000 
080 
-9.920 
10.000 



2's complement: 
offset half scale 
true zero output 
MSB complemented. 



a-c 
b-d 



Positive full scale 
Positive full scale - LSB 
+ 1 LSB 
Zero scale 
-1 LSB 

Negative full scale + LSB 
Negative full scale 



1111 



1.992 
1.984 
1.008 
1.000 
.992 
.008 
.000 



.008 
.016 
.992 
1.000 
1.008 
1.992 
2.000 



9.920 
9.840 
.080 
.000 
-.080 
-9.920 
10.000 



Note 1 : An external inverter is necessary since the code select inverts the MSB and adds a 1 LSB balance current to \q. Only one of these features is 
desired for this code. 

ADDITIONAL CODE MODIFICATIONS 

1 . Any of the offset binary codes may be complemented by reversing the output terminal pair. 



3-80 



Am6080 



A 0' A 15 



D -D 7 



Am90B0A 
SYSTEM 



SYSTEM APPLICATIONS 

Am9080A DATA SYSTEM 



CHIP 
SELECT 
DECODER 



0> 




WRITING DATA INTO THE Am6080 (2's Complement) 

PORT 1 :EQU OOH OUTPUT PORT ADDRESS 

MOV A, M :GET DATA FROM MEMORY 

OUT PORT1 :SEND DATA 



Am2900 DATA SYSTEM: MULTIPLE ANALOG INPUTS 



COM 
REG 
Am25 


WAND 
STER 
LS374 




'. 




n PROGRAM 
SEQUENCER 
(2) Am291 1 


i, 


8 


CONTROL STORAGE 
(6) Am27S11 
256 x 24 PROM 




'* 

24 


INSTRUCTION PIPELINE 
REGISTER 



OTHER 
CONTROL 



DATA BUS 



i INSTRUCTION 
DECODER 
Am29811A 



CODE D -D 7 
SEL 



DE 

T 



-O w 
-O cs 



CODE D -D 7 
SEL 




DACK 
IACK 
EOP 
• ROY 



- D„-D 7 



- D -O 7 



3-81 



ANALOG/DIGITAL CONVERTER UNDER 
SOFTWARE CONTROL 




LIC-071 



Am9080A SOFTWARE FOR A/D CONVERSION USING Am6080. 



SEQ SOURCE STATEMENT 

P0RT1 EQU 00H ;6080 A/0 PORT ADDRESS 

1 P0RT3 EQU 02H ;C0MPARAT0R ADDRESS 

2 ORG 3E50H 

3 START: LXI SP.STAKS-16 ;INITIAL STAKS POINTER 

4 SAMPLE: CALL ADCON ;CALL A/D CONVERSATION 

5 JMP SAMPLE ;NEXT SAMPLE 

6 ADCON: XRA A :CLEAR ACC 

7 MOV D.A ;CLEAR D REG 

8 STC ;SET CARRY 

9 RAR ;SET BIT 7 TO 1 

10 MOVB.A ;ST0RE TEST BIT AT B REGISTER 

11 LOOP: MOVE.A ;ST0RE TEST WORD 

12 OUT P0RT1 ;OUTPUTTOA/D 



SEQ 


SOURCE STATEMENT 




13 


IN PORT3 


;INPUT FROM COMP 


14 


CRA A 


;SET SIGN FLAG 


15 


JM NEXT 


;IF SMALLER GO TO NEXT BIT 


16 


MOV D,E 


;SAVE RESULT 


17 NEXT: 


MOV A,B 


;GET NEXT TRIAL BIT 


18 


RAR 


;SHIFT RIGHT ONCE 


19 


RC 


;RETURN ON CARRY 


20 


MOV B,A 


;STORE TEST BIT 


21 


ADD D 


;ACCUMULATE RESULT 


22 


JMP LOOP 


;TRY NEXT BIT 


23 STAKS: 


DS 16 




24 


END START 





3-82 



Am6080 



APPLICATIONS 



Instrumentation and Control 

Data Acquisition 
Data Distribution 
Function Generation 
Servo Controls 

Programmable Power Supplies 
Digital Zero Scale Calibration 
Digital Full Scale Calibration 
Digitally Controlled Offset Null 



Signal Processing 

CRT Displays 

IF Gain Control 

8x8 Digital Multiplication 

Line Driver 



A/D Converters 

Ratiometric ADC 
Differential Input ADC 
Microprocessor Controlled ADC 



Audio 

Music Distribution 
Digitally Controlled Gain 
Potentiometer Replacement 
Digital Recording 



01 A Converters 

Single Quadrant Multiplying DAC 
Two Quadrant Multiplying DAC 
Four Quadrant Multiplying DAC 



Metallization and I 



D Dt D 2 D 3 D 4 D 5 D 6 
9 8 7 6 5 4 3 



■■vrrrvrr 




DIE SIZE 0.085" X 0.124" 



3-83 



Am6081 

Microprocessor System Compatible 8-Bit High Speed Multiplying D/A Converter 



DISTINCTIVE CHARACTERISTICS 

• 8-Bit D/A with 8-Bit input data latch 

• Compatible with most popular microprocessors including 
the Am9080A-4 and the Am2900 

• Write, Chip Select and Data Enable logic on chip 

• DAC appears as memory location to microprocessor 

• MSB inversion under logic control 

• Differential current outputs 

• Output current mode multiplexer with logic selection 

• 2-Bit status latch for output select and code select 

• Choice of 8 coding formats 



• Fast settling current output - 200ns 

• Nonlinearity to ±0.19? max over temperature range 

• Full scale current pre-matched to ±1 LSB 

• High output impedance and voltage compliance 

• Low full scale current drift - ±5ppm/°C 

• Wide range multiplying capability -2.0MHz bandwidth 

• Direct interface to TTL, CMOS, NMOS 

• Output range selection with on chip multiplexer 

• High speed data latch - 80ns min write time 



GENERAL DESCRIPTION 

The Am6081 is a monolithic 8-bit multiplying Digital-to-Analog 
converter with an 8-bit data latch, a 2-bit status latch, chip 
select and other control signal lines which allow direct inter- 
face with microprocessor buses. 

The converter allows a choice of 8 different coding formats. 
The most significant bit (D 7 ) can be inverted or non-inverted 
under the control of the code select input. The code control 
also provides a zero differential current output for 2's com- 
plement coding. A pair of high voltage compliance, dual com- 
plementary current output channels is provided and is 
selected by the output status command. The output multi- 
plexer also allows analog bus connection of several convert- 
ers, range or output load selection, and time-shared operation 
between D/A and A/D functions. The data and status latches 
are high speed which makes the Am6081 capable of interfac- 
ing with high speed microprocessors. The DE and SE control 
signals allow the data and status latches to be updated 



individually or simultaneously. 

Monotonic multiplying performance is maintained over a more 
than 40 to 1 reference current range. Matching within ±1 LSB 
between reference and full scale current eliminates the need 
for full scale trimming in most applications. 

The Am6081 guarantees full 8-bit monotonicity. Nonlinearities 
as tight as 0.1 % over the entire operating temperature range 
are available. Device performance is essentially unchanged 
over the full power supply voltage and temperature range. 

Applications for the Am6081 include microprocessor compati- 
ble data acquisition systems and data distribution systems, 
8-bit A/D converters, servo-motor and pen drivers, waveform 
generators, programmable attenuators, analog meter drivers, 
programmable power supplies, CRT display drivers and high 
speed modems. 



EQUIVALENT CIRCUIT 



LSB MSB CODE 

000,02030,0505 D 7 SEL V+ 



csv 

BE^ 
SE» 

V BEF(+)o 
v REF(-)» 




CODE 
ST»TUS 
L*TCH 




CONNECTION DIAGRAM 
Top View 



CODE SELECT 

(MSB) D7 INPUT 2 D 7 

D 6 INPUT 3 D 6 

D.- INPUT * 

D 4 INPUT 5 

D 3 INPUT 6 [J D 3 

D 2 INPUT 7 

D, INPUT l[3 D, 

(LSB) Dfj INPUT C t>0 

CHIP SELECT 10 | CS 

rz gno 



V ■ POSITIVE PQWEH SUPPLY 

OUT SEL 23 OUTPUT SELECT 

K>; M21 



I 20 OUTPUT 1 
1 19 OUTPUT 1 

| IB NEGATIVE POWER SUPPLY 



V PIEFI-I NEGATIVE REFERENCE 

Vrefi. 

se i | 14 status latch enable 
de ^1] data latch enable 



ORDERING INFORMATION 

Package Temperature Order 
Type Range Nonlinearity Number 



Hermetic 
DIP 


-55°Cto +125°C 


±.1% 
±.19% 


Am6081 ADM 
Am6081 DM 


Hermetic 
DIP 


0°C to +70°C 


±.1% 
±.19% 


Am6081ADC 
Am6081 DC 


Molded 
DIP 


±.1% 
±.19% 


Am6081APC 
Am6081PC 



3-84 



Am6081 



Am6081 FUNCTIONAL PIN DESCRIPTION 
Symbol Function 

CS Chip Select - This active low input signal enables 
the Am6081 . Writing into the data or status latches 
occurs only when the device is selected. 

DE Data Latch Enable - This active low input_is_ used 
to enable the data latch. The CS, DE, and "W must 
be active in order to write into the data latch. 

SE Status Latch Enable - This active highjnput is 
used to enable the status latches. The CS, SE, 
and W must be active in order to write into the 
status latches. 

W Write - This active low control signal enables the 
data and status latches when the CS, DE, and SE 
inputs are active. 

D -D 7 D -D 7 are the input bits 1-8 to the input data latch. 

Data is transferred to the data latch when CS, DE, 
and W are active and is latched when any of the 
enable signals go inactive. 



CODE Code Select - Input to the_CODE SELJatch. The 
SEL latch is transparent when CS, SE and W are ac- 
tive and is latched when any of the above signals 
go inactive. When CODE SEL latch = 0, the MSB 
(D 7 ) is inverted and 1 LSB balance current is 
added to the l output. 

OUT Output Select - Input to the_OUT SELJatch. The 
SEL latch is transparent when CS, SE and W are ac- 
tive and is latched when any of the above signals 
go inactive. When the OUT SEL latch is low, the 
channel 1 output pair (l 01 , T^j) is selected. When 
the OUTJ3EL latch is high, the channel 2 output 
pair (l 02 , I02) is selected. 

VreF(+) Positive and negative reference voltage to the ref- 
V R ef(_) erence bias amplifier. These differential inputs allow 
the use of positive, negative and bipolar references. 

COMP Compensation - Frequency compensating terminal 
for the reference amplifier. 

'oi'Joj These high impedance current output pairs are 
'02> '02 selected by the output select latch. I 01 and I02 are 

true outputs and and IqT are complementary 

outputs. 



DATA LATCH CONTROL 



FUNCTION TABLES 

STATUS LATCH CONTROL 

CODE SEL and 



CODE SELECT AND 
OUTPUT SELECT 



CS 


w 


DE 


Data Latch 


CS 


w 


SE 


OUT SEL Latch 











Transparent 










1 


Transparent 


X 


X 


1 


Latched 




X 


X 





Latched 


X 




X 


Latched 




X 


1 


X 


Latched 


1 




X 


Latched 




1 


X 


X 


Latched 




















CODE 
SEL 


OUT 
SEL 


Function 







MSB Inverted (Note 1) 


1 




MSB Non-inverted 







Output Channel 1 




1 


Output Channel 2 



X = Don't Care 

Note 1 . 1 LSB balance current is added to the Iq output. 



MAXIMUM RATINGS 



Operating Temperature 


Power Supply Voltage 


±18V 


Am6081 ADM, Am6081DM 


-55°C to +125°C 


Logic Inputs 


-5V to +18V 


Am6081ADC, Am6081DC 
Am6081APC, Am6081PC 


0°C to +70°C 


Analog Current Outputs 


-12V to +18V 


Reference Inputs (V 15 , V 16 ) 


V- to V+ 


Storage Temperature 


-65°C to +150°C 


Reference Input Differential Voltage (V 15 to V 16 ) 


±18V 


Lead Temperature (Soldering, 60 sec) 


300°C 


Reference Input Current (l 15 ) 


1 ,25mA 



GUARANTEED FUNCTIONAL SPECIFICATIONS 



Resolution 


8 bits 


Monotonicity 


8 bits 




Am6081 

ELECTRICAL CHARACTERISTICS 

These specifications apply for V + = +5V, = -15V, l REF = 0.5mA, over the operating temperature range 
Output characteristics refer to all outputs. 

Am6081A 



Parameter 



Description 



Conditions 



Min. 



Typ. 



Max. Min. 



unless otherwise specified. 

Am6081 
Typ. Max. Unit 







Resolution 


Straight coding /Sign Magnitude 


8/9 


8/9 


8/9 


8/9 


8/9 


8/9 


bits 






Monotonicity 


Straight coding /Sign Magnitude 


8/9 


8/9 


8/9 


8/9 


8/9 


8/9 


bits 


D.N 


L 


Differential 
iNominedniy 








±0.19 






±0.39 


%FS 


N.L. 




Nonlinearity 




- 


- 


±0.1 


- 


- 


±0.19 


%FS 


Ifs 




Full Scale Current 


V REF = 10.000V 

R 15 = ^16 = 20.000kn 

Ta = 25°C 


1.984 


1.992 


2.000 


1.976 


1.992 


2.008 


mA 


TCI, 


S 


Full Scale Tempco 






±5 


— c\j 




-t-in 

X I u 




ppm/°C 


- 


±.0005 


±.002 




±.001 


±.004 


%FS/°C 


Voc 


Output Voltage 
Compliance 




-10 




+ 18 


-10 




+ 18 


Volts 


'fss 




Full Scale 
Symmetry 


'fsi _ 'fsi or 'fS2 - !fs2 


- 


±0.1 


±1.0 


- 


±0.2 


±2.0 




'oss 




Output Switch 
Symmetry 




'fsi ~ 'fS2 or !fsi _ 'fs2 




mu. 1 






xU.ii 


-i-o n 


/AM 


izs 


Zero Scale Current 




- 


0.01 


0.4 


- 


0.01 


0.8 


/*A 


'dis 




Output Disable 
Current 


Output of mpx "Off" Channels 


- 


0.01 


0.05 


- 


0.01 


0.05 




'RR 




Reference Current 
Range 


V- = -5V 
V- = -15V 





0.5 


0.55 





0.5 


0.55 


mA 





0.5 


1.1 





0.5 


1.1 


V|L 




Logic 
Input 
Levels 


Logic "0" 








0.8 






0.8 


Volts 


V,H 




Logic "1" 




2.0 






2.0 






>IN 




Logic Input Current 


V, N = -5Vto +18V 






40 






40 




Vis 




Logic Input Swing 


V- = -15V 


-5 




+ 18 


—5 




+ 18 


Volts 


Its 




Reference Bias 
Current 




- 


-0.5 


-2.0 


- 


-0.5 


-2.0 


ftA 


dl/d 


t 


Reference Input 
Slew Rate 


Ri5(EQ> = soon 

CC = 0pF 


4.0 


8.0 


" 


4.0 


8.0 


" 




PSS 


!fs+ 


Power Supply 
Sensitivity 


V+ = +4.5V to +5.5V, V- = -15V 
V- = -13.5V to - 16.5V, V+ = +5V 


- 


±0.0005 


±0.01 


- 


±0.0005 


±0.01 


%FS 


PSS 


iFS- 


- 


±0.0005 


±0.01 


- 


±0.0005 


±0.01 






Power Supply 
Range 


'ref - U.bmA, VquT - ov 


4.5 


- 


18 


4.5 


- 


18 


Volts 


V- 




-18 


- 


-4.5 


-18 


- 


-4.5 


l+ 


Power Supply 
Current 


V+ = +5V, V- = -5V 


— 


9.8 


14.7 


— 


9.8 


14.7 


mA 


I- 




—7.4 


— 9.9 




—7.4 


-9.9 


l+ 


V+ = +5V, V- = -15V 




9.8 


14.7 




9.8 


14.7 


I- 




-7.4 


-9.9 




-7.4 


-9.9 


l+ 


V+ = +15V, V- = -15V 




9.8 


14.7 




9.8 


14.7 


I- 




-7.4 


-9.9 




-7.4 


-9.9 


' 


Power 
Dissipation 


V+ = +5V, V- - -5V 




86 


123 




86 


123 


mW 


V+ = +5V, V- = -15V 




160 


222 




160 


222 


V+ - +15V, V- = -15V 




258 


369 




258 


369 



3-86 



Am6081 

AC CHARACTERISTICS 

V + = +5V, V_ = -15V, Iref = 0.5mA, R L < 500fl, C L < 15pF over the operating temperature range unless otherwise specified 











Commercial 
Temp. Grades 


Military 
Temp. Grades 




Parameter 


Description 


Conditions 


Mm. 


Tun 

Typ. 


Max. 


Min. 


Twn 

Typ. 


max. 


Unit 


k 


Settling Time, All Bits Switched 


T A = 25°C 
Settling to ±V 2 LSB 




200 






200 




ns 


tpi_H 


Propagation 


Each bit 


T A = 25°C 
50% to 50% 




90 


180 




90 


180 


ns 


'PHL 


Delay 


All bits switched 




90 


180 




90 


180 


'os 


Output Switch Settling Time 


T A = 25°C 

to ±1/2LSB of l FS 




250 






250 






•op 


Output Switch Propagation 
Delay 


T A = 25°C, 

DU7C 10 OUvc 




150 


300 




150 


300 


ns 


t 

»DH 


Data Hold Time 


Qaa timinn rlianrom 

occ iiiTiiny uidyrdiii 


10 


-30 




10 


-30 






'ds 


Data Set Up Time 


See timing diagram 


80 


35 




100 


35 




ns 


'dw 


Data Write Time 


See timing diagram 


80 


35 




100 


35 




ns 


<SH 


Status Hold Time 


See timing diagram 


10 


-70 




10 


-70 




ns 


*ss 


Status Set Up Time 


See timing diagram 


200 


100 




250 


100 




ns 


<sw 


Status Write Time 


See timing diagram 


200 


100 




250 


100 




ns 



Notes: 1 . t DW is the overlap of W low, CS low, and DE low. All three signals must be low to enable the latch. Any signal going inactive latches the data. 

2. t s is measured with the latches open from the time the data becomes stable on the inputs to the time when the outputs are settled to within 
±1/2 LSB. All bits switched onor off. 

3. t sw is the overlap of W low, CS low and SE high, all three signals must be active to enable the latch and any signal going inactive will latch 
the data. 

4. The internal time delays from CS, W, SE and DE inputs to the enabling of the latches are all equal. 



The h 



(t> -D 7 ) 



OUTPUT 'O 
(NOTE 2) |- 



RAM 



1 / 



|- — to 

xxxxxx— 



Um *DH 

xxxxxxxxxx 



3C 





■ tsw — 

/ 

— 'ss — 




w \ 

(NOTES 3. 4) ' 




co -- XXXXXX mta ™ e 


5<xxxxxxxxx 






<s 




OUTPUT lO 
(NOTE 2) ^ 


K 





3-87 



Am6081 



APPLICATION HINTS 

1 . Reference current and reference resistor 

There is a 1 to 4 scale up between the reference current (l REF ) 
and the full scale output current (l FS ). If V REF = +10Vand l FS 
= 2mA, the value of the R 15 is: 

4x10 Volt 




Reference amplifier compensation 

For AC reference applications, a minimum value compensa- 
tion capacitor (C c ) is normally used. The value of this 
capacitor depends on R 15 . The minimum values to maximize 
bandwidth without oscillation are as follows: 



Table 2 
Compensation Capacitor 
(l FS = 2mA, l REF = 0.5mA) 



Rref (kfi) 


C C (PF) 


20 


100 


10 


50 


5 


25 


2 


10 


1 


5 


.5 






Reference Amplifier 
Frequency Response 




A 0.01 capacitor is recommended for the fixed reference operation. 



Output Voltage 
Compliance 

ALL BITS ON 



































V- 




15V 




1 




OA 


rtiA 








V- 
































'Hth 




I 

















































-14 -10 -6 -2 2 6 10 14 18 
OUTPUT VOLTAGE - VOLTS 



Reference Amplifier Biasing 




Reference Configuration 


R15 


R16 


R IN 


c c 


■ref 


Positive Reference 


Vr+ 


ov 


NIC 


.0VF 


Vr+/Rib 


Negative Reference 


ov 


Vr- 


NIC 


.01 >iF 


-VR-/R15 


Lo Impedance Bipolar 
Reference 


Vr+ 


ov 


Vm 


(Note 1) 


(Vr+/Ris) + (V IN /R|N) 
(Note 2) 


Hi Impedance Bipolar 
Reference 


Vr + 


v IN 


N/C 


(Note 1) 


(V R+ - V IN )/R 15 
(Note 3) 


Pulsed Reference (Note 4) 


Vr+ 


ov 


V|N 


No 
Cap 


(V R+ /R 15 ) + (V IN /R, N ) 



Notes: 1 . The compensation capacitor is a function of the impedance seen at the + V REF input and must be at least C = 5pF x R, 5(EQ) (in kfl). For 
n T5 < 800fi no capacitor is necessary. 

2. For negative values of V, N , V R+ /R 15 must be greater than -V, N Max/R, N so that the amplifier is not turned off. 

3. For positive values of V| N , V R+ must be greater than V| N Max so the amplifier is not turned off. 

4. For pulsed operation, V R+ provides a DC offset and may be set to zero in some cases. The impedance at pin 15 should be 
800fl or less and an additional resistor may be connected from pin 15 to ground to lower the impedance. 



3-88 



Am6081 




OPTIONAL 
(NOTE 1 




MSB LSB. 

Note: Connect all unused outputs to ground. 



CODE FORMAT 


CODE 
SEL 


OUT 
SEL 


CON- 
NECTIONS 


OUTPUT SCALE 


OUT MSB LSB 
SEL D7 D6 OS D4 D3 D2 D1 DO 




(mA) 


(mA) 


V UT 


UNIPOLAR 


Straight binary: one 


1 





a-e 
b-g 


Positive full scale 
Positive full scale - LSB 
Zero scale 


X 11111111 
X 11111110 
X 000000 


1.992 
1.984 
.000 







9.960 
9.920 
.000 




1 


c-e 
d-g 


Complementary binary: 
one polarity with 
complementary input 
code, true zero output. 


1 





a-g 

b-e 


Positive full scale 
Positive full scale - LSB 
Zero scale 


X 000000 
X 000000 1 
X 11111111 


1.992 
1.984 
.000 







9.960 
9.920 
.000 


1 


c-g 

d-e 


SIGNED 
MAGNITUDE 


Signed magnitude binary: 
8 bits + sign reflected 
code, overlapping 
true zero output. 


1 




a-e 
c-f 


Positive full scale 
Positive full scale - LSB 
( ) Zero scale 
(-) Zero scale 
Negative full scale - LSB 
Negative full scale 


1 11111111 

1 11111110 
1 000000 
000000 
11111110 
11111111 


1.992 
1.984 
.000 
.000 
.000 
.000 


.000 
.000 
.000 
.000 
1.984 
1.992 


9.960 
9.920 
.000 
.000 
-9.920 
-9.960 


Complementary signed 
magnitude: 

8 bits + sign complementary 
reflected code, overlapping 
true zero output. 


1 




b-e 
d-f 


Positive full scale 
Positive lull scale - LSB 
(+) Zero scale 
(-) Zero scale 
Negative full scale - LSB 
Negative full scale 


1 000000 
1 1 

1 11111111 

11111111 
000000 1 
000000 


1.992 
1.984 
.000 
.000 
.000 
.000 


.000 
.000 
.000 
.000 
1 984 
1.992 


9.960 
9.920 
.000 
.000 
-9.920 
-9.960 


SYMMETRICAL 
OFFSET 


Straight offset binary: 
offset half scale, 
symmetrical about zero, 
no true zero output. 


1 





a-e 
b-f 


Positive full scale 
Positive full scale - LSB 
(+) Zero scale 
(-) Zero scale 
Negative full scale - LSB 
Negative full scale 


X 11111111 
X 11111110 
X 1 000000 
X 1111111 
X 000000 1 
X 000000 


1.992 
1.984 
1.000 
.992 
.008 
.000 


.000 
.008 
.992 
1.000 
1.984 
1.992 


9.960 
9.880 
.040 
-.040 
-9.880 
-9.960 


1 


c-e 
d-f 


1's complement: 
offset half scale, 
symmetrical about zero, 
no true zero output 
MSB complemented, 
(need inverter at D 7 ) 


1 

(Note 1 ) 





a-e 
b-f 


Positive full scale 
Positive full scale - LSB 
(+) Zero scale 
(-) Zero scale 
Negative full scale - LSB 
Negative full scale 


X 1111111 
X 1111110 
X 000000 
X 11111111 
X 1 1 
X 1 000000 


1.992 
1.984 
1.000 
.992 
.008 
.000 


.000 
.008 
.992 
1.000 
1.984 
1.992 


9.960 
9.980 
.040 
-.040 
-9 880 
-9.960 


1 


c-e 
d-f 


OFFSET 
WITH 
TRUE 
ZERO 


Offset binary: 
offset half scale, 
true zero output 
MSB complemented 
remainder add to l G . 
(need inverter at D 7 ) 




(Note 1) 





a-e 
b-f 


Positive full scale 
Positive full scale - LSB 
+ LSB 
Zero scale 
- LSB 

Negative full scale + LSB 
Negative full scale 


X 11111111 
X 11111110 
X 1 1 
X 1 000000 
X 1111111 
X 000000 1 
X 000000 


1.992 
1 984 
1.008 
1.000 
1.992 
.008 
000 


.008 
.016 
.992 
1.000 
1.008 
1.992 
2.000 


9.920 
9.840 
.080 
.000 
-.080 
-9.920 
-10.000 


1 


c-e 
d-f 


2's complement: 
offset half scale 
true zero output 
MSB complemented. 








a-e 
b-f 


Positive full scale 
Positive full scale - LSB 
+ 1 LSB 
Zero scale 
-1 LSB 

Negative full scale + LSB 
Negative full scale 


X 111111 1 
X 1111110 
X 000000 1 
X 000000 
X 11111111 
X 1 1 
X 1 000000 


1.992 
1.984 
1.008 
1 000 
.992 
.008 
.000 


.008 
.016 
.992 
1.000 
1.008 
1.992 
2.000 


9.920 
9.840 
.080 
.000 
-.080 
-9.920 
-10.000 


1 


c-e 
d-f 



Note 1 : An external inverter is necessary since the code select inverts the MSB and adds a 1 LSB balance current to l . Only one of the two features 

is desired for these codes. 
ADDITIONAL CODE MODIFICATIONS 

1 . Any of the offset binary codes may be complemented by reversing the output terminal pair. 

2. The sign on any of the sign-magnitude codes may be changed by reversing the output terminal pair. 

3. The polarity of the unipolar codes may be changed by driving the opposite side of the balanced load. 

3-89 



Am6081 



SYSTEM APPLICATIONS 

Am9080A DATA SYSTEM: SEPARATE UPDATE OF DATA AND STATUS 



SELECT OUTPUT PORT 1 



CHIP 
SELECT 
DECODER 



DATA BUS 


; 












D | 


* ► 




DE SE D -D 7 CODE OUT \ 

SEL SEL 

CS 10, V 

w 





:> 



MVI A, 2 
OUT 1 
MOV A, M 
OUTO 



SET STATUS TO (SELECT OUTPUT 1) 

SEND STATUS 

GET DATA FROM MEMORY 

SEND DATA 



SELECT OUTPUT PORT 2 

MVI A, 3 : SET STATUS TO 1 (SELECT OUTPUT 2) 

OUT 1 : SEND STATUS 

MOV A,M : GET DATA FROM MEMORY 

OUT : SEND DATA 



SELECT OUTPUT PORT 2 AND 2 s COMPLEMENT CODE 

MVI A, 1 
OUT 1 
MOV A, M 
OUTO 



SET STATUS TO 3 (OUTPUT 2, MSB COMP) 
SEND STATUS 
GET DATA FROM MEMORY 
SEND DATA lic-oob 



Am9080A DATA SYSTEM: SIMULTANEOUS UPDATE OF DATA AND STATUS 



O -D 7 
SYSTEM 

iow 




ADDRESS BUS 












AO 


( DATA BUS > 










z\ 

SEL 
DEC 


IP 

ECT C 

)DER 


CODE D -D 7 OUT , \ 

CS SEL SEL jA" 

101 V — 

Am6081 / 

« 

SE DE ^2/- 







MOV A, M 
OUTO 
OUT 1 
OUT 2 
OUT 3 



GET DATA IN ACCUMULATOR 
OUTPUT DATA TO PORT 1, 2'S COMPLEMENT 
OUTPUT DATA TO PORT 2, 2'S COMPLEMENT 
OUTPUT DATA TO PORT 1, STRAIGHT BINARY 
OUTPUT DATA TO PORT 2, STRAIGHT BINARY 



Lic-010 



Am9080A DATA SYSTEM: 8-BIT PLUS SIGN CONVERSION 




I I 



MOV A, M 
OUTO 
OUT 1 



LOAD MAGNITUDE (8-BITS) 
SEND POSITIVE OUTPUT 
SEND NEGATIVE OUTPUT 



3-90 



SYSTEM APPLICATIONS (Cont.) 
Am2900 DATA SYSTEM: MULTIPLE ANALOG OUTPUTS 







COM 
REG 
Am2S 


imp 

STER 
LS374 








u PROGRAM 
SEQUENCER 
(2) Am29 1 1 




8 


CONTROL STORAGE 
(6) Am27S1l 
256 x 24 PROM 




24 


INSTRUCTIC 
REGI 


N PIPELINE 
STER 



„ INSTRUCTION 
DECODER 
Am29811A 



MUX 

Am25S151 



DACK 

■ IACK 

■ EOP 
• RDV 




3-91 



Am6081 



SYSTEM APPLICATIONS (Cont.) 



D/A CONVERSION WITH 12-BIT DYNAMIC RANGE 



7 °6 K 5 a A 



DIGITAL 
INPUT 



°3 B 2 B 1 B 



1A 2A 3A 4A 1B 2B 3B 4B 
S Am25LS157 

1C 2C 3C 4C 



WHEN THE UPPER 4 BITS, D 8 -D n , OF 
THE 12-BIT CODE ARE ZERO, THE 
LOWER 8 BITS AND THE 1X SCALE 
ARE SELECTED. 



1A 2A 3A 4A 1B 2B 31 
S Am25LS157 

1C 2C 3C 4C 



D 7 D 6 D 5 D 4 



D 3 D 2 D, D ,o 2 




AID CONVERSION WITH AUTO RANGING AND DIFFERENTIAL INPUT 



OUT 
SEL 



D 7 D 6 D 5 D 4 D 3 D 2 D, D 



<f 



±3 




■ °7 

■ °B 

■ o, 

■ D 2 



DIGITAL 
OUTPUT 



O, Q 6 Q 5 4 3 Q 2 Q, Q 



START 
COMMAND 



7=0 



Am2502 



WHEN THE FIRST FOUR BITS CONVERSION 
RESULTS ARE ZERO. THE IX SCALE 
IS SELECTED AND THE CONVERSION IS 
RESTARTED. THE START COMMAND 
RESETS THE CONVERSION TO 16X SCALE 



LIC-014 



3-92 



Am 6081 



SYSTEM APPLICATIONS (Cont.) 



ANALOG/DIGITAL TRANSCEIVER WITH HARDWARE 
CONTROLLED SUCCESSIVE APPROXIMATION A/D CONVERSION 



ANALOG 




LIC-015 



ANALOG/DIGITAL TRANSCEIVER WITH 
SOFTWARE CONTROLLED A/D CONVERSION 

ANALOG 




Am6081 









Am9080A SOFTWARE FOR A/D AND D/A CONVERSION USING Am6Q81 




s 


EQ 


SOURCE STATEMENT SEQ 


SOURCE STATEMENT 





PORT1 


EQU 00H 


18 


CMA 




1 


PORT3 


EQU 02H 


19 


CPA A 


SET SIGN FLAG 


2 P0RT2 


EQU 01 H 


20 


JM NEXT 


IF SMALLER GO TO NEXT BIT 


Q 





ORG 3E50H 


21 


MOV D,E 


SAVE RESULT 


A 
H 


CTADT- 
o I Mn I . 


LXI SP.STAKS-16 


INITIAL STAKS POINTER 22 NEXT: 


MOV A,B 


GET NEXT TRIAL BIT 


5 


SAMPLE: 


CALL ADCON 


;CALL A/D CONVERSATION 23 


RAR 


SHIFT RIGHT ONCE 


6 




CMA 


24 


RC 


RETURN ON CARRY 


7 




CALL DACON 


;CALL D/A CONVERSION 25 


MOV B,A 


STORE TEST BIT 


8 




JMP SAMPLE 


'.NEXT SAMPLE 26 


ADD D 


ACCUMULATE RESULT 


9 


ADCON: 


XRA A 


.CLEAR ACC 27 


JMP LOOP 


TRY NEXT BIT 


10 




MOV D,A 


;CLEAR D REG 28 DACON: 


OUT PORT 2 


OUTPUT TO D/A 


11 






;SET CARRY 29 


MVI C.05H 


LOAD C REG WITH TIME 


12 




RAR 


;SET BIT 7 TO 1 30 


OCR C 


TIME DELAY 


13 




MOV B,A 


;ST0RE TEST BIT AT B REGISTER 31 


RZ 


RETURN 


14 


LOOP: 


MOV E,A 


;ST0RE TEST WORD 32 FILT: 


RET 




15 




CMA 


33 STAKS: 


OS 16 




16 




OUT P0RT1 


;0UTPUT TO A/D 34 


END START 




17 




IN PORT3 


;INPUT FROM COMP 
























ADVANCED MICRO DEVICES DATA CONVERSION PRODUCTS 








Digital to Analog Converters 










AmDAC-08 


- 8-Bit High Speed Multiplying D/A Converter 










Am 1508/1 408 


- 8-Bit Multiplying D/A Converter 










Am6070 


- 8-Bit Companding D/A Converter for Control Systems (/x-law) 








Am6071 


- 8-Bit Companding D/A Converter for Control Systems (A-law) 








Am6072 


- 8-Bit Companding D/A Converter for Telecommunications (^t-law) 








Am6073 


- 8-Bit Companding D/A Converter for Telecommunicatons (A-law) 








Am6080 


- 8-Bit High Speed Multiplying D/A Converter System/Microprocessor Compatible 






Am6081 


- 8-Bit High Speed Multiplying D/A Converter System/Microprocessor Compatible 






*Am6689 


- 8-Bit, Ultra High Speed D/A Converter (ECL) 










*Am6012 


- 12-Bit High Speed Multiplying D/A Converter 










Analog to Digital Converters 










*Am6688 


- 4-Bit Quantizer (Ultra High Speed A/D Converter) 








Successive Approximation Registers 










Am2502 


- 8-Bit Successive Approximation Registers 










Am2503 


- 8-Bit Successive Approximation Registers 










Am2504 


- 12-Bit Successive Approximation Registers 










Sample and Hold Amplifiers 










LF1 98/398 


-Monolithic Sample and Hold Amplifier 










*Am6098 


-Precision Sample and Hold Amplifier 










Comparators 












LM1 11/311 


- Precision Voltage Comparator 










LM119/319 


- Dual Comparator 










Am686 


- High Speed Voltage Comparator 










High Speed Operational Amplifiers 










Ami 18/31 8 


- High Speed Operational Amplifier 










LF1 55/1 56/1 57 


- JFET Input Operational Amplifiers 










LF355/356/357 


- JFET Input Operational Amplifiers 








• To be announced. 







3-94 



Am6081 



APPLICATIONS 



Instrumentation and I 

Data Acquisition 
Data Distribution 
Data Transceiver 
Function Generation 
Servo Controls 

Programmable Power Supplies 
Digital Zero Scale Calibration 
Digital Full Scale Calibration 
Digitally Controlled Offset Null 



Signal Processing 

CRT Displays 

Floating Point Analog Processors 
IF Gain Control 
Four Quadrant Multiplexer 
8x8 Digital Multiplication 
Line Driver 



A/D Converters 

Ratiometric ADC 
Differential Input ADC 
Multiple Input Range ADC 
Two Channel ADC 
Microprocessor Controlled ADC 



Audio 

Music Distribution 
Digitally Controlled Gain 
Potentiometer Replacement 
Digital Recording 
Speech Digitizing 



D/A Converters 

Single Quadrant Multiplying DAC 
Two Quadrant Multiplying DAC 
Four Quadrant Multiplying DAC 
Two Channel DAC 
Multiple Output Range DAC 



Metallization and Pad Layout 



D D, Dj D 3 D 4 D 5 D 6 
9 8 7 6 5 4 3 




16 17 18 19 20 21 

v REF(-> COMP V- 10, ioj I0 2 



DIE SIZE 0.085" X 0.124" 



3-95 




TABLE OF CONTENTS 



INTRODUCTION 3-97 

Companding Principles 3-97 

Analog to Digital Conversion Using DACs 3-98 

Companding DACs in Industrial Systems 3-99 

Companding DACs in PCM 

Transmission Systems 3-99 

COMPANDING DAC CIRCUIT DESCRIPTION 3-100 

General Circuit Description 3-100 

Detailed Circuit Description 3-101 

Generation of the /n-Law and A-Law Characteristics . 3-104 

Output Current Tables 3-104 

Parametric Analysis and Recommendations 3-109 



TYPICAL CIRCUIT APPLICATIONS 3-111 

Basic Circuit Connections 3-111 

Operating Modes 3-114 

Microprocessor Based Data Acquisition 

Systems Applications 3-115 

Motion Control Systems Applications 3-118 

Audio System Applications 3-120 

Telecommunication Systems Applications 3-123 

SUMMARY 3-129 

REFERENCES 3-129 



3-96 



Companding DAC 



INTRODUCTION 

Modern electronic systems are replacing many of the analog 
signal processing and transmission functions with digital data 
processing. The use of digital electronics can lead to im- 
provements in system cost, performance, accuracy and relia- 
bility. Digital systems can transmit many signals on the same 
line in a multiplexed mode and do not suffer from the same 
kinds of noise and crosstalk problems that are inherent in 
analog systems. The digital processing of analog information 
requires conversion of the analog signal into digital form and 
the reverse conversion of the digital result back into an analog 
signal. Analog to digital converters, (ADC), and digital to 
analog converters, (DAC), perform these functions. The DAC 
is the key circuit element in both of these processes since it is 
used in a feedback loop to generate the ADC function. 
Monolithic technology has advanced dramatically in the last 
few years making low cost 8-bit DACs a reality today; in the 
near future, 10 and 12-bit monolithic DACs will also become 
available. This trend in DAC technology will help accelerate 
the trend toward more digital processing and transmission of 
analog information. 

Many analog signals vary in amplitude from very small values 
to very large values. The dynamic range of a converter is a 
measure of its ability to handle a wide range of input 
amplitudes and is defined as the ratio of the largest resolvable 
signal (V m max.) to the smallest signal (V| N min.) that can be 
handled. This ratio is often expressed in decibels using the 
conversion formula 20 log (V| N max/V| N min). Linear DACs re- 
solve a ratio of 2 n :1, (n equals the number of bits), or n • 6dB. 
An 8-bit linear DAC, for example, resolves a ratio of 256:1 or 
48dB. 

The accuracy of a converter is a prime concern in most appli- 
cations. Accuracy is generally specified with respect to the full 
scale output (as a percent of full scale) or to the smallest step 
size (i.e., ±1/2LSB refers to ±1/2 of the smallest step size). 
Linear converters tend to be more accurate as the number of 
steps increases because the step size decreases. Many sys- 
tems require high accuracy as a percent of the input signal 
level rather than as a percent of full scale. The accuracy as a 
percent of input signal level (reading) decreases as the signal 
level decreases because the amount of error is constant. An 
8-bit linear DAC with an accuracy of .2% of full scale (±1/2 
LSB) has an accuracy of .2% of reading for input signals 
near full scale, but an accuracy of only 20% of reading for an 
input near 195 of full scale. 

For many types of applications, the accuracy and dynamic 
range of an 8-bit linear DAC are sufficient. However, there are 
many classes of problems that require a wider dynamic range 
to handle signal ratios of several thousand to one. Voice 
processing, speed control and music synthesis fall into this 
category. A 12-bit linear DAC provides a wider dynamic 
range, 72dB, and higher accuracy than an 8-bit linear DAC. 
However, these devices are very expensive, and, furthermore, 
it turns out that while most applications require the dynamic 
range of the 12-bit linear DAC they do not require its ac- 
curacy. A nonlinear DAC can provide such performance with 
fewer digital bits. It does so by using a nonlinear transfer 
characteristic to compress an analog signal into a digital word, 
and a complementary transfer characteristic to expand the 
digital values into analog signals with a wide dynamic range. 

An 8-bit nonlinear DAC can achieve a 72dB dynamic range 
with accuracy expressed as a percent of reading that ranges 
from 1.6% to 3.2% over the entire dynamic range of the de- 
vice. The overall nonlinear analog to digital and digital to 



analog conversion procedure is called the companding pro- 
cess. This note will discuss the Am6070 family of Compand- 
ing DACs and their applications. 

Companding Principles 

Companding transfer functions were originally developed to 
satisfy the requirements of telephone voice communication 
systems. Studies of speech signals have shown that the dis- 
tribution of amplitudes covers a range of several thousand to 
one and that the lower amplitude signals occur more often 
than the large amplitude signals. More attention should, there- 
fore, be paid to the low level signals. It is important to main- 
tain a better signal to distortion ratio (the ratio of signal level 
to conversion error) for low level signals at the expense of a 
poorer ratio for the less probable high level signals. In order 
to accomplish this goal, a logarithmic type of transfer charac- 
teristic is used with more steps at low levels and fewer steps 
at high levels. 

A true logarithmic function has a discontinuity at zero and 
thus cannot be used directly for signal compression. A modi- 
fied transfer characteristic with the form "log (1 +x)" can be 
used to smooth the characteristic near zero. Two popular 
schemes have been developed - the ji-law by the Bell sys- 
tem for use in U.S. telephone systems and the A-law by the 
CCITT for use in European systems. They can be described 
by the following mathematical equations: 



fi-Law: Y = 0.18 In (1 X| ) sgn (X) 

A-Law: Y = 0.18 (1 + In (A |X | )) sgn (X), 1/As |X|s 1 

Y = 0.18 (A|X|) sgn (X), =s |X| =s 1/A 

where: X = analog signal level normalized to unity 
(encoder input or decoder output) 

Y = digital signal level normalized to unity 

(encoder output or decoder input) 
fx = 255 and A = 87.6 

Both functions require that the size of the analog output 
change increase for each increasing digital code. In order to 
implement such a function, an overly complex analog circuit 
would be needed. This requirement is met, instead, by a 
piecewise linear approximation. In this approximation, an 8-bit 
digital word generates 256 analog outputs with a transfer 
characteristic which is symmetrical about the origin. Figure 1 
shows the /x-law and A-law transfer characteristics and the 
linear 8-bit DAC transfer characteristic. The positive 128 steps 
are divided into 8 segments or chords of 16 steps each, from 
step to step 15. The step size is constant within a chord 
and doubles for each increasing chord. If the step size in the 
first chord, chord 0, is assigned a value of 1, the next chord, 
chord 1 , has a step size of 2, chord 2 has a step size of 4, 
etc. The last chord has a step size of 128 units and ends 
roughly at the value 4000. The 128 steps represent a 7-bit 
digital word with a dynamic range of 72dB, 20 log (4000:1), 
which is equivalent to the dynamic range of a 12-bit linear 
DAC. 

The above description describes the ft-law curve. The A-law 
differs from the ^-law only in the first two chords. The step 
size in the A-law DAC does not change between the first and 
second chords, but doubles in all succeeding chords. The 
A-law DAC has a 1/2 step offset at zero so that the positive 
and negative zero codes do not generate the same point. The 
A-law DAC has a dynamic range of 62dB which is equivalent 
to an 1 1 -bit linear DAC. 



3-97 



Companding DAC 




8-BIT 
LINEAR DAC I 



DIGITAL INPUT 



"0.5mA 
(FOR A-LAW) 



J I I I L 

IRD 1 

CHORD 

CHORD 3 j 




(l FS = 2048pA) 



Fig. 1. Transfer Functions for ^-Law and A-Law Decoders. 



I to Digital Conversion Using 



A digital input word to a DAC corresponds to an exact and 
unique analog output level. The total number of discrete out- 
put levels, m, depends on the number of DAC binary inputs, 
(m=2 n , n = number of input bits), and each output level is 
specified to be within a certain error band of its ideal value. 
An analog input to an ADC, on the other hand, may have an 
infinite number of signal levels which must be represented 
with only a finite number of digital output combinations. The 
output code, ideally, identifies the digital word that most 
closely represents the analog input. The classical way to gen- 
erate a fast ADC function is to use a DAC in a feedback loop 
together with special ADC logic, employing a comparator and 
a successive approximation register (SAR). The feedback 
loop compares the DAC output with the analog input and de- 
cides whether the digital code is greater than or less than the 
input to the DAC. The input to the DAC is then increased or 
decreased accordingly, and another comparison is made. This 
technique causes each bit to be changed one at a time, and, 
by comparing the DAC's output with the analog input, the 
value of that bit is determined. Modification of one bit at a 
time, starting with the most significant bit and ending with the 
least significant bit, leads to an output which with each suc- 
e bit becomes a closer approximation of the input level. 
A total of n comparisons are needed for an n-bit converter. 



The overall transfer characteristic of the entire ADC system is 
shown in Figure 2a. The ADC logic approximates the input 
analog signal by rounding off to the closest lower digital value. 
The maximum uncertainty in the digital representation of the 
analog input will be a full bit. In order to reduce this uncer- 
tainty, the ADC transfer curve can be modified to round to the 
nearest digital code, instead of the lowest, by adding a half 
step offset to the characteristic as shown in Figure 2b. The 
ADC now changes its outputs for analog inputs halfway be- 
tween digital code points and gives a reading with ±1/2 step 
uncertainty. The half step offset necessary for better ADC ac- 
curacy is easily provided by increasing the DAC's analog out- 
put level by a half step whenever the DAC is used in an ADC 
scheme. This additional half step is easy to generate with 
linear DACs because of their constant step size throughout 
the entire dynamic range. For a Companding DAC this addi- 
tion is much more difficult since the step size varies with sig- 
nal value. In order to alleviate this problem, the Companding 
DAC has a built in capability to produce an appropriate half 
step offset signal at_its output by a logic command. When this 
command input (E/D pin) is at logic 0, the Companding DAC 
is in the decode mode and the output will not contain the half 
step offset current. When the command input is at logic 1, the 
DAC is in the encode mode, i.e., within an ADC scheme, and 
the output current is increased by the correct half step for any 
input mode. 



3-98 



Companding DAC 





X101 






X101 

< 






. SIGN, 


X100 












TPUT OIGITAI 


X011 
X010 






< 

t X011 
D 

| X010 






o 


X001 


' ' 




° X001 
XDOO 


/I I I I I l l 








INPUT ANALOG SIGNAL 

a. Without Input Offset Signal. 


LIC-018 




INPUT ANALOG SIGNAL 

b. With a 1/2 Step Offset Signal. 


LIC-019 



Fig. 2. Transfer Characteristic of an A to D Conversion System. 



Companding DACs in Industrial Systems 

Companding DACs differ from linear DACs in output dynamic 
range, transfer function, and the size of intermediate output 



Comparable 8-bit linear DACs, such as the popular 
AmDAC-08, have a linear transfer characteristic with 256 
linear steps, where each step is 8/u.A in size. The AmDAC-08 
has a dynamic range of only 48dB while the 8-bit Com- 
panding DAC, (Am6070), has an output dynamic range of 
72dB, which is also achievable with a 1 2-bit linear DAC. The 
output current increments of the Companding DAC, corres- 
ponding to small output signals, are significantly smaller than 
8/j.A, which is the step size for the AmDAC-08. The step sizes 
in the first four chords of the Companding DAC transfer func- 
tion are 0.5fiA, 1 .0/xA, 2.0/u.A, and 4.0^.A, respectively, with a 
total of 64 steps and a current value at the end of the fourth 
chord of approximately 100^A. By comparison, the AmDAC- 
08 uses only 12 uniform steps to resolve a 100/u.A output cur- 
rent level. 



Given the assumption that most industrial systems employ an 
8-bit digital data bus, the 8-bit DAC is a logical choice for 
interfacing with these systems. Companding DACs can be 
used in the same general applications as the AmDAC-08, particu- 
larly for reconstruction of analog signals with dynamic ranges that 
exceed 48dB. One example is the measurement of gas or liquid 
pressure, in an industrial environment, by pressure transducers 
with a pressure range of to 3000PSI. Another example is digital 
recording of sound signals which usually exhibit a very large 
dynamic range. 

The Companding DACs logarithmic-like nonlinear transfer 
function suggests the application of this device for simulation 
of nonlinear waveforms which can be generated by converting 
a sequence of bytes, from an 8-bit processor, into an analog 



signal with an exponential shape. This type of signal can be 
used in nonlinear control systems such as motor velocity con- 
trollers. Additionally, the high resolution and accuracy of the 
Companding DAC transfer function, for small output signal 
levels, provide a very smooth and precise analog control sig- 
nal to devices whose outputs are voltage or current depen- 
dent. 

In general, the Companding DAC should be used in any sys- 
tem where a large dynamic range is needed. Such systems 
include servo motor controls, electromechanical positioning, 
voice and music synthesis and recording, secure communica- 
tions, log sweep generators, digital control of gain and attenu- 
ation, and microprocessor controlled signal generation. 

Companding DACs in PCM Transmission Systems 

The companding laws were developed to satisfy the require- 
ments of the telephone system for the digital transmission of 
voice signals. Voice signals exhibit a dynamic range of sev- 
eral thousand to one. To transmit this information with 8-bit 
words and retain reasonable accuracy at low levels, a com- 
panding transfer characteristic must be used to compress the 
analog signal prior to transmission and to restore the original 
signal after reception. The transmission of an analog signal in 
a digital format involves sampling, quantizing (A to D conver- 
sion), and compressing the analog signal as shown in Figure 
3. The receiver must perform the complementary functions of 
expansion, digital to analog conversion and filtering to restore 
the analog signal waveform. The entire procedure is known as 
pulse code modulation, (PCM), and is the prevalent technique 
for digital transmission in communication systems. Currently, 
the Bell ^t-law is the standard in the United States and the 
CCITT A-law is the standard in Europe. 



SAMPLING 
OF AN ANALOG 
SIGNAL 



DIGITAL REPRESENTATION 
OF ONE PARTICULAR 
ANALOG SIGNAL AMPLITUDE 



ANALOG SIGNAL 




{MSB) 



AMPLITUDE 
SAMPLES 



[BIT 1 I BIT 2 jBIT 3] BIT 7\B\T 5 I BIT 6 J BIT 7I BIT B\ 

"1" "1" "0" "1" "1" "1" "0" "1" 



Fig. 3. Pulse Code Modulation Example. 

3-99 



Companding DAC 



ANALOG _ 
INPUT 



QUANTIZER 
(A TO 0) 



TRANSMITTER 
(PCM ENCODER) 



COMPRESSOR 



SERIAL TO 
PARALLEL 
REGISTER 



DAC 
(D TO A) 



ANALOG 
OUTPUT 



(PCM DECODER) 



LIC-021 

Fig. 4 One-Way PCM Transmission System Block Diagram. 



ANALOG 
INPUT 



A TOD 

OUTPUT 




ANALOG INPUT 



SAMPLE 

a 

HOLD 



COMPARATOR 



SUCCESSIVE 
APPROXIMATION 
LOGIC 



TRANSMITTER 



COMPANDING DAC 



TO A TRANSFER 
FUNCTION: 

ANALOG 
OUTPUT 



DIGITAL INPUT 



SERIAL TO 
PARALLEL 
REGISTER 



COMPANDING 
DAC 



Fig. 5. One-Way PCM Transmission System Implemented with Companding DAC. 



A simplified block diagram of a PCM transmission system is 
shown in Figure 4. The analog signal must be sampled at a 
rate that is at least twice as fast as the maximum bandwidth 
of the system, (3.4KHz), in order to achieve satisfactory signal 
reproduction at the receiver site. (This requirement is based 
on the Nyquist sampling theorem.) The telephone system 
uses a sampling rate of 8kHz which allows 125^s between 
samples. During this time the entire signal sampling, quan- 
tizing, encoding, and multiplexing must be completed. 

The companding DAC is a complete PCM decoder (receiver) 
that performs both the decoding and D/A conversion. The 
DAC has additional encoding capabilities which make it very 
attractive for use in CODECs (a CODEC is both an Encoder 
and Decoder). The transfer characteristics of this device 
closely follow the characteristics defined by the /i-law, 
(Am6072), or A-law, (Am6073), A typical connection of a 
Companding DAC in a PCM transmission system is shown in 
Figure 5. In the transmitter side, the Companding DAC op- 
erates in a feedback loop using a SAR to perform the data 
encoding function. The corresponding logarithmic transfer 
curve for the entire feedback loop portion of the transmitter is 
also shown in Figure 5. The value of the sampled signal is 
estimated by a series of 9 iterations until its appropriate quan- 
tised digital representation appears at the 8-bit parallel data 
output of the SAR. This 8-bit digital code will be transmitted to 
the digital inputs of another Companding DAC for the de- 
coding operation. The input/output transfer function for the 
Companding DAC is also shown in Figure 5. 



The Companding DAC can be used in PCM decoders, en- 
coders or complete CODECs. It is a high speed device that is 
capable of handling more than one channel in a multiplexed 
system. In multi-channel systems Companding DACs can be 
configured in a variety of ways depending on the number of 
channels, the method of transmission, (serial or parallel data), 
and synchronization of the system. A single Companding DAC 
can be used, for example, to decode all 24 channels in a 
standard Bell D3 data bank. 



COMPANDING DAC CIRCUIT DESCRIPTION 
General Circuit Description 

The basic function of the 8-bit, Companding DAC is to convert 
a digital input value into an analog output current. The output 
current is a function of the digital data inputs and the input 
reference current. The full scale current, l FS , is generated by 
the 7-bit data input binary code 111 1111, and is a linear 
function of the reference current, l REF . There are two oper- 
ating modes, Encode and Decode, which are controlled by the 
Encode/Decode, (E/D), digital control signal. The output 
dynamic ranges achieved with the sign-plus-7-bit Companding 
DACs are 62dB (A-law) and 72dB (/j.-law) which correspond 
to the output dynamic ranges of sign-plus-11-bit and sign- 
plus-1 2-bit linear binary DACs. Digital data and control inputs 
provide for easy digital control of converter operations in 
computer based data conversion systems. 



Companding DAC 



The internal device design assures the accuracy and 
monotonicity of the Companding DAC over the entire dynamic 
and temperature ranges by maintaining the chord end points 
and step size deviations within allowable limits. Parametric 
deviations and requirements can be expressed in terms of 
corresponding step fractions which are applied throughout the 
entire output dynamic range. In industrial environments it is 
customary to specify allowable deviations from ideal paramet- 
ric values within ± half a step. However, the At-law and A-law 
based PCM communication systems specify the output cur- 
rent deviations in terms of dB, with respect to l FS . Further- 
more, these communication requirements in dB cannot be 
translated to some reasonable "step fraction" deviation which 
will be common for the entire output dynamic range. Con- 
sequently, Companding DACs applied in communication sys- 
tems must be tested against specific output current values 
which are calculated separately for each step of the transfer 
characteristic. This difference between communication and in- 
dustrial Companding DAC devices is recognized by Advanced 
Micro Devices which offers n-law and A-law devices for both 
the industrial market, Am6070 and Am6071, and the tele- 
communication market, Am6072 and Am6073. 

These Companding DACs are manufactured in an 18-pin 
package. There are seven digital data inputs, _(B1 through 
B7), two control digital input signals, (SB, E/D), and four 
analog current outputs, (l D(+). 'od(-). 'oei+i. !oe(-))- Tne 
maximum output current value or full scale current, l FS , is de- 
termined by the value of the reference current, l REF , supplied 
to the Companding DAC via two analog reference inputs, 
(V R(+) and V R( _)). There are three power supply connections 
(V-, V+ and Ground). 



Detailed Circuit Description 

The block diagram of the Companding DAC is shown in Fig- 
ure 6. The circuit consists of the following five major blocks: 

• The chord generator produces the total current for each 
chord or segment of the curve. 

• The pedestal generator generates the pedestal or starting 
point for each chord. 

• The step generator generates the proper step current for 
each chord. 

• The chord decoding logic decodes the chord inputs and 
controls the inputs to the pedestal and step generator cir- 
cuits. 

• The output switching matrix sums the step and pedestal 
currents and routes them to the proper output node. 

To understand the circuitry of the Companding DAC it is im- 
portant to understand how the companding curve is gener- 
ated. The companding curve is a piecewise linear approxi- 
mation of an exponential characteristic. It consists of 16 linear 
segments centered around the origin. The curve is symmetri- 
cal around the origin so we need only examine the positive 
portion of the curve. Each segment or chord consists of six- 
teen steps, step through step 15, and the size of each step 
doubles as the chord number increases. In order to smooth 
out the characteristic as the chords change, the step current 
value for the first step of each higher chord, step 0, is set to 
be 1 1/2 times larger than the step current values in the lower 
chord. The succeeding fifteen steps, step 1 to step 15, are 2 
times larger than steps of the previous chord. Figure 7 shows 
a detailed synthesis of the companding function. The first 



CHORD BITS 



«LC- 



B t B 5 B 6 B 7 



6 7 8 



1 OF 8 
CHORD DECODER 



SB E/B 
2 1 



STEP CURRENT 
GENERATOR 



OUTPUT 
CURRENT 
SWITCH 
MATRIX 



- Ioe(+I 

- l OE <-) 

" l D< + > 

- Iqd(-) 



PEDESTAL 
SELECTOR & 
GENERATOR 



Vr(-H 




Note 1: l EN contributes to Iq only in the encode mode specified by E/D = "1" 



Fig. 6. Companding DAC Functional Block Diagram. 

3-101 



Companding DAC 




Fig. 7. Construction of /i-Law 



chord, CO, is generated from a current source, l co . The sec- 
ond chord, C1, starts at current l P1 , (known as the pedestal 
current), and is generated from a current source, lei, which is 
twice the value of l co . The next chord current source, \ C2 , 
starts at a pedestal current l P2 and has a total value equal to 
four times l co . This process continues with each chord N hav- 
ing a total chord current equal to 2 N I C0 and starting at a 
pedestal current which equals the summation of all currents in 
the lower chords: 



N-1 

Ipn = 2 0cm + 1-5'Im) 

M=0 



N-1 

16.5 2 l M , (l P0 = 0), 
M=0 



The generation of the pedestal current by summing the lower 
chords ensures monotonic behavior in the transition between 
chords. The selection of the proper step within the given 
chord is accomplished by routing the chord current, l CN , 
through a step generator which chooses the proper fraction of 
the chord current necessary to generate the selected number 
of steps. The resulting net output current I ut. can De ex- 
pressed in terms of step currents, l N , corresponding to the 
chord N: 

N-1 

l 0UT = l PN + S-I N = (16.5 2 l M ) + S • l N , (Ipo = 0), 
M=0 



where S = step number 
number = 0, 1 7. 



0, 1, 



15 and N = chord 



where l M is the step current value in chord M. 



The circuit has 9 digital inputs, an 8-bit word and a control bit. 
The 8-bit digital input word is broken into three parts. The first 
bit is the sign bit and specifies whether the output lies in the 
positive or negative portion of the curve. The next three bits 
define which of the 8 chords is to be selected. This three bit 
field has a value designated as N which is between and 7. 
The last four bits specify one of the sixteen steps and has a 
value equal to S. The control bit is the E/D signal which con- 
trols the output switching. 

The chord generator is the key element in the DAC. It must 
generate eight binary weighted chord currents and is similar 
to an 8-bit linear DAC. The detailed schematic, shown in Fig- 
ure 8, shows a master/slave ladder arrangement biased from 
a reference amplifier and transistor. The reference amplifier 
forces the base voltage of the reference transistor, (Q ), to 
the value required to sink the reference current. This voltage 
will bias the master ladder so that Q1 runs at 2'I REF , Q2 at 
l REF , Q3 at .5«I REF , and Q4A and Q4B at .25-l REF each. The 
slave array uses a binary weighted resistor array to generate 
the lower four chord currents by dividing the current from 
Q4B. An 8-bit linear DAC does not require the resistor array 
in the slave ladder but the Companding DAC does, in order to 
ensure 12-bit linearity in Chord 0. The LSB current in an 
AmDAC-08 is 8/nA ±4/j.A while the Chord current source in 
an Am6070 has a value of 8^A ±.5//.A. 








Ft R R 



Fig. 8. Chord Current Generator Diagram (Indicated current values correspond to the n-law DAC). 

3-102 



Companding DAC 



STEP 
BIT 

INPUT i 



5 




-GND 

"~is l E 



la' 



O.SfiA 
STEP) 



I 0.25„A 
| (1/2 STEP) 



16X ' "I 8X 


1 - 


1 " 


1 2L_J 


Mcn 








T EXAMPLE: l co = 8.25 M A 









(8.25 F A = 33 X 0.25«A) 



UC-026 



Fig. 9. /j-Law Step Current Generator. 




b.cva 

r (B STEPS) 



1 4.0mA 


| 2.0mA 


|(4 STEPS) 


| (2 STEPS) 



1.<VA 
KSTEP l N ) 



{(1/2 STEP) 



1(1/2 STEP) 





16X 


"1 " "1 


4X 


) » ^ 




1 • 






-n = 18m A 
ScA = 32 X 0.5„A) 











Fig. 10. A- Law Step Current Generator. 



The chord select inputs, B1, B2, B3, control a one of eight 
decoder that selects one of the chords, routes that chord cur- 
rent source to the step generator and switches all the lower 
order chord current sources to the pedestal generator. 

The step generator for the ju-law characteristic is shown in de- 
tail in Figure 9. This circuit divides the total chord current 
source, l CN , into 33 equal parts, and the step current value, 
l N , is equal to 2/33 of the chord current source. The 33 parts 
accommodate the required 1.5 step transition between 
chords, so that the total internal chord current source is equal 
to 16.5 steps. The step generator is similar to a four bit DAC 
but has six current source outputs to generate 8, 4, 2, 1, 1 
and 1/2 step currents. This current division can be done using 
emitter area scaling with enough accuracy to meet the 



monotonicity and linearity specifications without the use of 
emitter resistors. The four step bit inputs can choose from 
to 15 steps to be switched into the output summing network. 
The 1/2 step current is used as the encode offset current in 
the encode mode and will track the value of the chord current. 
When the transition to the next chord is made, the full chord 
current is switched to the pedestal generator causing a 
change in the output of 1.5 steps, i.e., from 15 steps to 16.5 
steps. The step selector uses a fully differential current switch 
to ensure high speed performance. This switch does not re- 
quire capacitive charging and discharging of low current 
nodes and has a nearly constant 40ns propagation delay over 
the dynamic range of the varying chord currents, from the first 
step current on chord of .5^A to the last step current on 
chord 7 of .5mA. 



3-103 



Companding DAC 



The output summing network sums the outputs of the pedes- 
tal generator, step generator, and encode current, and routes 
the current to the_output selected by the combination of SB 
and E/D. If the E/D input is high, the encode current, l EN , is 
summed with the step and pedestal currents_and is routed to 
I e<+). if SB is 1 , or to Ioe(-). if SB is 0. If E/D is low, only the 
step and pedestal currents are summed and sent to the out- 
put; the output current is routed to Iodi+) or Iod(-i depending 
on the state of SB. Only one output will be active and the 
other outputs will be in a high impedance, off, state. 



Generation of the >x-Law and A- Law Characteristics 

The ju.-law and A-law devices have similar characteristics 
which differ in the chords near zero. In the ^x-law device, the 
step size doubles when chord ends and chord 1 begins and 
the first step of chord zero is equal to zero, and the points for 
positive and negative zero are the same. In the A-law curve, 
the step size does not change between chord and chord 1 . 
The first two chords are colinear and the step size does not 
start doubling until chord 2. Additionally, the A-law curve has 
a 1/2 step offset at the zero point so that positive and nega- 
tive zero are not equal. These differences in the two com- 
panding laws are relatively minor and the two laws can be 
generated from the same integrated circuit with only minor 



The ^-law curve is generated using the earlier described step 
generator. If step size in the first chord is set to be .5fiA, the 
internal chord current source must be 8.25/iaA (16.5 x ,5;/.A). 
Each succeeding internal chord current source doubles in 
value so that the last two chord current sources are 528^A 
and 1056/u.A. The reference current is equal to 1/2 the largest 
current source, so the required reference current is 528/^A. 
The full scale output current can be calculated by summing all 
the internal current sources and subtracting 1 .5 steps from the 
most significant chord, because the full scale current output 
requires only 15 steps out of the available 16.5 steps to be 
switched into the output. This gives a full scale current of 
2007.75/iA. The Output current for any point on the com- 
panding curve can be calculated in terms of the internal chord 
source, 8.25M, and its step value, .5/j.A, using the follow- 
ing formula: 

l N , s = ((2 N - 1) • 8.25 M A) + (S • 2 N • 5/iA) 



where N represents the chord number and S the step 
number. The first term represents the pedestal current value; 
the second term the value of the steps in the selected chord. 

The A-law curve is generated by using the step generator 
shown in Figure 10. The internal chord current source is di- 
vided into 32 equal parts with current source values of 8, 4, 2, 
1,1/2 and 1/2 steps. The zero offset is generated by sum- 
ming a 1/2 step current with the output of the step generator 
independent of input code. The range of output values of the 
step generator is from 1/2 step to 15.5 steps, and the internal 
chord current source has a value equal to 16 steps. The 1.5 
step transition is accomplished by switching the total internal 
chord current source to the pedestal generator, i.e., adds 1/2 
step, (the encode current l EN ), and summing the 1/2 step 
offset current from the next higher chord, which is the same 
as one step on the lower chord. 

The A-law Companding DAC doubles the size of the chord 
current source l C o from the /i-law l co value by connecting the 
collector of Q8B to Q8A instead of its base as indicated in 
Figure 8, so that it is equal to the chord 1 current source. The 
reference current is adjusted to set the first chord step size to 
VA and the internal chord current source value to 16/xA. 
The last two chords will have internal current source values of 
512/xA and 1024/iA each. The reference current required to 
bias the chord generator is 512/iA. The full scale output cur- 
rent can be calculated by summing all the internal chord cur- 
rent sources and subtracting 1/2 step from the last chord, be- 
cause only 15.5 steps of the 16 steps in the last chord are 
switched to the output. The full scale current is nominally 
2016jiA. The current at any point on the A-law companding 
curve can be calculated by using the following formula: 



l N s = (2S+1) • .5/xA, for N=0, and 

= (2 N_1 • 16.5/xA) + (2 N_1 • S • VA), for N I 



Output Current Tables 

All output current values on the A-law transfer characteristic 
curve are higher than corresponding /it-law current values, be- 
cause of the larger step sizes in chord for the A-law charac- 
teristic. The different step sizes in chord were originally 
suggested by the International Telegraph and Telephone 



TABLE 1 

NORMALIZED A-LAW DECODER OUTPUT 
(SIGN BIT EXCLUDED) 



TABLE 2 

NORMALIZED M -LAW DECODER OUTPUT 
(SIGN BIT EXCLUDED) 



STEP IS] 



CHORD (CI 



33 
35 



102 
106 
110 
114 
118 
122 



132 
140 
148 
156 
164 
172 
180 
188 
196 
204 
212 
220 
228 
236 
244 



264 
280 
296 
312 
328 
344 
360 
376 
392 
408 
424 
440 
456 
462 



528 
560 
692 
624 
656 
688 
720 
752 
784 
816 



912 
944 
976 
1008 

32 



1056 
1120 
1184 
1248 
1312 
1376 
1440 
1504 
1568 
1632 
1696 
1760 
1824 
1888 
1952 



2112 
2240 
2368 
2496 
2624 
2752 
2880 
3008 
3136 
3264 
3392 
3B20 
3648 
3776 
3904 
4032 

128 











CHORD (C) 








STEP (S) 





































1 


2 


3 


4 


5 


6 


7 








33 


99 


231 


495 


1023 


2079 


4191 


1 


2 


37 


107 


247 


527 


1087 


2207 


4447 


2 


4 


41 


115 


263 


559 


1151 


2335 


4703 


3 


6 


45 


123 


279 


591 


1215 


2463 


4959 


4 


8 


49 


131 


295 


623 


1279 


2591 


5215 


5 


10 


53 


139 


311 


655 


1343 


2719 


5471 


6 


12 


57 


147 


327 


687 


1407 


2847 


5727 


7 


14 


61 


155 


343 


719 


1471 


2975 


5983 


8 


16 


65 


163 


359 


751 


1535 


3103 


6239 


9 


18 


69 


171 


375 


783 


1599 


3231 


6495 


10 


20 


73 


179 


391 


815 


1663 


3359 


6751 


11 


22 


77 


187 


407 


847 


1727 


3487 


7007 


12 


24 


81 


195 


423 


879 


1791 


3615 


7263 


13 


26 


85 


203 


439 


911 


1855 


3743 


7519 


14 


28 


89 


211 


455 


943 


1919 


3871 


7775 




30 


93 


219 


471 


975 


1983 


3999 


8031 


STEP SIZE 


2 






16 


32 


64 


128 


256 



3-104 



Companding DAC 



TABLE 3 

IDEAL A-LAW DECODER OUTPUT VALUES EXPRESSED 
IN dB DOWN FROM OVERLOAD LEVEL (+3dBmo) 



14 

15 



-69.11 
-59.57 
-55.13 
-52.21 
-50.03 
-48.28 
-46.83 
-45.59 
-44.50 
-43.54 
-42.67 
-41.88 
-41.15 
-40.48 
-39.86 
-39.28 



-38.74 
-38.23 
-37.75 
-37.29 
-36.85 
-36.44 
-36.05 
-35.67 
-35.31 
-34.96 
-34.62 
-34.30 
-33.99 
-33.69 
-33.40 
-33.12 



-35.72 
-32.21 
-31.73 
-31.27 
-30.83 
-30.42 
-30.03 
-29.65 
-29.29 
-28.94 
-28-60 
-28.28 
-27.97 
-27.67 
-27.38 
-27.10 



26.70 
-26.19 
-25.71 
-25.25 
-24 81 
-24.40 
- 24.00 

23.63 
-23.27 
-22.92 
-22.58 
-22.26 
-21.95 
-21.66 
-21.36 
-21.08 



-20.68 
-20.17 
-19.68 
-19.23 
-18.79 
-18.38 
-17.98 
-17.61 
-17.24 
-16.90 
-16.56 
-16.24 
-15.93 
-15.63 
-15.34 
15.06 



-14.66 
-14.15 
-13.66 
-13.21 
-12.77 
-12.36 
-11.96 
-11.59 
-11.22 
-10.88 
-10.54 
-10.22 
-9.91 
-9.61 
-9.32 
-9.04 



-8.64 
-8.13 
-7.64 
-7.19 
-6.75 
-6.34 
-5.94 
-5.57 
-5.20 
-4.86 
-4.52 
-4.20 
-3.89 
-3.59 
-3.30 
-3.02 



-2.62 
-2.11 
-1.62 
-1.17 
-0.73 
-0.32 
+0.08 
+ 0.46 
+ 0.82 
+ 1.16 
+ 1.50 
+ 1.82 
+ 2.13 
+ 2.43 
+2.72 
+ 3.00 



TABLE 4 

IDEAL /i-LAW DECODER OUTPUT VALUES EXPRESSED 
IN dB DOWN FROM OVERLOAD LEVEL (+3dBmo) 











CHORD 








STEP 




































O 


1 


2 


3 


4 


5 


6 


7 







-44.73 


-35.18 


-27.82 


-21 .20 


-14.90 


-8.74 


-2.65 


1 


-69.07 


-43.73 


-34.51 


-27.24 


-20.66 


-14.37 


-8.22 


-2.13 


2 


-63.05 


—42.84 


-33.88 


-26.70 


-20.15 


-13.87 


-7.73 


-1.65 


3 


-59.53 


—42.03 


-33.30 


-26.18 


-19.66 


-13.40 


-7.27 


-1.19 


4 


-57.03 


-41.29 


-32.75 


-25.70 


-19.21 


-12.96 


-6.83 


-0.75 


5 


-55.10 


-40.61 


-32.24 


-25.24 


-18.77 


-12.53 


-6.41 


-0.33 


6 


-53.51 


-39.98 


-31.75 


-24.80 


-18.36 


-12.13 


-6.01 


+0.06 


7 


-52.17 


-39.39 


-31 .29 


-24.39 


-17.96 


-11.74 


-5.63 


+0.44 


8 


-51.01 


-38.84 


-30.85 


-23.99 


-17.58 


-11.37 


-5.26 


+0.81 


9 


-49.99 


-38.32 


-30.44 


-23.61 


-17.22 


-11.02 


-4.91 


+ 1.16 


10 


-49.07 


-37.83 


-30.04 


-23.25 


-16.87 


-10.68 


-4.57 


+1.49 


11 


-48.25 


-37.37 


-29.66 


-22.90 


-16.54 


-10.35 


-4.25 


+ 1.82 


12 


-47.49 


-36.93 


-29.29 


-22.57 


-16.22 


-10.03 


-3.93 


+2.13 


13 


-46.80 


-36.51 


-28.95 


-22.25 


-15.91 


-9.73 


-3.63 


+2.43 


14 


-46.15 


-36.11 


-28.61 


-21 .94 


-15.61 


-9.43 


-3.34 


+2.72 


15 


-45.55 


-35.73 


-28.29 


-21 .63 


-15.32 


-9.15 


-3.06 


+3.00 



Consultive Committee (CCITT), in its recommendation for the 
encoding laws in Pulse Code Modulation communication sys- 
tems for voice frequency signals of commercial quality. 

This recommendation contains several different tables with in- 
formation for A-law and /x-law encoding requirements. The 
most important pair of tables contain all 128 distinctive de- 
coder output current values expressed in normalized units. 
The normalized current output values for A-law and jit-law 
Companding DACs are presented in Tables 1 and 2, respec- 
tively. Step of chord in the A-law table is equal to the 
value of one normalized unit, whereas the corresponding 
normalized zero current value in the /x-law table is zero. The 
actual size of this normalized unit is NOT REQUIRED TO BE 
THE SAME for A-law and for jit-law, and entries in Tables 1 
and 2 should not be used for any comparison of the two en- 
coding laws. Each table, independently, provides the infor- 
mation for a particular encoding law about required relation- 
ships between the output current magnitudes. In addition, the 
input data coding for Table 2, which contains entries for the 
/x-law normalized output values, is the one's complement of 
the input data codes suggested by the original CCITT and 
Bell D3 specification. However, data input coding shown in 
Tables 1 and 2 is accepted as standard input data coding in 
order to have consistent data coding for /a-law and A-law 
Companding DACs. The maximum normalized current values 
in Tables 1 and 2 are 4032 and 8031, respectively, and these 
values can be easily derived by summing all of the 128 nor- 
malized ! 

Additional conditions beyond the two maximum normalized 
values are related to the ratios, in /aA, between the 
amplitudes corresponding to full scale current values, and the 
amplitudes of output currents which are chosen as the refer- 
ence outputs for A-law and for /x-law decoding devices. These 
reference outputs are generated as sinusoidal waveforms of 
1kHz by applying a periodic sequence of eight 8-bit data 
words at the Companding DACs inputs at an 8kHz rate. 
These sequences are specified separately for both encoding 
laws. The signal level at the peaks of these reference 
sinusoidal waveforms is chosen as the reference OdB level. 
This level is implied to be the same for both encoding laws. 
The dB levels, calculated by using the peaks of the 1kHz 
sinusoidal waveforms with amplitudes which correspond to the 



theoretical maximum output current values, are specified to be 
+3.14dB and +3.17dB above the common reference level for 
the A-law and /x-law decoding devices, respectively. The 
small difference in the specified theoretical maximum output 
current levels implies a very small difference between actual 
full scale current values for A-law and /n-law decoders. In 
practice, the actual level for the full scale output current val- 
ues for both laws is set to be +3.00dB above the reference 
OdB level. The ideal decoder output values expressed in dB 
down from the full scale current output for A-law and /x-law 
are presented in Tables 3 and 4. The reference OdB level can 
be found in these tables between steps 5 and 6 on chord 7. 
Comparison of the numbers corresponding to step 1 in chord 
shows a difference between the two encoding laws with re- 
spect to the output dynamic ranges. The output dynamic 
range is 62.57dB for A-law, ( + 3.00dB to -59.57dB), and 
72.07dB for M -law, ( + 3.00dB to -69.07dB). 

In order to make the electrical designs of A-law and /--law 
Companding DACs as similar as possible, the normalized unit 
value of current in Table 1 , A-law table, is chosen to be 0.5/xA 
and the normalized unit current quantity in Table 2, /±-law 
table, is chosen to be 0.25/iA. These different "unit" values 
will cause the steps in chord for A-law Companding DACs 
to be twice as large as the corresponding ^-law device step 
sizes. Consequently, the ideal full scale absolute current val- 
ues corresponding to 4032 and 8031 normalized units are 
2016/j.A for A-law and 2007.75/- A for /i-law DACs. Tables 5 
and 6 contain all 128 absolute decoder output current values 
in ^A. These tables can be further expressed in terms of per- 
cent of full scale current output, which may be important for 
some "percentage" oriented applications. Tabulated sum- 
maries of step and chord endpoint sizes which can be ex- 
tracted from Tables 1 through 6 are presented in Tables 7 
and 8. The last column in these tables points out that the best 
resolution and accurac f ,e achieved in chord of the Com- 
panding DACs transfer function. 

The output current values presented in Tables 5 and 6 are 
ideal output currents with ideal reference currents of 528/xA 
and 512^iA. respectively. The output current deviations for the 
communication application of Companding DACs are specified 
by the compandor tracking system requirements which are 
illustrated for both decoders in Figures 11 and 12. In both fig- 
ures a dotted line represents a total gain deviation, in dB, for 



3-105 



Companding DAC 



TABLE 5 

IDEAL A-LAW DECODER OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED) 



STEP 


CHORD 


U 


1 


m 






E 
W 


c 
O 


i 





.500 


16.500 


33.000 


66.000 


132.00 


264.00 


528.00 


1056.00 


1 


1.500 


17.500 


35.000 


70.000 


140.00 


280.00 


560.00 


1 120.00 


2 


2.500 


18.500 


37.000 


74.000 


148.00 


296.00 


592.00 


1184.00 


3 


3.500 


19.500 


39.000 


78.000 


156.00 


312.00 


624.00 


1248.00 


4 


4.500 


20.500 


41.000 


82.000 


164.00 


328.00 


656.00 


1312.00 


5 


5.500 


21.500 


43.000 


86.000 


172.00 


344.00 


688.00 


1376.00 


6 


6.500 


22.500 


45.000 


90.000 


180.00 


360.00 


720.00 


1440.00 


7 


7.500 


23.500 


47.000 


94.000 


188.00 


376.00 


752.00 


1 504.00 


8 


8.500 


24.500 


49.000 


98.000 


196.00 


392.00 


784.00 


1568.00 


9 


9.500 


25.500 


51.000 


102.000 


204.00 


408.00 


816.00 


1632.00 


10 


10.500 


26.500 


53.000 


106.000 


212.00 


424.00 


848.00 


1696.00 


11 


11.500 


27.500 


55.000 


110.000 


220.00 


440.00 


880.00 


1760.00 


12 


12.500 


28.500 


57.000 


114.000 


228.00 


456.00 


912.00 


1824.00 


13 


13.500 


29.500 


59.000 


118.000 


236.00 


472.00 


944.00 


1888.00 


14 


14.500 


30.500 


61.000 


122.000 


244.00 


488.00 


976.00 


1952.00 


15 


15.500 


31.500 


63.000 


126.000 


252.00 


504.00 


1008.00 


2016.00 


STEP 
SIZE 


1 


1 


2 


4 


8 


16 


32 


64 



TABLE 6 

IDEAL M -LAW DECODER OUTPUT CURRENT IN MICROAMPS (SIGN BIT EXCLUDED) 



STEP 


CHORD 





1 


2 


3 


4 


5 


6 


7 





.000 


8.250 


24.750 


57.750 


123.75 


255.75 


519.75 


1047.75 


1 


.500 


9.250 


26.750 


61.750 


131.75 


271.75 


551.75 


1111.75 


2 


1.000 


10.250 


28.750 


65.750 


139.75 


287.75 


583.75 


1175.75 


3 


1.500 


11.250 


30.750 


69.750 


147.75 


303.75 


615.75 


1239.75 


4 


2.000 


12.250 


32.750 


73.750 


155.75 


319.75 


647.75 


1303.75 


5 


2.500 


13.250 


34.750 


77.750 


163.75 


335.75 


679.75 


1367.75 


6 


3.000 


14.250 


36.750 


81.750 


171.75 


351.75 


711.75 


1431.75 


7 


3.500 


16.250 


38.750 


85.750 


179.75 


367.75 


743.75 


1495.75 


8 


4.000 


16.250 


40.750 


89.750 


187.75 


383.75 


775.75 


1559.75 


9 


4.500 


17.250 


42.750 


93.750 


195.75 


399.75 


807.75 


1623.75 


10 


5.000 


18.250 


44.750 


97.750 


203.75 


415.75 


839.75 


1687.75 


11 


5.500 


19.250 


46.750 


101.750 


211.75 


431.75 


871.75 


1751.75 


12 


6.000 


20.250 


48.750 


105.750 


219.75 


447.75 


903.75 


1815.75 


13 


6.500 


21.250 


50.750 


109.750 


227.75 


463.75 


935.75 


1879.75 


14 


7.000 


22.250 


52.750 


113.750 


235.75 


479.75 


967.75 


1943.75 


15 


7.500 


23.250 


54.750 


117.750 


243.75 


495.75 


999.75 


2007.75 


STEP 
SIZE 


.5 


1 


2 


4 


8 


16 


32 


64 



3-106 



DAC 



TABLE 7 

A- LAW DECODER STEP SIZE AND CHORD SIZE SUMMARY 



















Resolution 




Step Size 


Chord Endpoints 


Step Size 


Chord Endpoints 


Step Size 


Chord Endpoints 


Chord Endpoints 


& Accuracy 




formalized 


Normalized 


in /xA with 


in mA with 


as a % of 


as a % 


in dB Down 


of Equivalent 


Chord t 


o Full Scale 


to Full Scale 


2016mA F. S. 


2016mA F. S. 


Full Scale 


of Full Scale 


from Full Scale 


Binary DAC 





2 


31 


1.0 


15.5 


0.05% 


0.775! 


-42.28 


Sign + 11 Bits 


i 


2 


63 


1.0 


31.5 


0.05% 


1.56% 


-36.12 


Sign + 11 Bits 


2 


4 


126 


2.0 


63.0 


0.1% 


3.13% 


-30.10 


Sign + 10 Bits 


3 


8 


252 


4.0 


126.0 


0.2% 


6.25% 


-24.08 


Sign + 9 Bits 


4 


16 


504 


8.0 


252.0 


0.4% 


12.5% 


-18.06 


Sign + 8 Bits 


5 


32 


1008 


16.0 


504.0 


0.8% 


25.0% 


-12.04 


Sign + 7 Bits 


6 


64 


2016 


32.0 


1008.0 


1.69! 


50.0% 


-6.02 


Sign + 6 Bits 


7 


128 


4032 


64.0 


2016.0 


3.2% 


100% 





Sign + 5 Bits 



TABLE 8 

/i-LAW DECODER STEP SIZE AND CHORD SIZE SUMMARY 



Chord 


Step Size 
Normalized 
to Full Scale 


Chord Endpoints 
Normalized to 
Full Scale 


Step Size 
in fiA with 
2007.75mA FS 


Chord Endpoints 

in fj-A with 
2007.75mA FS 


Step Size 
as a % of 
Full Scale 


Chord Endpoints 
as a % of 
Full Scale 


Chord Endpoints 

in dB Down 
from Full Scale 


Resolution & 
Accuracy of 
Equivalent 
Binary DAC 







2 


30 


0.5 


7.5 


0.025% 


0.37% 


-48.55 


Sign + 12 Bits 


1 




4 


93 


1 .0 


23.25 


0.05% 


1.16% 


-38.73 


Sign + 11 Bits 


2 




8 


219 


2 


54.75 


0.1% 


2.73% 


-31.29 


Sign + 10 Bits 


3 




16 


471 


4.0 


117.75 


0.2% 


5.86% 


-24.63 


Sign + 9 Bits 


4 




32 


975 


8.0 


243.75 


0.4% 


12.1% 


-18.32 


Sign + 8 Bits 


5 




64 


1983 


16.0 


495.75 


0.8% 


24.7% 


-12.15 


Sign + 7 Sits 


6 




128 


3999 


32.0 


999.75 


1.6% 


49.8% 


-6.06 


Sign + 6 Bits 


7 




256 


8031 


64.0 


2007.75 


3.2% 


100% 





Sign + 5 Bits 



O 1-75 



CCITT A-LAW 
SPECIFICATION 
(MAXIMUM) 



Am6073 
SPECIFICATION 
(MAXIMUM) 



-60 -55 -50 



INPUT SIGNAL LEVEL — dBmo 



various signal levels which can be distributed over the en- 
coder and decoder portions of a "one way" communication 
system. It is understood that encoder and decoder system 
portions are implemented with corresponding Companding 
DACs. For the Bell D3 system jn-law tracking specification, 
the -37dBmo and -50dBmo output current levels can be 
found between steps 11 and 12 on chord 1, and steps 8 and 
9 on chord 0, respectively. For the CCITT A-law compandor 
tracking specification, the -40dBmo, -50dBmo, and 
-55dBmo output current levels can be found in the corre- 
sponding A-law tables between steps 13 and 14 on chord 0, 
steps 4 and 5 on chord 0, and steps 2 and 3 on chord 0, re- 
spectively. Conversion of the requirements imposed by Fig- 
ures 11 and 12 to absolute current values produces corre- 
sponding absolute decode output current tables with 
minimum, ideal and maximum values specified for each step. 





















| BELL D3 SYSTEM 
1 SPECIFICATION 
| (MAXIMUM) 










1 

-.1 






























Am6072 
SPECIFICATION 
(MAXIMUM! 







-40 -37 -30 -20 
INPUT SIGNAL LEVEL - 



Fig. 11. CCITT A-Law Compandor Tracking Specification. Fig. 12. Bell D3 System Compandor Tracking Specification. 

3-107 




TABLE 9 

ABSOLUTE DECODER OUTPUT CURRENT LIMITS IN fiA 
CONFORMING TO BELL D3 COMPANDOR TRACKING SPECIFICATIONS 



STEP 


CHORD NO. 


NO. 





1 


2 


3 


4 


5 


6 


7 





-.250 
.000 
.250 


7.789 
8.250 
8.739 


24.048 
24.750 
25.473 


56.112 
57.750 
59.436 


120.24 
123.75 
127.36 


248.49 
255.75 
263.22 


505.00 
519.75 
534.93 


1018.02 
1047.75 
1078.34 


1 


.250 
.500 
.750 


8.733 
9.250 
9.798 


25.991 
26.750 
27.531 


59.998 
61.750 
63.553 


128.01 
131.75 
135.60 


264.04 
271.75 
279.69 


536.10 
551.75 
567.86 


1080.21 
1111.75 
1144.21 


2 


.750 
1.000 
1 .250 


9.677 
10.250 
10.857 


27.934 
28.750 
29.590 


63.885 
65.750 
67.670 


135.79 
139.75 
143.83 


279.59 
287.75 
296.15 


567.19 
583.75 
600.80 


1142.39 
1175.75 
1210.08 


3 


1 .250 
1.500 
1.750 


10.621 
1 1 .250 
11.917 


29.878 
30.750 
31 .648 


67,771 
69.750 
71 .787 


143.56 
147.75 
152.06 


295.13 
303.75 
312.62 


598.28 
615.75 
633.73 


1204.58 
1239.75 
1275.95 


4 


1 .750 
2.000 
2.250 


1 1 .565 
12.250 
1 2.976 


31 .821 
32.750 
33.706 


71 .658 
73.750 
75.904 


151.33 
155.75 
160.30 


310.68 
319.75 
329.09 


629.37 
647.75 
666.66 


1266.76 
1303.75 
1341.82 


5 


2.250 
2.500 
2.750 


12.509 
13.250 
14.035 


33.764 
34.750 
35.765 


75.544 
77.750 
80.020 


159.10 
163.75 
168.53 


326.22 
335.75 
345.55 


660.46 
679.75 
699.60 


1328.94 
1367.75 
1407.69 


6 


2.750 
3.000 
3.250 


1 3.453 
14.250 
15.094 


35.707 
36.750 
37.823 


79.431 
81.750 
84.137 


1 66.88 
171.75 
1 7G 77 


341 .77 
351 .75 
362.02 


691 .56 
711.75 
732.53 


1 39 1.13 
1431 .75 
1473.56 


7 


3.250 
3.500 
3.750 


14.397 
15.250 
16.154 


37 .651 
38.750 
39.882 


83 31 7 
85.750 
88.254 


1 74 65 
179.75 
185.00 


357 32 
367.75 
378.49 


722 65 
743.75 
765.47 


1 453.31 
1495.75 
1539.43 


8 


3.750 
4.000 
4.250 


1 5.341 
16.250 
17.213 


39.594 
40.750 
41.940 


87 204 
89.750 
92.371 


1 82 42 
187.75 
193.23 


372 86 
383.75 
394.96 


753 74 
775.75 
798.40 


1515 50 
1559.75 
1605.30 


9 


4.248 
4.500 
4.767 


1 6.285 
17.250 
18.272 


41 .537 
42.750 
43.998 


91 .090 
93.750 
96.488 


1 90.20 
195.75 
201.47 


388.41 
399.75 
411.42 


784.83 
807.75 
831.34 


1 577.68 
1623.75 
1671.16 


10 


4.720 
5.000 
5.296 


17.229 
18.250 
19.331 


43.480 
44.750 
46.057 


94.977 
97.750 
100.604 


197.97 
203.75 
209.70 


403.95 
415.75 
427.89 


815.92 
839.75 
864.27 


1639.87 
1687.75 
1737.03 


11 


5.192 
5.500 
5.826 


18.173 
19.250 
19.812 


45.424 
46.750 
48.115 


98.863 
101.750 
104.721 


205.74 
211.75 
217.93 


419.50 
431.75 
444.36 


847.02 
871 .75 
897.21 


1702.05 
1751.75 
1802.90 


12 


5.664 
6.000 
6.356 


19.675 
20.250 
20.841 


47.367 
48.750 
50.174 


102.750 
105.750 
108.838 


213.52 
219.75 
226.17 


435.05 
447.75 
460.82 


878.11 
903.75 
930.14 


1764.23 
1815.75 
1868.77 


13 


6.136 
6.500 
6.885 


20.647 
21 .250 
21.871 


49.310 
50.750 
52.232 


106.636 
109.750 
112.955 


221 .29 
227.75 
234.40 


450.59 
463.75 
477.29 


909.20 
935.75 
963.07 


1826.42 
1879.75 
1 934.64 


14 


6.608 
7.000 
7.415 


21.619 
22.250 
22.900 


51.253 
52.750 
54.290 


1 10.523 
1 1 3.750 
117.072 


229.06 
235.75 
242.63 


466.14 
479.75 
493.76 


940.29 
967.75 
996.01 


1888.60 
1943.75 
2000.51 


15 


7.080 
7.500 
7.944 


22.590 
23.250 
23.929 


53.197 
54.750 
56.349 


114.409 
117.750 
121.188 


236.83 
243.75 
250.87 


481.68 
495.75 
510 23 


971.39 
999.75 
1028.94 


1950.79 
2007.75 
2066.38 


STEP 
SIZE 


.5 


1 


2 


4 


8 


16 


32 


64 



The decoder output current values which comply with the Bell 
D3 compandor tracking requirements are presented in Table 
9. A similar table can be generated for the CCITT A-law com- 
pandor tracking specification. The corresponding encode out- 
put values can be derived from the decode output values by 
adding a half a step to all entries in a given decode table. The 
specified limit values include the combined effects of chord 
end point deviations, step nonlinearity. encode output errors, 
full scale current deviation from ideal, full scale symmetry er- 
ror, zero scale current error, full scale drift, and output imped- 
ance change over the specified voltage compliance and 
temperature ranges. The adjacent step current levels in Table 



9 for any particular Companding DAC will not overlap, as 
might be implied from the presented minimum and maximum 
values, because the device is guaranteed to be monotonia 

If the decode output limits for the /x-law Companding DAC are 
specified to be ±1/2 step from the ideal values, Table 9 can 
be replaced by a similar table. The most important difference 
between the two tables would be found in the limit values cor- 
responding to the lower step current values in chords 1 
through 7. The approximate representations of ±1/2 step, ±1 
step limits and the corresponding Bell D3 compandor tracking 
limits in Table 9 are illustrated in Figure 13. 



3-108 



Companding DAC 




Fig. 13. Output Current Limit Diagrams for D3, ±1/2 Step, and ±1 Step Tolerance Specifications. 



Parametric Analysis and Recommendations 

A detailed specification for a digital-to-analog converter should 
include information about important DAC parameters such as 
resolution, monotonicity, dynamic range, settling time, non- 
linearity, full scale and zero scale current errors, gain error, 
output voltage compliance, input, output and reference signal 
levels, operating temperature range, power supply range and 
power dissipation. 

The resolution of a DAC is determined by the maximum 
number of digital input combinations which can be used to 
generate analog output signals. The resolution for Com- 
panding DACs with sign-plus-7 bit digital data input signals is 
±128 steps. A converter is monotonic if its analog output al- 
ways increases with an increase in the digital value of the 
input data code. Monotonicity for the Am6070/71/72/73 de- 
vices, is guaranteed over the full operating temperature range 
and for both groups of 128 steps. Two parameters which are 
used to describe nonlinear errors in a DACs transfer function 
are the DAC s nonlinearity and the differential nonlinearity er- 
ror. The nonlinearity of a Companding DAC is defined as the 
maximum deviation of the actual output values from an ideal 
piece-wise linear characteristic calculated from measurements 
of the actual full scale and zero scale current values. These 
two current measurements can be used to compute the cor- 
responding theoretical chord endpoint values, and nonlinearity 
is measured as the difference between this calculated transfer 
characteristic and the actual current values at the output of 
the DAC. The differential nonlinearity of the device is a mea- 
sure of how much any single step current value varies with 
respect to its theoretical value, (calculated from the actual full 
scale output current). Differential nonlinearity of ±1/2 step will 
ensure monotonic behavior. These errors and all other trans- 
fer function related errors are specified for the Am6070 Com- 
panding DAC Family by the limit current values in the corre- 
sponding Absolute Decoder Output Current Level Table. 

The DACs current outputs have a very high impedance, and 
the output current will not change its value significantly with 
changes in the applied voltage at the DACs outputs. The out- 
put voltage compliance range is defined as the maximum 
range of voltages, at the DACs output, that can be sustained 
while meeting the output current specifications. The absolute 



maximum output voltage swing, (l REF = 528/xA), is specified 
between V- plus 10V and V- plus 36V, where V- is the 
Companding DACs negative power supply. The maximum 
range for the reference inputs V R( _) and V RI+) is specified to 
be between the V- and V+ power supply values. The 
maximum power supply range, V+ to V-, is specified at 36V, 
and maximum power dissipation for temperatures less than 
100°C is rated at 500mW. 

The settling time for a DAC is defined as the elapsed time, 
after an input code transition, required for the DACs output to 
reach a final value within specified limits. These limits are 
generally ±1/2 of the corresponding step current value. The 
settling time is usually specified for the input code transition 
from zero scale to full scale value, and for the Companding 
DAC Am6070 family the typical value is 300ns. However, this 
is not the worst case transition. Because of the different step 
sizes, the output current settling error band changes as the 
chord current changes, becoming smaller for lower chords. 
Settling times in chord 7 are measured when the output set- 
tles within ±32/iA of its final value, while settling times in 
chord are measured when the output settles to within 
±.25/iA of it's final value. The worst case transition is, there- 
fore, the transition from full scale current down to zero scale 
current value, and requires a settling time of 4/i.s for /i-law 
DACs and 2.5jts for A-law DACs. 

The currents of each of the four Companding DACs analog 
outputs can be measured using the circuit shown in Figure 
14. This circuit contains 4 resistors, R1, R2, R3, R4, and two 
operational amplifiers, A1 and A2. Resistor tolerances of 0.19J 
give 0.1 9f output measurement error (approximately 2^A at 
full scale). The input offset current of the operational amplifier 
also increases the output measurement error. This error is 
most significant near zero scale. The Ami 01 A and Am308 
devices, for example, may be used for A1 and A2, since their 
maximum offset currents which would add directly to the 
measurement error, are only 10nA and 1nA, respectively. The 
input offset voltage of the amplifiers, with output resistor val- 
ues of 2.5ka, also contributes to the output measurement 
error by a factor of 400nA for every mV of offset voltage. 
Therefore, to minimize this error, the offset voltages of A1 and 
A2 should be nulled. 



3-108 



Companding DAC 



B 7 B 6 B 5 B„ B 3 B 2 B, SB E/D 



U 3 2 1 



DEVICE 
UNDER TEST 
COMPANDING DAC 



f R REF- 
20kft 




R,-R 2 -R 3 -R 4 -2.5kS2s0.1% 




Eoi 



LINE SELECTION TABLE 



TEST 






OUTPUT 


GROUP 


E/D 


SB 


MEASUREMENT 


1 


1 


1 


'OE <+> 


<E 0l /Ril 


2 


1 





"OE <-) 


<E 01 /R 2 ( 


3 





1 


loo W 


{E 02 /R 3 ) 


4 








"OD (-> 


(E02' R 4) 



Fig. 14. Companding DAC Output Current DC Test Circuit. 



The recommended operating range for the reference current 
l REF is 0.1mA to 1.0mA. The full scale output current, l FS , is a 
linear function of the reference current, and may be approx- 
imated using the equation l FS = 3.9«I REF . This tight relation- 
ship alleviates the requirement for trimming the l REF current if 
the Rref resistors' values are within ±1% of the calculated 
value. Lower values of l REF will reduce the negative power 
supply current, and will increase the reference amplifier nega- 
tive common mode input voltage range. However, the device 
accuracy specifications are not guaranteed at reference cur- 
rents below 0.5mA. 

The ideal value for the reference current, (V REF /R REF ), is 
528/xA for jt-law and 512/xA for A-law Companding DACs. 
The corresponding ideal full scale decode current values are 
2007.75^A and 2016jxA, respectively. A percentage change 
from the ideal l REF value produced by changes in the V REF or 
R REF values produces the same percentage change in the 
decode and encode output current values. The positive volt- 
age supply, V+, may be used, with certain precautions, for 
the positive reference voltage. In this case, the reference re- 
sistor R REF(+) should be split into two resistors and their junc- 
tion bypassed to ground with a capacitor of about 0.01 nF. 
The total resistor value should provide the required reference 
current. The R REF( _) resistor value should approximately 
equal the R REF(+) value in order to compensate for errors 
caused by the reference amplifier's input bias current. 

An alternative to the positive reference voltage biasing is the 
application of a negative voltage to the V R( _) terminal through 
the resistor R REF( _) with the R REF(+) resistor tied to ground. 
The advantage of this arrangement is the presence of very 
high impedance at the V R( _) terminal while the reference cur- 
rent flows from ground through R REF(+) into the V R(+) termi- 
nal. 

The Companding DAC can be used as a multiplying DAC by 
varying the reference current. It is important that the reference 
current have a DC component that guarantees an uninter- 
rupted flow of current INTO the V R(+) terminal. The input ref- 
erence amplifier has sufficient bandwidth and slew rate, 
(0.12mA7/iS minimum), to handle small signal inputs up to 5% 
of reference current at frequencies up to 500KHz, and large 
signal inputs of up to 50% of reference current at frequencies 
up to 80kHz. 



The Companding DAC has a wide output voltage compliance 
suitable for driving a variety of loads. Using the ideal recom- 
mended value for l REF and V- = -15V, the positive voltage 
compliance limit is +18V and the negative voltage compliance 
limit is -5.0V. For other values of l REF and V-, the negative 
voltage compliance limit, V c<-). may be calculated as fol- 
lows: 

Voc(-) = (V-) + 2 (l REF • 1.55kf!) + 8.4V, 

where 1 .55kfi and 8.4V are equivalent worst case values for 

the Companding DAC. 

The V LC input controls the input logic threshold voltage, allow- 
ing the device to interface with various logic families. This 
input should be placed at a potential which is 1 .4V below the 
desired logic input switching threshold. Two external discrete 
circuits which provide this function for non-TTL driven inputs 
are shown in Figure 15. For TTL-level logic inputs, the V LC 
input should be grounded. If negative voltages are applied at 
the digital logic inputs, they must have a value which is more 
positive than -5V. 



CMOS. HTL. NMOS 




TO PIN 10 

"V LC 



Notes: 1. Set the voltage "A" to the desired logic input switch- 
ing threshold. 

2. Allowable range of logic threshold is typically -5V to 
+ 1 3.5V when operating the companding DAC on ± 
15V supplies. luj.ojj 



Fig. 15. Interfacing Circuits for ECL, 
CMOS, HTL and NMOS Logic Inputs. 



3-110 



With the V- voltage between -15V and -11V, the V oc( _) 
value, the input reference common mode voltage range, and 
the log c input negative voltage range are reduced by an 
amount equivalent to the difference between -15V and the 
V- value chosen. With V+ between +5V and +15V, the re- 
ference amplifier common mode positive voltage range and 
the V LC input values are reduced by an amount equivalent to 
the difference between +15V and the V+ value chosen. 

TYPICAL CIRCUIT APPLICATIONS 

Basic Circuit Connections 

The Companding DAC belongs to the class of multiplying D to 
A converters with true current outputs. The input reference 
current can be generated by a unipolar constant reference 
voltage source or by a bipolar AC reference voltage. The 
applied bipolar reference source usually modulates the refer- 
ence current, l REF , supplied from the constant reference volt- 
age as shown in Figure 16. Figure 16a shows a high input 
impedance configuration where the bipolar input signal V, N 
modulates the voltage level at the V R(+) input by forcing the 
voltage across R REF to be V REF - V m , which in turn modifies 
Iref- Figure 16b shows low input impedance connections, 
where l REF equals the sum of the DC reference current from 
V REF and the AC input current from V m . For both low imped- 
ance and high impedance connections, the minimum ref- 
erence current value at the reference input, V R(+) should be 
at least 0.1mA and the maximum value should not exceed 
1.0mA. 

The wide output voltage compliance range, (-5V to +18V 
with Ir E f = 528^A and V- = -15V), allows a variety of 
loads to be driven. Two typical connections are shown in Fig- 
ure 17. Voltage output relationships for single ended and dif- 
ferential resistive output connections are described in the out- 
put voltage table of Figure 17a. The reference current in this 
resistive load example is set to be 528|U,A (^-law Companding 
DAC). The resulting negative voltage generated by the cur- 



Companding DAC 



DIGITAL INPUTS 




>REF = ( V REF - V| N )/R R EF + 





9 


8 


7 


6 


5 


4 


3 


2 


1 


B 7 E 


6 B 5 B 4 a 3 B 2 B 1 s 


E E 


□ f»N 


V R(+> 
















OE [_ 






COMPANDING DAC 






VR(- 


































v L c <->> 



r 




a. High Input Impedance Connection. 



DIGITAL INPUTS 



<\j Wv * ^ 



REF — 

i REF = V| N /n IN + v ref /r ref+ 
R REF - = (Rref+ • Rin>/(Href+ + Rin) 

'fS~ 4 !rEF 




B 7 Bg Bg B 4 B 3 B 2 B-, SB E/D (+) 

'.w 

COMPANDING DAC 




b. Low Input Impedance Connection. 



Fig. 16. Companding DAC's Multiplying Connections. 

rents at the outputs A, B, and C, does not exceed the 
minimum value of -5V, which corresponds to the lower limit 
of the output voltage compliance range. In the example with 
balanced load connections, the sum of the common mode 
voltage, V CM , and the differential voltage across the load 
should also be within the -5V and +18V output voltage com- 
pliance limit. 




DIGITAL INPUTS 



B e B 5 B 4 B 3 B 2 B, SB E/D 




4.98 4 * 



INPUT CODE 
(E/D, SB, B-! B 7 ) 


OUTPUT VOLTAGE (V) 


"A" 


"B" 


"C" 


DIFF 


10 111 1111 
10 110 1111 
10 000 0000 




+5.02 
+ 10.00 


N/A 


N/A 


N/A 


01 111 1111 




-5.00 


+5.00 


-10.00 


01 110 1111 




+0.02 


+5.00 


-4.98 


01 000 0000 




+ 5.00 


+5.00 







N/A 








00 000 0000 




+5.00 


+5.00 





00 110 1111 




+5.00 


+0.02 


+4.96 


00 1 1 1 1111 




+5.00 


-5.00 


+ 10.00 



a. Resistive Output Connections. 



DIGITAL INPUTS 



R REF- 
20kll 





9 


8 


7 


6 


5 


4 


3 


2 


1 




1 


B7 8 

V R (+) 


6 B5 B4 B3 B2 B1 S 


Bt "V, 












Am6070 










Vr 
V 


-) 
















( 

OD 


\. 12 








V+ 






V,r'-' 



T 



"CM 



— -1SV +15V 

b. Balanced Load Connections. 



Fig. 17. Companding DAC's Output Connections. 

3-111 



Companding DAC 



Operational amplifiers and/or comparators can be driven by 
Companding DACs. The circuits shown in Figure 18 demon- 
strate various voltage ranges which can be achieved at the out- 
puts of operational amplifiers. The circuit in Fig_ure 18a pro- 
vides OV at the op-amp output whenever the E/D inpuHs set 
to logic 1. When the circuit is in the decode mode, E/D = 
the output voltage polarity is determined by the sign bit 
input level. With the sign bit set low, the Iod(-) output is ac- 
tive and the corresponding full scale output current, l FS = 
2mA, will generate a maximum negative voltage of -5V at the 
op-amp's positive input. The chosen resistor values and their 
connections provide the op-amp with a gain of 2 and a 
maximum negative output voltage of -10V. With the sign bit 
set high the Iodi+) output is active and the op-amp's negative 
input will be held at virtual ground. With a full scale current of 
2mA flowing into the Iodi+i P' n > ,ne op-amp will act as a 
transconductance amplifier supplying 2mA to the Iod(+) P' n 
via the 5kfi feedback resistor. This current will generate a 
maximum of +10V at the output, which will make the total 
output voltage swing between -10V and +10V. The circuit in 
Figure 18b similarly provides a voltage swing between -5V 
and +5V across the output capacitor. The output dynamic 
range expander circuit connections, shown in Figure 19, ex- 
tend the ju-law Companding DACs dynamic range from 72dB 
to 78dB. The A-law Companding DACs dynamic range can 
be similarly increased from 62dB to 66dB. In this circuit, the 



outputs loo(+) and 'oe(+) are_tied together, and Iodi-i an d 
Iqe(-) are tied together; the E/D input is used as a fifth step 
which represents the least significant digital data input, and 
provides the desired interleaving between the encode and de- 
code current levels. Each chord now contains 32 uniform 
steps, with the smallest step size value 0.25jiiA and the 
largest value 32/u.A. The resulting full scale current is equal to 
the corresponding full scale encode current value, and the 
ratio between the full scale current value and the smallest cur- 
rent step value, l FS /0.25, exceeds 8000 for the /x-law Com- 
panding DAC. The smallest and the largest current step sizes 
will generate 0.625mV and 80mV changes, respectively, at 
the op-amp output. 

Digital inputs SB and E/D can be used together with data 
inputs B1 through B7 to provide an output multiplexing capa- 
bility when connected as shown in Figure 20. The logarithmic 
digital attenuator circuit combines the companding DACs mul- 
tiplying capabilities with the multiplexing function which is 
accomplished by using the SB and E/D inputs as channel 
select inputs. The analog signal, V !N , applied at the V R( _) 
reference input can be attenuated by approximately 0.3dB per 
step and 6dB per chord, throughout most of the output 
dynamic range. The SB and E/D inputs provide signal switch- 
ing combinations which will multiplex the attenuated analog 
signal into four different analog channels. 



tlOV INPUT 




DIGITAL INPUTS 



B 7 B 6 B 5 B 4 B 3 B 2 B, SB E/D | + )\ 
'OE , 



— -15V 




LIC-037 



a. 10V Range Encode/Decode Connections. 



V REF DIGITAL INPUTS 




ANALOG 
OUTPUT 

±5.0V 



b. Compliance Extension Using AC Coupled Output. 



Fig. 18. Some Output Voltage Expansion Schemes. 

3-112 



Companding DAC 



•:rr 

>20k 



DIGITAL INPUTS 



B 7 B 6 B 5 B 4 B 3 B 2 Bt SB E/D 

'refoj 

companding dac 

|Am6070j 



— -15V 





ANALOG 
" OUTPUT 



IDEAL VALUES: l REF = V REF fl REF . 528^A 

l FS = 2007.75tiA - 32fiA 2039.75^A 



Fig. 19. Output Dynamic Range Expander. 



ATTENUATION 
■ 6dB/CHORD CHANNEL 
■-.MB/STEP SELECT 



<>_L 



9|al 7 



Lihl 



B7 B6 B5 B4 B3 B2 B1 SB E D 

'OE(+)> 



COMPANDING 
DAC 



V- V+ V, 



13 18 1 





FIRST 

-| | CHANNEL 

OUTPUT 



3 CHANNEL 



■ 3RD CHANNEL 




FOURTH 
- CHANNEL 
OUTPUT 



Fig. 20. Logarithmic Digital Attenuator. 



For applications where the output dynamic range is to be 
smaller than 78dB, the circuit connection shown in Figure 21 
can be used. With given V REF and V, N values, there are three 
resistor values, R REF , r 1> and R2, which need to be deter- 
mined. The starting assumption is that a maximum gain of 
unity from V, N to V 0UT , (OdB), is achieved with all digital 
inputs set to logic 1. The digital inputs all set to logic will 
determine the minimum gain of the circuit and consequently 
the desired output dynamic range. Considering the currents 
flowing through resistors R1, R2, and R RE f. and the DAC's 
output with digital inputs at all 1's, the following relationships 
can be established: 

lp.1 = V'out/R1 = 'OUT + Ir 2 ; Iout - 3.8 l REF ; l R2 = V, N /R2; 
l REF = (V REF - V IN )/R REF (1) 

The relationship between output 
and input voltages, V REF and V, N , 
lows: 

V' 0UT = 3.8 (R1/R REF ) V REF - [3.8(R1/R REF ) + R1/R2] • V IN 

(2) 

Vqut = "[3.8 (R1/R REF ) + R1/R2] • V IN 



In order to have unity gain, V 0UT /V| N = 1, the coefficient for 
V, N in the equations (2) must also be 1 : 



-[3.8 (R1/R REF ) + R1/R2] = 1 



(3) 



Two additional conditions for calculating R REF , R1 and R2 
values are the minimum gain value G min , and the require- 
ments for the minimum and maximum l REF values, 0.1mA and 
1 mA, respectively: 



Gmin.dB = 20 log [V OU t/V| N ] = -20 log (R2/R1), (4) 
and 0.1mA =s (V REF - V, N )/R REF s 1mA (5) 

The op-amp output in Figure 21 has a DC component that will 
be attenuated as well as the AC input signal. The output 
coupling capacitor is used to remove the DC level. However, 
during switching, the change in DC level will cause a step 
transient or "click" at the output. 



3-113 



Companding DAC 



R2 



F -15V + 15V I ~| 

I13 |ia |io 



v B6F »|v, N | 



V- V+ V LC 



COMPANDING DAC 



R(-l 
E/6 SS EM 



1 2 3 4 5 6 7 8 9 



F 



DIGITAL INPUTS 



lODI-l ' 




-\\— "OUT 



Fig. 21. AC Coupled Digital Attenuator, Adjustable Range. 



Operating Modes 

The Companding DAC has two basic operating modes, de- 
code and ^ncode, which are controlled by the Encode/ 
Decode, E/D, input signal. A logic applied to the E/D input 
places the Companding DAC in the decode mode, and current 
will flow into the Iod(+) or 'od(-) output, depending on the 
state of the sign bit, SB, input. A logic 1 at the E/D input 
places the Companding DAC in the encode mode, which dif- 
fers from the decode mode by a half step offset current in 
each chord, and current flows into one of the I e outputs. 

The basic decoder connection for the Companding DAC is 
shown in Figure 22. The E/D input is grounded, which keeps 
the Companding DAC in the decode mode. The eight digital 
data inputs generate an output decode current which is con- 
verted by an operational amplifier to a bipolar voltage, E - 
Several discrete E values are tabulated in Figure 22 for both 
/x-law and A-law versions of Companding DACs. The values 
indicated in parenthesis correspond to the A-law Companding 
DAC. 

The Companding DAC can be used together with a Succes- 
sive Approximation Register, SAR, a comparator, and addi- 
tional SSI logic elements to perform the encoding or com- 
pression of an analog signal. The circuit, Figure 23, repre- 
sents an Analog-to-Digital data conversion system. The first 



task of this system is to determine the polarity of the incoming 
analog signal a nd to ge nerate a corresponding SB input . 
When the proper START, S, and CONVERSION COMPLETE, 
CC, signal levels are set, the first clock pulse sets the MSB 
output of the SAR, Am2502, to a logic and sets all other 
parallel digital outputs to logic 1 levels. At the same time, the 
flip-flop is triggered, and its output provides the E/D input with 
a logic level. No current flows into the I e outputs. This dis- 
connects the converter from the comparator inputs, and the 
incoming analog signal can be compared with ground which is 
applied to the opposite comparator input. The resulting com- 
parator output is fed to the Am2502 serial data input, D, 
through an exclusive-or gate. At the same time, the other 
input to the exclusive-or gate is held at a logic level by the 
logic shown in Figure 23. This exclusive-or gate inverts the 
comparator's outputs whenever a negative signal polarity is 
detected. This maintains the proper output current coding, i.e., 
all ones for full scale and all zeros for zero scale. 



The second clock pulse changes the E/D input back to a logic 
1 level because the CC signal changes. It also clocks the D 
input signal of the Am2502 to its MSB output, and transfers it 
to the SB input of the Companding DAC. Depending upon the 
SB input level, the Companding DACs output current will flow 
into the Ioe(+) or 'oei-i output. 



DIGITAL INPUTS 



B 7 B 6 B 5 B 4 B 3 B 2 B, SB E/D 

«M*1 




2.5 k!i 

-vw- 



-15V *15V 

'ref " Vref'Rreft 

IDEAL VALUES: l ReF - S20 M A |5I2,.A} 

l FS = 2007.75^ (2016*,A| 






E/D 


SB 


B1 


e 2 


B 3 


B 4 


85 




B 7 




POSITIVE FULL SCALE 









i 


1 




1 


1 




5.040V 


(*) ZERO SCALE -1 STEP 





■ 





D 








Q 





1 


0.004V 


(+1 ZERO SCALE 





















0.0012V 


(-1 ZERO SCALE 




















-0.0012V 


f-l ZERO SCALE +1 STEP 


















a 






oo4v 


NEGATIVE F ULL SCALE 





: 


1 


1 


1 




1 




' 


-5.040V 



Fig. 22. Detailed Companding DAC Decoder Connection. 

3-114 



Companding DAC 



ANALOG INPUT 



[GROUNDED FOB 
SINGLE-ENDED | 
INPUTSI I 



— 2 5kil> >2 




START *S.0V 



1 



SERIAL 

DATA 

OUTPUT 



Am2502 
SUCCESSIVE APPROXIMATION 
REGISTER ISAR) 



1 



CONVE RSION 
COMPLETE 



PARALLEL 

DATA 

OUTPUT 



E/D SB B 2 B 3 B 4 B 5 B 6 B ? 

V REF(*| 




, R REFM 
> 19.53kH 



; r refi-i 

>20kSi 



Fig. 23. Detailed Companding DAC Encode Connection. 



Nine clock pulses are required to obtain a digital, non- 
complemented, binary representation of the incoming analog 
signal at the eight Am2502 digital outputs. The resulting 
analog output signal is compared with the analog input signal 
after each of the nine successive clock pulses. The analog 
input signal should not be allowed to change its value during 
the data conversion time. In high speed systems, fast 
changes of the input analog signals are usually prevented by 
using sample and hold circuitry. 

When the Companding DAC is used in a feedback loop with a 
SAR, the data input transitions in the successive approxi- 
mation search technique exhibit a maximum change of two 
adjacent bits, and the starting pattern is 01 1 1 1111. The next 
successive pattern after the first iteration, will be either 
00111111 or 10111111. The worst case settling times are ex- 
perienced during step bit changes in chord 0, where the out- 
put current must settle to ±0.25liA. The worst case settling 
time is about 600ns for code changes in the upper end of 
chord zero and 1 800ns for code changes near zero. The sys- 
tem clock must take into account the settling time of the DAC, 
the switching speed of the comparator and the time delays in 
the SAR. In general, the DAC is the slowest component, 
(comparator Am311s delay is about 200ns and SAR delays 
are about 46ns), and will determine the clock rate. For op- 
timum accuracy the clock rate should accommodate the 
1800ns settling time near zero scale current. However, faster 
clock rates (1100ns-1 800ns) can be used with some degrada- 
tion in accuracy for signals near zero. 

Microprocessor Based Data Acquisition 
Systems Applications 

High output resolution with guaranteed monotonicity over its 
entire dynamic range and digitally controllable inputs makes 
the Companding DAC very attractive for application in data 
acquisition and control systems. The encoding capability, in 



particular, provides an acquisition system with considerable 
flexibility, limited only by the rate of change of the acquired 
analog input signals. 

A typical data acquisition system using the Companding DAC 
is shown in Figure 24. The A to D data conversion procedure 
is controlled by the 9080A Microprocessor set, (Am9080A 
8-bit Microprocessor, Am8224 Clock Generator and Driver, 
and Am8238 System Controller and Bus Driver). The START 
one-shot circuit, Am26S 02 w ill be activated by the START 
A/D command, (CS = 0, IOW =_0), which will initiate the A to 
D procedure by setting the S input of the SAR circuit, 
Am2502, to a logic 0. The width of the one-shot pulse must 
be greater than the period of the DATA CLOCK signal to ini- 
tialize the SAR logic. The duration of DATA CLOCK period 
must accommodate the worst settling time of the DAC and 
comparator Am311, to ensure valid data at the SAR input. 
The one-shot circuit may be eliminated, provided that the ex- 
pected worst case settling time does not exceed 1lis and the 
SYSTEM CLOCK, 01, does not_exceed 2MHz. The first data 
clock after S goes low sets the CC output high, which in turn 
switches the input sample and hold circuit, (LF198), into the 
hold mode and puts the microprocessor into a wait state. After 
eight subsequent DATA CLOCK periods, (8 x 2fis), the con- 
version complete signal, CC, changes from logic 1 to logic 0, 
which puts the S & H circuit into the sample mode and allows 
the microprocessor to resume its functions by removing the 
logic from the_RDYIN input of the Am8224 chip. With a logic 
1 at the SAR's S input, the DATA CLOCK cannot change the 
SAR's digital data outputs after completion of conversion. 
Thus, these outputs will be stable and available for sub- 
sequent interrogation. Th e mi crocomputer will issue a READ 
A/D command, (CS = 0, IOR = 0), which enables the three- 
state data buffer, Am25LS241 , and transfers the data outputs 
of the SAR to the system data bus and into the micro- 



3-115 



Comi 



-15V +15V 



i | 13 | 18 



HDYIN 

Q 



41 HLDA 
■2 WR 
RDY DBIN 
RST 
SYNC 



ADDRESS BUS 



ADDRESS 
DECODING 

LOGIC 
(25LS13B) 



READ A O 



B7 86 B5 B4 B3 82 B1 SB E D 



2G 1G 



DATA 
BUFFER 
Am25LS241A 



SAR 
2SD2 

CC 



MASTER RESET 



\7 



DATA CLOCK (SOOKHi MAX) 




Fig. 24. Microprocessor Controlled Data Acquisition System. 



processor's accumulator. A subsequent memory write com- 
mand, then stores this data in the desired memory location. 
For the next A to D data conversion, the microprocessor must 
generate another START A/D signal. An A to D data acqui- 
sition can be achieved using only three 9080A instructions. 

OUT (to ADC device) -generation of START A/D command 
IN (from ADC device) -generation of READ A/D command 
STA (to MEMORY) -store digital representation of the 

acquired analog signal into memory 

If the required nine DATA CLOCK periods present a prohib- 
itively long wait state for the processor, the A to D procedure 
can be more efficiently handled using a suitable interrupt 
scheme. The logic shown in Figure 25 illustrates the A to D 
and D to A co nversion using three inte rrupts. The external in- 
terrupt signal, VALID RECEIVE DATA, which initializes the A 
to D conversion, is received and processed by the Am9519 
Universal Interrupt Controller. It's output, GINT, is recog nized 
by the 9080A Microprocessor logic and ge nerates the INTA 
signal at the output of the Am8238. The VALID RECEIVE 
DATA signal will cause the receive S & H circuit to switch into 
the hold mode after 5/xs, via Am26S02 and associated flip- 
flop circuitry. This delay is needed to satisfy the sample time 
requirements for the (Am)LF398 S & H circuit, with C^ = 
1000pF. This one-shot circuit may be eliminated if the analog 
input data is maintained unchanged fo r about 25/xs after rec- 
ogn ition o f the VALID RECEIVE DATA signal. Upon receipt of 
an INTA signal, the Am9519 provides the address of an 
appropriate subroutine to the CPU. This subroutine will initiate 
the A to D conversion by generating the ST ART A/D com- 
mand. After A to D con vers ion is complete, the DATA READY 
signal, identical to the CC signal, generates an interrupt for 
the 9080A microprocessor to read and store the results of the 
A to D data conversion via an octal, non-inverting, three-state 
driver, the Am25LS241A. The CC signal at the same time will 



switch the receiving S & H circuitry into the sample mode. 
Two sequences of 9080A instructions which perform the ac- 
quisition operations described are detailed in Table 1 0. The cor- 
responding functional flow charts are shown in general form in 
Figure 26. 

The addition of SS I logic shown in Figure 25 generates sig- 
nals CS2 and CS3 which transmit an analog signal generated 
by the DAC from digital information stored in the system 
memory. An e xternal interrupt request for tr ansmission of the 
analog signal, TRANSMISSION REQUEST, will initiate the D 
to A conversion subroutine. A corresponding word in memory 
will be fetched into the 9080A accumulator and then lat ched 
into the A m25LS374, Octal D type register, via signals CS2 
and IOW. At the same time, the non-inverting three-state data 
bus transceivers, Am8T28, will be turned to the direction 
which corresponds to the D to A conversion procedure. The 
latch captures valid 9080A accumulator data, which will be 
used as the digital inputs throughout the D to A conversion 
procedure. The next instruction in sequence will be a com- 
mand to s tart s amplin g the Companding DAC's decode out- 
puts, (CS3 = 0, IOW = 0), which will be already settled. As- 
suming that one 9080A I/O instruction takes about 5fis at a 
system clock frequency of 2MHz, the next co mmand in the in- 
struction seque nce may generate a signal VALID TRANS- 
MISSION DATA, (CS3 = 0, IOR = 0), which will put the trans- 
mission S & H circuitry into the hold mode and return the data 
transceivers, Am8T28, to the direction which corresponds to 
the A to D conversion procedure. Input data for the Com- 
panding DAC is supplied by the SAR circuitry. A sequence of 
9080A instructions which could handle the D to A conversion 
procedure and analog signal transmission through the pro- 
gramming I/O interrupt scheme shown, is presented in Table 
10. The corresponding functional flow chart is shown in Figure 
26. 



3-116 



Companding DAC 




LIC-045 

Fig. 25. Microprocessor Controlled Single Channel Transceiver Converter System. 



GENERATE START 



MAIN PROGRAM 



DATA 

READY 

INTERRUPT 



STORE ACCUMULATOR 



ENABLE OTHER 
CPU INTERRUPTS 



MAIN PROGRAM 



LOAD ACC. WITH DATA 
FOR D/A CONVERSION 



GENERATE TRANSMISSION 

HOLD COMMAND AND 
VALID TRANSMISSION DATA 



ENABLE INTERRUPTS AND 



TO MAIN PROGRAM 
t 



Fig. 26. Functional Interrupt Subroutine Flow Charts for Data Transceiving Converter. 

3-117 



Companding DAC 



TABLE 10 

INTERRUPT SUBROUTINES FOR SINGLE CHANNEL DATA TRANSCEIVING 
CONVERTER SYSTEM IMPLEMENTED WITH 9080A INSTRUCTIONS 



VALID RECEIVE DATA Interrupt Subroutine: 

OUT (to ADC) -Generate START A/D command. 

El - Enable other CPU interrupts. 

RET - Return to main program. 

DATA READY Interrupt Subroutine: 

STA (to TEMP) - Save accumulator content. 

IN (from ADC) - Read digital results from SAR outputs Into accumulator. 

STA (to Memory) - Store accumulator's content into memory. 

LDA (from TEMP) - Restore accumulator's content before subroutine. 

El - Enable other CPU interrupts. 

RET - Return to main program. 

TRANSMISSION REQUEST Interrupt Subroutine: 



STA (to TEMP) 
LDA (from DATA) 
OUT (to LATCH) 
OUT (to DAC) 
IN (from DAC) 
LDA (from TEMP) 
El 

RET 



Save Accumulator content. 

Load accumulator with digital data which will be converted to an analog signal. 
Output data for D to A conversion to the latch circuit and STAR T D/A con versio n. 
Generate Transmission SAMPLE command for S & H circuitry. CS3 = 0, IOW = 0. 



Generate Transmission HOLD command for S & H circuitry, and VALID TRANSMISSION DATA signal. 
Restore accumulator's content before interrupt subroutine. 
Enable other CPU interrupts. 
Return to main program. 



Motion Control Systems Applications 

The high resolution and accuracy of the Companding DAC 
transfer function for small output signal levels provide a very 
smooth and precise analog control signal to devices whose 
outputs are voltage or current dependent. However, when 
major disturbances are detected in the system, the Com- 
panding DAC will produce correspondingly larger control 
analog signals which cause very fast output response of the 
controlled analog device. Figure 27 shows the Companding 
DAC used in a feedback loop to provide a small analog error 
signal to control the speed and direction of a voltage con- 
trolled motor in order to properly position the shaft. The shaft 
encoder generates an 8-bit digital word which represents the 
current shaft position of the motor. 

There are 256 discrete positions of the shaft which can be 
identified at the shaft encoder's output. This output will be 



sampled and latched using an 8-bit register, Am25LS273. The 
sampling rate is determined by dividing the time for one shaft 
revolution at the motor's highest speed by 256. The maximum 
rate will be limited by propagation delays through the 
comparator and ALU chips and by the settling time of the 
Companding DAC. The output of the shaft position sampling 
register, data "B", is digitally compared with the desired shaft 
position, data "A". The magnitude of the difference between 
digital words "A" and "B" is directly porportional to the error 
of the motor shaft position. The sign of this digital subtraction 
provides information about the polarity of the analog error sig- 
nal which drives the motor in the direction necessary to de- 
crease the error. The speed of the motor is proportional to the 
magnitude of the error I A— B| . The sign and magnitude of the 
error are determined by two comparator chips, (Am9324 
Four-Bit Comparator), and two ALU chips, (Am25LS381 



POSITION AND 
CLEAR COMMANDS 
(FROM COMPUTER) 



"DONE- 
(TO COMPUTER) 



SHAFT POSITION 
(FROM COMPUTER) 



ANALOG 
OUTPUT ( + ) 
(SHAFT ERROR) 



Am25LS273 



8 




V 



SAMPLE COMMAND 



(GENERATED BY THE COMPUTER 
OR BY AN INDEPENDENT CLOCK) 




ANALOG 
—I— OUTPUT (-) 



ANALOG 
ERROR SIGNAL 

/ 




SHAFT ENCODER 
(CODE WHEEL) 



Figure 27. Nonlinear, Computer Controlled, Digital-to-Shaft-Posttion Conversion System. 

3-118 



Companding DAC 



Four-Bit Arithmetic Logic Unit). The end of the motor shaft 
correction procedure is indicated to the computer via the 
comparator's output "A=B". 

The eight digital bits of the error magnitude |A-B| are 
applied to the seven data inputs of the Am6070 and to the 
E/D input. The Am6070 outputs are connected to provide 32 
steps per chord, which totals 256 steps or a 78dB output 
dynamic range. The smallest and largest step sizes are 
0.25|U.A and 32/iA, respectively. The sign bit value is taken 
from the "A>B" output of the comparator circuit, and deter- 
mines the polarity of the op-amp, (Am)LF356, output voltage. 

The computer function in Figure 27 is mainly confined to ini- 
tializing the shaft correction procedure by latching the desired 
shaft position, data "A". Clear commands may be issued dur- 
ing the power-up procedure in order to bring the motor shaft 
to some initial position. The application of the Companding 
DAC with its nonlinear transfer characteristic and its non- 
uniform step sizes which are proportional to the magnitude of 
the error, | A— B| , significantly reduces system transient re- 
sponse effects such as over-shoots and ringing while mini- 
mizing the time required to reach the new shaft position. The 
system can be programmed to be either critically damped 
(minimum response time) or under damped (no overshoot). 

Figure 28 shows a Companding DAC in a feedback loop 
which provides small analog error signals for control of the 
velocity of a voltage controlled motor. This is a paper cutting 
control system where paper is unwound from a feed roll and 
cut to size by a mechanical knife. In this application the Com- 
panding DAC is in the velocity feedback path and its output is 
used to generate a velocity profile command signal. The 
motor rotation is initiated from a front panel by depressing the 
START button. A COUNT-UP command from a micropro- 
cessor sets the binary counter to its count up mode, which 
drives the Companding DAC inputs. When some predeter- 
mined number of counts has been reached, the counter stops 
and the Companding DAC is held at a constant output value. 
The incremental encoder produces pulse counts proportional 



V UT VELOCITY PROFILE 

V1 CUT 



START COMMAND 



MICROPROCESSOR 
CONTROL 



COUNTER AND 
COMPANDING 
DAC 



VOUT 


MOTOR 




CONTROL 




Fig. 28. Paper Cutting Control System. 



to the distance of paper travel. The desired paper size ex- 
pressed as a number of incremental encoder pulse counts is 
stored in a CPU storage register. The outputs of the incre- 
mental encoder are constantly accumulated in an internal 
CPU counter and are compared with the content of the CPU 
storage register throughout the entire velocity control proce- 
dure. When a match is found, the corresponding COUNT 
DOWN command is issued to the counter, the internal counter 
is cleared, and a new value is loaded into the internal storage 
register. 

The values which control the velocity of the motor are stored 
in a register, external to the CPU, and its content is compared 
with the outputs of a binary up/down counter during the 
motor's acceleration and deceleration phases. Whenever a 
match is achieved, an interrupt signal will be generated and 
the working mode of the external counter changes. The final 
stop position is approached in a well controlled manner which 
stops the paper and cuts it with a minimum of overshoot and 
error. 

Figure 29 shows the necessary logic for generation of the 
velocity profile control signal. The CPU will first load the ex- 
ternal storage register, Am25LS273, via the LOAD signal, to 
the desired count-up value for the external up/down counter, 
Am25LS193. Upon recognition of the START request, the 
CPU issues the COUNT-UP command which enables the 
8-bit comparator chip, Am25LS2521. The zero initial digital 
code at the Companding DAC inputs produces zero voltage at 
the output, V 0UT . Every enabled conversion clock pulse will 
increase the Companding DAC output current by a corre- 
sponding amount, and the V ut increases in accordance with 
the Companding DAC transfer characteristic. This portion of 
the velocity profile control signal corresponds to the motor ac- 
celeration phase. When the counter outputs match the content 
of the external storage register, the interrupt signal INT1 is 
generated, and the UP flip-flop is reset. 

This stops the up/down counter and the motor continues to ro- 
tate with a constant velocity, V1 . Duration of the acceleration 
phase depends on the value initially stored in the external 
storage register and th e freq uency of the conversion clock. 
Upon recognition of the INT1 signal, the CPU will load a new 
value into the external storage register, which is used to de- 
celerate the motor from velocity V1 to a lower velocity, V2. 
During the constant velocity phase, V1, the encoder pulses 
accumulate in the CPU counter until the value "m ", stored in 
the CPU internal storage register, is reached. At this time the 
CPU will issue a COUNT DOWN command and reload the in- 
ternal storage register with the value "n". The sum of these 
two values, m + n, should represent the length of the paper 
expressed in encoder pulses. This value is "p" pulses shorter 
than the desired ideal paper length. 

The COUNT DOWN command initiates the count-down mode 
of the external up/down counter, PHASE I, and enables the 
comparator. When the counter outputs match the valu e stor ed 
in the external storage register, the interrupt signal INT2 is 
generated and counting stops. The motor continues to rotate 
with some constant velocity, V2, which is significantly smaller 
than velocity V1 . This velocity, V2, is a function of the conver- 
sion clock frequency and the motor's mechanical parameters 
such as inertia, weight, etc. The mechanical parameters may 
cause synchronization difficulties between the second decel- 
eration phase of the voltage waveform at V 0UT and the actual 
velocity of the motor. The velocity V2 is much smaller than V1 
and allows a smooth, well controlled stop of the motor at the 
end of the PHASE II of count-down mode, and thus ensures 
the smallest possible overshoot and error. 



Companding DAC 



CPU 
!Am90B0A 
Am8224 
Amd238 
Am9S19 
INTERNAL REGISTER 
INTERNAL COUNTER 
SYSTEM MEMORY) 



IOW r 



ADDRESS 
DECODING 
LOGIC 

(7404 

7430) 



D up Q 
CK Q" 



COUNTDOWN 



1 7474 



J. 7474 



8-BIT 
COMPARATOR 
(Am25LS2521) 



SYSTEM DATA BUS 




8-BIT 
REGISTER 
(Am25LS273) 



D Q 
CK O 



CONVERSION CLOCK |500KHz MAX) 



m ENCODER PULSES^ PLS 
COUNT UP 



COMPANDING DAC\ 
(Am6070) 





UP DOWN 
COUNTER 
cp (2X Am25LS193) 



Fig. 29. Microprocessor Controlled Generation of Motor Velocity Control Signal. 



The INT2 signal automatically clears the external storage reg- 
ister to all zeros and informs the CPU that the deceleration 
PHASE I is complete. The CPU continues, internally, to ac- 
cumulate the encoder pulses until their number becomes "n". 
At this time the CPU issues a new COUNT DOWN command 
to initiate PHASE II of the count-down mode, and reloads the 
internal storage register with a final number "p". This number, 
when summed with the previous two numbers "m" and "n", 
determines the final length of paper, m + n+p, and is accumu- 
lated in the internal CPU counter during PHASE II of c ounter's 
count-down mode. At the end of this phase, the INT3 signal is 
generated and counting stops. The number of encoder pulses 
in the internal counter will be compared with the number "p" 
stored in the internal storage register. If a satisfactory match 
is found, the CPU issues a CUT command to the paper cut- 
ting station and the paper is cut to the desired size. Finally, 
the CPU issues the CLEAR command to initialize the INT 
flip-flops and clear the internal counter. It also reloads both in- 
ternal and external storage registers with appropriate values, 
so that a new velocity profile control signal can be generated. 
Much of the logic shown could be implemented in software, 
but this would require that much of the microprocessor re- 
sources be dedicated to this speed control function. 
Audio System Applications 

Audio system equipment applications require signal con- 
verters which can process bipolar analog audio signals within 
a ±10V range. A DAC, in an audio system, provides digital 
gain and/or attenuation of input audio signals. This requires a 
multiplying DAC, i.e., it must accept an audio signal either in 
single ended or differential form, and process it as a function 
of the digital control inputs. Ideally, an audio level control de- 
vice provides an equal change, in dB, of relative signal level 



between any two adjacent digital codes or steps throughout 
its entire output dynamic range. However, differences be- 
tween steps which exceed 1dB can be annoying to the human 
ear. For high quality audio systems, the DAC must have low 
signal distortion, (on the order 0.05?? or less over most of the 
dynamic range), large working dynamic range, (80dB or 
more), wide bandwidth, large signal to noise ratio, S/N, (80dB 
or more), and transient-free output gain-change operation 
which is independent of digital input states. 

The Companding DAC with its multiplying feature and its abil- 
ity to extend its dynamic range up to 78dB, satisfies or ex- 
ceeds most of these requirements. It handles audio input sig- 
nals up to ±10V, and its output signal distortion is 0.02% or 
less over most of the audio signal range. Its nominal level/ 
step resolution is 0.1 5dB, and its S/N ratio is 80dB or better 
when referred to a 1V output. However, its total useful audio 
dynamic range, with a maximum 1dB difference between two 
adjacent steps, is only 59dB, and its output exhibits DC gain 
step transient effects, due to the required DC bias current. 

The Companding DAC's DC output current potential "click" ef- 
fects must be suppressed for applications in audio systems 
where there are large changes in the digital input code. Figure 
30 shows the connection for the necessary DC output current 
compensation. The output dynamic range can be adjusted by 
varying the value of resistor R2. To suppress the DC step 
transients, the current l 2 compensates for all DC changes in 
current I,. The l 3 current reflects only the AC changes in cur- 
rent l 1 and the current through resistor R2 due to changes in 
the V m signal. This allows the attenuated V, N signal to be DC 
coupled through op-amp A2. The maximum gain for the circuit 
is assumed to be unity, (OdB), when all digital inputs are set 



3-120 



Companding DAC 



R IN 



DIGITAL 
INPUT 



'ODI-I 



"Bl + I 
SB E.T3 B7 



R HEF+ ^ 



"BEF 




'l =l 10C + l lAC 




Vr,-> 



Iqdi i> 



'OE(-) , 




Fig. 30. DC Coupled Digital Attenuator, Adjustable Range. 



at logic 1. A determination of the resistor values Rref+. R1 
and R2, was discussed in the section on the AC coupled digi- 
tal attenuator. The R RE f- value should be identical to R REF+ 
value and the R3 and R4 values must be equal, so that the 
current, l 2 will compensate tor the DC component of l-j. 

The 1dB audio resolution requirement truncates approximately 
19dB from the Companding DAC's total dynamic range of 
78dB. The level ratio becomes greater than 1dB between the 
9th and 8th step of chord 0, (0.25/j.A/step). If the 1dB reso- 
lution criterion is applied to a comparable sign-plus-13 bit 
linear DAC, the corresponding 1dB requirement also takes off 
19dB, and the breakpoint occurs between the 9th and 8th 
step of the linear 13-bit DAC transfer characteristic. The 
subtle difference between the 13-bit linear DAC and the 
sign-plus-8 bit Companding DAC lies in the distribution of the 
dB ratio values within the steps of the 59dB workable audio 
dynamic range. For a linearly scaled 13-bit linear DAC, the 
level ratios in dB among the steps close to the full scale 
current are very small. The ratios increase as the step 
numbers decrease toward zero. On the other hand, the 
sign-plus-8 bit Companding DAC maintains a near constant 
0.15dB between steps over the entire dynamic range, with the 
exception of steps in chord 0. 

The 59dB working dynamic range is not wide enough for high 
quality audio systems which require an 80dB audio control 
range. To satisfy this requirement, two DACs can be 
cascaded with their digital inputs driven in parallel. The total 
dynamic range is now increased to 156dB and the working 
range, (1dB/step or less), is now approximately 106dB. A 
cascading scheme for Companding DACs, which also 
provides for DC transient-free operation, is shown in Figure 
31. The advantage of the cascaded Companding DAC's 
scheme over a similar cascaded linear DAC's scheme is in 
the number of control bits required to achieve the 106dB 
range and in the 0.3dB/step uniform attenuation distribution 



over most of the 106dB range. The audio signal, V| N , is 
shown in Figure 31 as a single input. 

All three Companding DACs in Figure 31 have their SB inputs 
tied to logic 1. The reference currents for all three DACs 
should be maintained at positive values throughout the 
attenuation procedure by proper selection of the input resistor, 
r in = V| N /I| N , where l IN < l REF . ln Figure 31, the maximum 
li N value is equal to one half of the DC reference current, and 
the maximum value of V| N is only limited by the output 
voltage swings of operational amplifiers A2 and A3. The DC 
transient effects in the cascaded DACs are compensated for 
by using a Companding DAC followed by the A1 op-amp. The 
DC compensation circuitry is completely isolated and 
independent of the AC effects of the applied audio signal V, N , 
and the only critical requirement is matching R-, and R REF(+) . 
The step sizes in all chords should be matched for all three 
Companding DACs. For audio signals with amplitudes not 
more negative than -5V, (Companding DAC's maximum 
negative output voltage is -5V), the A1 op-amp can be 
eliminated, and the positive inputs of the A2 and A3 op-amps 
can be driven by the DC compensating DAC directly. 

Companding DACs, with their logarithmic transfer function, 
are natural generators for the attack and decay analog signal 
waveforms used in electronic organs and musical 
synthesizers. A waveform's attack, sustain, and decay times, 
together with additional harmonic content information, 
determine the sounds of a particular musical instrument. For 
example, woodwinds have very short attack and decay times. 
The circuit shown in Figure 32 generates trapezoidal-like 
waveforms with exponential rise and fall times under the 
control of an 8-bit microprocessor, Am9080A. Digital inputs 
are supplied by two pairs of 4-bit binary counters, 
Am25LS191, which are set to the Count Down mode. All of 
the counters are simultaneously loaded by the LOAD 
command which is decoded from the microprocessor's 



3-121 



Companding DAC 




t~ -15V + 15V 



LIC-051 

Fig. 31. DC Coupled Cascaded Digital Attenuator. 






LIC-052 



Fig. 32. Microprocessor Controlled Waveform Generator, Attack, Sustain and Decay Signal Waveforms. 

3-122 



Companding DAC 



address signal combination. Companding DACs 1 and 2 are 
in the decode mode. The SB inputs are determined by the 
most significant data bit, DB7, which is stored in the flip-flop 
during counter loading. The Companding DACs' decode 
outputs which have the same polarity are tied together and 
fed into an LF356 operational amplifier. After the settling time 
required for the Companding DACs outputs, the currents at 
the op-amp's inputs should be equal, and its output, V 0UT , 
should be OV. A command COUNT #1 closes the analog 
switch, AH0014, and enables counters 1A and 1B via their 
ENABLE inputs. The 500kHz clock frequency allows sufficient 
settling time for the Companding DACs outputs. The initial 
rise of the op-amp output voltage, V ut, depends on the 
number initially stored in the counters, i.e., it depends on the 
starting point of the Companding DAC trans fer characteristic. 
When Counter #1 reaches zero, the INT1 signal indicates 
underflow, further counting stops, and the microprocessor is 
informed about the end of Counter #1 operation. After a 
certain sustain time, which can be preprogrammed, the 
microprocessor issues the COUNT #2 command and the 
V ut waveform starts its decay portion. The time duration of 
the Attack and Decay slopes generated by the logic in Figure 
32 are equal and is specified by the starting count in Counters 
#1 and #2. 

Note that the microprocessor can control the counting 
functions and the external counter could be replaced with 
simple, octal data latches. With the increased use of digital 
techniques and microprocessors for control functions in 
complex audio systems, microprocessor controlled analog 
waveforms, similar to those generated by the logic in Figure 
32, may become very desirable and attractive tools for the 
generation of various audio effects. However, it is important to 
remember that the output from the Companding DAC consists 
of discrete, non-uniform steps and is not continuous. To 
obtain a real, continuous signal from the output, some filtering 
or integration may be required. 

Telecommunication System Applications 

Digital PCM transmission systems compress analog speech 
signals into a train of 8 digital bits for each sample. They 
transmit this information and then decode and expand it back 
into analog signals. The Companding DAC represents a 
monolithic solution for most requirements of the PCM 
encoding and decoding procedures. This device replaces a 
considerable number of discrete and hybrid components in 
existing PCM transmission schemes. At the same time, the 
Companding DAC provides increased signal-to-noise ratio in 
the system, reduces system signal distortions and stimulates 
further development and wider usage of digital channel 
switching techniques. 

Currently, most transmission systems in the United States 
follow the Bell D3 communication channel bank specifications, 
where each channel bank consists of 24 voice channels and 
the necessary transmission equipment. The entire signal 
sampling, encoding and multiplexing procedure in the 24 
channel bank system must be performed within 125ju.s. The 
PCM channel time slot distribution, within a one 125jis time 
frame, is shown in Figure 33. Each slot contains an 8-bit 
digital representation of a particular signal sampled from a 
corresponding voice channel. The total number of bits in the 
D3 channel bank time frame is calculated as follows: (24 
channels x 8 bit/channel) + 1 signalling bit = 193 bits. The 
additional single bit is used to identify the beginning of a 
frame, and data is transmitted at 1.544MHz (193 bits/samples 
x 8000 samples/sec). In addition, in every sixth frame the 




ALL 8 BITS FOR I IN 5 FRAMES 

VOICE ENCODING I OUT OF 6 

LIC-063 

Fig. 33. PCM Channel Timing Frame Format. 

least significant bit in each channel slot is used for 
communication signalling purposes. Consequently, the signal 
samples in every sixth frame are represented with only 7 
digital bits. The increase in signal distortions in this time frame 
is slight and is not considered significant for PCM voice 
transmission performance. When the Companding DAC is 
used as a simple decoder at the receiving side of a system, 
the connection shown in Figure 19 can be used to minimize 
distortion caused by the absence of the least significant bit, 
B7, during these signalling frames. When the signalling frame 
is recognized, the Companding DAC output is increased by a 
half step from its corresponding decode output value by 
switching the E/D input from a logic level to a logic 1 . 
However, the European systems, using A-law devices, have 
32 channels per bank where the 2 channels are used for 
signalling information. Each frame requires 256 (32 x 8) bits. 
The corresponding data transmission rate is 2.048MHz (256 
bits/sample x 8000 sample/sec). 

In a two-way PCM communication system, a single 
Companding DAC can perform the time shared encoder and 
decoder functions known as the CODEC function. The logic 
state of the E/D input determines the operating mode of the 
Companding DAC and switches the output current to the 
appropriate outputs. The Companding DAC digital inputs 
during the encode operation are generated by the successive 
approximation procedure. In the decode mode, the eight 
digital inputs are supplied from an external source, either in 
serial or parallel. The basic diagram for a typical CODEC is 
shown in Figure 34. 

The logic in Figure 34 provides automatic handling of the E/D 
signal levels during the CODEC'S XMT mode of operation. 
The first task of the system is to initialize the SAR circuit by 
proper manipulation of the START input for the successive 
approximation procedure. The XMT COMMAND should be 
synchronized with the low-to-high transition of the START 
pulse, and its level must be held at logic 1 for the next 8 
CLOCK pulses to keep the three-state XMT buffer, 74126, in 
the low impedance state. During the A to D conversion period, 
a serial train of 8 digital bits, which represent the sample at 
the TRANSMIT ANALOG I NPUT in F igure 34, appears on the 
XMT DATA line. XMT and RECEIVE commands are mutually 
exclusive. 

The CODEC in Figure 34 is se t to the receive mode of 
operation by setting the RECEIVE command signal to a logic 



Companding DAC 




Fig. 34. PCM Encoder/Decoder or Transceiving Converter. 



level after the START pulse returns to its positive level. A 
serial data source, DATA STORAGE, supplies a digital train 
of 8 bits to the serial input D of the SAR circuit via the 
three-sta te buffer, RCV, 74126. At the same time, the 
RECEIVE command signal level keeps the exclusive-or gate 
output separated from the same SAR's serial D input via 
another three^state buffer, SEP. The same command also 
keeps the E/D input of the Companding DAC at logic 
throughout the entire D to A procedure via the MODE flip-flop 
in the successive approximation logic. In this CODEC'S 
receive mode, the SAR circuit acts as a serial-to-parallel shift 
register for the incoming data on the RECEIVE DATA line. 
After the 8 clock pulses, the outputs of the SAR are ready for 
the D to A conversion. An analog current representation of the 
RECEIVE DATA train appears at the RECEIVE ANALOG 
OUTPUT, after an appropriate settling time. During this time 
the SAR outputs must remain u nchanged and the START 
signal must remain at logic 1 . The RECEIVE command signal 
must be held at logic for the entire D to A conversion time 
which includes the Companding DAC's settling time. The 
CODEC must sample the analog input prior to each A/D 
conversion. During this sampling period the analog input 
signal will be changing and the Companding DAC cannot be 
used to encode this signal. The total encoding time must 
include the sampling time and the A/D conversion time. If the 
sampling time period is greater than the time required for the 



decoding procedure, the Companding DAC can be used as a 
decoder during this time period and thus, the decoding 
operation will not require any additional system time. 
The CODEC operations in PCM communication systems can 
be performed on a single channel or on multiple channels in a 
multiplexed channel switching scheme. The final number of 
multiplexed channels which can be served by a single 
Companding DAC with a data sampling rate of 8kHz is limited 
by the CODEC'S sampling and settling times. 

Two examples of a single channel PCM CODEC are shown in 
Figure 35 and 36. The major difference is in the structure of 
the XMT and RECEIVE data bus. The parallel data I/O 
CODEC in Figure 35 transmits and receives digital data in 
parallel form. The parallel data CODEC contains data bus 
transceivers, (Am)8T26, for handling data in communications 
systems which might be controlled by one of the popular 8-bit 
microprocessors. A parallel data I/O CODEC has a 
considerably shorter D to A conversion time than a serial I/O 
CODEC. 

The circuits shown in Figures 35 and 36 are controlled asyn- 
chronously with START, XMT, RECEIVE and their corre- 
sponding SAMPLE COMMANDS, which are generated and 
supplied externally by a communication system. The CLOCK 
signal is also externally supplied, and in the case of a serial 
data I/O CODEC, it must be synchronized with the incoming 



3-124 



Companding DAC 





LIC-056 



Fig. 36. Single Channel PCM Codec Serial Data I/O. 

3-125 



Companding DAC 



and outgoi ng serial data train. The CODEC'S only output con- 
trol signal, CONVERSION COMPLETE, CC, provides the ex- 
ternal communication system with information necessary to 
generate a XMT signal during the encoding procedure. XMT 
and RECEIVE commands are mutually exclusive. The trans- 
mit and receive data transfers can be performed either alter- 
nately or simultaneously. In the latter case the external com- 
munication system must employ separate transmit and re- 
ceive data buses. In addition, storage devices external to the 
CODEC logic must be provided for the receive data. The code 
assignment for outgoing or incoming parallel data provides 
uncomplemented binary values for sign and magnitude. The 
DAC data bus, as a result, yields "high zeros" density for 
small output signal amplitudes. 

To perform a transmit operation cycle, the START pulse must 
be held low for one clock cycle. Data conversion for a trans- 
mit operation is completed in 9 clock cycles, where the ninth 
cycle initializes the SAR for the next successive approxi- 
mation procedure. 



The RECEIVE operation in parallel data I/O CODEC is per- 
formed without using SAR logic, and the corresponding D to A 
data conversion does not require a CLOCK signal. Duration of 
the RECEIVE command signal must accommodate the Com- 
panding DAC's settling time, plus the sampling time (=5jiS) 
required by the S & H circuit, used at the CODEC'S analog 
output. The typical settling time for the worst case input code 
transition from all ones to all zeros is about 4/j.s. The re- 
ceiving data must not change during this time. A XMT com- 
mand must be issued after a high-to-low transition of the CC 
signal, and its duration depends on the time required by the 
external system logic to sample the correct content from the 
8-bit parallel data bus. A sample command pulse for a trans- 
mit operation can coincide with the START pulse; its duration 
depends on the sample and hold circuit used at the CODEC'S 
analog input. A sample command pulse for a receive oper- 
ation must be delayed from a low-to-high transition of the 
RECEIVE command signal by an amount equal to the Com- 
panding DAC's settling time. Its termination can coincide with 
a high-to-low transition of the RECEIVE command signal. 

In the serial CODEC the duration of XMT and RECEIVE 
command signals must similarly accommodate all signal 
propagation delays, as well as the settling and sampling 
times, necessary for conversion of an outgoing or an incoming 
series of 8 digital bits. During the receive operation, the SAR 
is acting as a serial-in to parallel-out shift register for data 
supplied from an external serial source. Shifting data into the 
SAR requires 9 clock pulses. A sample command pulse for a 
transmit cycle must be issued before an XMT command sig- 
nal; its duration depends on the S & H sampling time used at 
the CODEC analog input. A sample command pulse for a re- 
ceive cycle must be delayed by a time equal to the Com- 
panding DAC's settling time after a high-to-low transition of 
the CC signal occurs. The data transmission rate at the re- 
ceive line is limited only by the shifting speed of the SAR 
which is rated at 15MHz. The data transmission rate at the 
serial CODEC'S data XMT line is limited by the settling time of 
the Companding DAC and propagation delays through the 
comparator, exclusive-or, buffer (74126), and SAR devices. 

In a one-way PCM communication system the Companding 
DAC can be used as the decoder at the receiver end of a sys- 
tem or as a part of the encoder at the transmission end of a 
system. The transmission data bit rate for 24 communication 
channels sampled at 8kHz is 1 .544 megabits/sec. This trans- 



mission rate allocates 0.64^s for each of 193 bits within a 
125|U,s long 24-channel time frame. A 24-channel PCM de- 
coder which is capable of handling this transmission bit rate is 
shown in Figure 37. This schematic does not show the logic 
necessary for recognition of frame and signalling bits. To 
handle a single bit in 0.64/xs the total signal propagation time 
through the 8-bit D-type register, Am25LS273, the Com- 
panding DAC, Am6072, and the op-amp must not exceed 8 x 
0.64/nS = 5.12/iiS. This corresponds to the total shifting time 
of 8 bits through the serial-in, parallel-out, shift register, 
Am25LS164. The most critical propagation delay is caused by 
Companding DAC's worst case settling time which corre- 
sponds to the worst possible input transition of 1111111 to 
0000000, which can occur during D to A conversion. If 4fis 
are taken for the worst case settling times of the DAC and 
op-amp, only 1.12aiS are left to be distributed to all other time 
delays in the system. The 4-bit counter, Am25LS161, and 
8-bit shift register, Am25LS164, are synchronized with the 
system supplied data clock at 1 .544MHz. The additional logic 
in Figure 37 consists of analog switches AH0014 and 
AM9712, and the corresponding SSI control logic. This switch- 
ing scheme provides a minimum of crosstalk between output 
analog channels which may occur due to a possible break- 
before-make switching problem. The output analog channel 
hold capacitor values depend a lot on the type of a load at 
these outputs. The Bell D3 specification specifies system per- 
formance down to signal levels of -50dB (00000111 code on 
the transfer curve). Worst case settling time from full scale to 
-50dB is about 2.5/u.s. Decoders in excess of 24 channels, 
can be built using this settling time but they will have some- 
what higher distortion for signal levels below -50dB. 

In the PCM encoder schematic shown in Figure 38, the 
maximum settling time for the Am6072 is assumed to be 
1 .2fis for the worst input bit change. The Bell D3 specification 
can be satisfied using a settling time of 1.2,iiS, which is the 
worst case settling time in the successive approximation pro- 
cedure for signals near -50dB (lowest level on D3 specifica- 
tion). There will be some additional error for very low level 
signals, but the overall system will meet the D3 specification. 
The additional logic delay in the feedback path is estimated to 
be 100ns maximum, and is distributed among the comparator, 
Am686, the digital 2:1 multiplexer, Am74S258, the exclusive- 
or circuit, 74LS86, and the SAR, Am2502. This yields 1.3/is 
for one successive approximation iteration. Further timing 
analysis shows that, with no additional delays, 12 channels 
can be encoded within the 125/xs: 



1.3/xs 
Clock 



'8*12 = 10.4^s • 12 = 124.8ms 
= 1/1.3/xS = 769.23kHz 



Two methods are used in the schematics in Figure 38, to pre- 
vent additional delays. First, a special switching scheme of 
analog input signals is employed to sample a channel from 
one group while a channel from the other group is encoded. 
This sampling scheme saves the time required for sampling of 
an analog input and provides a solution for encoding a 
maximum number of channels for the given "one-bit iteration" 
time. This design uses analog multiplexers, AM9712, and 
sample and hold circuits, (Am)LF398. The analog multiplexer 
at the Companding DAC output, AH0014, switches to another 
comparator during the time allocated for the first bit iteration, 
when the sign bit of a sample is established and no current 
flows through l 0E outputs. Secondly, a one shot circuit is used 
to modulate the positive period of the first data clock pulse, 
after the SAR's CC signal is generated. The one shot pulse 
should split the positive portion of this first clock pulse into 



3-126 



Companding DAC 




LIC-057 

Fig. 37. 24-Channel PCM Decoder. 



two positive pulses, and the positive edge of the second pulse 
will initialize the SAR and eliminate the need for a ninth pulse. 
The net effect of this pulse modulation is a reduction of the 
time available to the SAR for the determination of the sign bit 
value and reduction of the time available for recording the 
SAR outputs with the correct least significant bit value. How- 
ever, the time for sign bit evaluation is 'Ips, and the LSB 
value can be taken from the SAR's serial data input D at the 
time of conversion completion. The encoding logic in Figure 
38 is fully synchronized with the system supplied data clock 
which is input at a frequency of 769.23kHz. A similar en- 
coding scheme provides encoding of 8 channels within the 
125ns time without the circuits which are enclosed by dotted 
lines in Figure 38. Only one S & H circuit and one comparator 
can be used, and the AH0014 and 74S258 circuits can be 
eliminated. This D3 system's 8-channel PCM encoder has 
15.6(ixs for an A/D conversion, which allows 5.2^s for the 



analog multiplexer, (AM9712), and S & H, (LF398), to switch 
and settle prior to the actual A/D conversion which takes 
10.4/iS. 

One multiplexed CODEC using a single Companding DAC is 
shown in Figure 39. The CODEC'S entire activity is syn- 
chronized with a data clock which drives the RECEIVING 
REGISTER, Am25LS22 (8-bit Serial/Parallel Register), the 
SAR, Am2502, and the 4-bit binary counter, Am25LS161. 
Maximum clock frequency is limited by the delays involved in 
the encoding path and by the data transfer protocol chosen 
for the XMT and RECEIVE data lines. Using 1.8/j.s for the 
Companding DAC's longest settling time and 150ns for all 
other propagation delays in the encoding path, the minimum 
time for eight iterations amounts to 8 x 1.95/us = 15.6/iS. The 
corresponding Data Clock frequency is 512.82kHz. A time 
frame of 125^s contains eight time-slots of 15.6/xs each. 



3-127 



Companding DAC 




•Note: Circuits enclosed by a dotted line may be eliminated in an 8-channel encoder tor the D3 communication system which 
uses 5.2 /xs for the input switching and sampling times, (Am9712 and LF398), and 10.4/iS for one A/D conversion. 

uc-c 

Fig. 38. 12-Channel PCM Encoder. 



The CODEC in Figure 39 has four multiplexed channels, and 
uses the data conversion protocol illustrated in Figure 40. This 
protocol allocates equal time to the encoding and decoding 
procedures. Although this is not the most economical timing 
scheme, it significantly simplifies the CODEC'S logic. The 
value of the most significant bit, MSB, of the 4-bit counter 
controls the switching between the encode and decode func- 
tions, and the switching of the input and output analog chan- 
nels in the analog multiplexers, AM9712, via 1 of 4 decoder 



circuit, Am25LS2539, (Dual 1 of 4 decoder). During the nega- 
tive half of the MSB period, the S & H circuit is placed in the 
hold mode, the DATA CLOCK and the outputs of BUFFER 
REGISTER, Am25LS373, (Octal Transparent Latch), are ena- 
bled and the Companding DAC is placed in the encode mode. 
At the same time, the RECEIVING REGISTER, Am25LS22, is 
receiving data with its outputs in the high impedance state. All 
analog switches, XMT and RECEIVE, are open during this 
negative portion of the MSB signal. 



3-128 



Companding DAC 



During the positive half of the MSB signal period, data clock 
inputs to the SAR and RECEIVING REGISTER, and START 
input to the SAR, are kept at logic 0. The S & H circuit is put 
into the sample mode, the BUFFER REGISTER is put in the 
high Z state, the RECEIVING REGISTER outputs are en- 
abled, and the Companding DAC is put into the decode 
mode. During this positive period, the currently addressed 
XMT and RECEIVE analog switches are closed. The positive 
going edge of the MSB signal also updates the address code 
for the ana og switches. 

Additional timing analysis reveals that by using different and 
reduced maximum settling times, for the encode and decode 
portions of the above described data conversion protocol, the 
number of multiplexed channels can be significantly in- 
creased. However, the necessary logic for control and timing 
of unequal encode and decode data conversion time periods 
will be more complex than the logic shown in Figure 39. The 
same encode/decode alternating timing procedure, with 1.1 /as 
allocated for the A/D settling time, and with only 5.6/is al- 
lowed for D to A conversion, (not limited by the DAC), will re- 
sult in eight multiplexed channels. Systems requiring more 
than eight channels can be built using multi sample and hold 
circuits to reduce the input sampling time period. The 
maximum number of channels, limited by the Companding 
DAC's settling times, can be further increased by adjusting 
data clock frequency to its optimal values for each of the suc- 
cessive approximation bit-iterations, repeatedly, for every A/D 
data conversion. 



SUMMARY 

The Companding DAC was originally developed for the needs 
and requirements of PCM communication systems. When 
used to perform a decoder function, at an 8kHz sampling rate, 
a single Companding DAC can comfortably serve up to 24 
voice channels. As a part of the encoding scheme, the Com- 
panding DAC can accommodate 12 D3 communication chan- 
nels. For implementation in CODEC functions, the Com- 
panding DAC is ideal for single channel CODEC schemes. 
The length of the output current's settling time is the most im- 
portant parameter to be considered for the Companding 
DAC's implementation in multiple channel CODEC schemes. 
An 8 channel CODEC is probably an optimum number of 
channels which can be served by a single Companding DAC. 

The timing restrictions are not of such importance in industrial 
systems. A logarithmic-like, piece-wise transfer function and 
the very fine resolution and accuracy of a 12-bit linear DAC 
which are achievable in the Companding DAC's chord 0, pro- 
vides industrial systems with a very sensitive tool. In addition, 
the Companding DAC's compatibility with 8-bit micropro- 
cessors offers a very powerful control vehicle in the areas of 
data acquisition and instrumentation systems. A wide dynamic 
range of 78dB which can be extended by a cascading 
scheme to 156dB or more, and a high signal-to-distortion ratio 
of 80dB, allow usage of the Companding DACs for attenua- 
tion functions even in a high fidelity audio system. Industrial 
applications represent a large potential market for Com- 
panding DACs and they should be given serious consideration 
by industrial system designers. 



REFERENCES 

Transmission Systems for Communications, Bell Telephone Labs, Revised Fourth Edition, December 1971. 
The International Telegraph and Telephone Consultative Committee, CCITT, Green Book, Volume III - 2, 1973. 
American Telephone and Telegraph Company: The D3 Channel Bank Compatibility Specification, Issue 2, 1974. 
PCM Update - Parts 1 and 2, GTE Lenkurt, San Carlos, CA, 1975. 
A 
A 



User's Handbook of D/A and A/D Converters, E.R. Hnatek, John Wiley & Sons, 1976. 

Versatile Integrated CODEC for PCM Systems, J.A. Schoeff, 1976 International Zurich Seminar on Digital 
Communications. 

Applicaton Considerations for IC Data Converters Useful in Audio Signal Processing, W.G. Jung, 55th Convention of 
the Audio Engineering society, 1 976, An Audio Engineering Society preprint. 

A Monolithic Companding D/A Converter, J.A. Schoeff, 1977 ISSC Conference, Digest of Technical Papers, 
Philadelphia, PA, USA. 

The Am6070, Am6071, Am6072 and Am6073 Data Sheets, Advanced Micro Devices, Sunnyvale, CA, 1977. 



3-129 



Companding DAC 



CONVERSION COMPLETE 



CHANNEL 4 




SYSTEM RESET 



Fig. 39. 4-Channel PCM CODEC with Simultaneous XMT and Receive Data Transfers. 



MSB BIT OF 
4-BIT COUNTER 



DATA CLOCK 



SAMPLE SIGNAL 



CHANNEL 1 

31.25/-S 



(512kHz. 
1.95^5) 



HOLD CH 1 SAMPLE 2 



ALL 
SWITCHES 
OPENED 



SELECTED 

I PAIR 
CLOSED 



STORE RECEIVE 
DATA FOR CH 1 f 



ENCODING 1 ' DECODING 1 



CHANNEL 2 _ 

31.25mS 



HOLD 2 SAMPLE 3 



ALL 
OPENED 



SELECTED 
"I PAIR 
| CLOSED 



STORE CH 2 
DISABLE 

STORE OUT I E ! JABI 1 E 
STORE OUT 
NO DATA 



DECODING 2 



CHANNEL 3 

31.25ms 



HOLD 3 SAMPLE < 



ALL 
OPENED 



SELECTED 
I PAIR 
CLOSED 



STORE CH 3 
DISABLE 



DECODING 3 



ENCODING 3 



CHANNEL 4 _ 

31.25ms 



HOLD 4 SAMPLE 1 



SELECTED 
I PAIR 
I CLOSED 



STORE CH 4 
DISABLE 



DECODING A 



ENCODING 4 



SIGN BIT ENCODING 
(1 DATA CLOCK P 



Fig. 40. Ideal Timing Diagrams for 4-Channel PCM CODEC. 



3-130 




ALPHA NUMERIC INDEX 
FUNCTIONAL INDEX 
SELECTION GUIDES 
INDUSTRY CROSS REFERENCE 
DICE POLICY 
ORDERING INFORMATION 
MIL-M-3851 0/MIL-STD-883 



H 

Wtm 



1 




PACKAGE OUTLINES 
GLOSSARY 

AMD FIELD SALES OFFICES, SALES REPRESENTATIVES, 
DISTRIBUTOR LOCATIONS 



9 



Line Drivers/Receivers - Section IV 

Ami 488 Quad RS-232C Line Driver 4-1 

Ami 489 Quad RS-232C Line Receiver 4-4 

Am1489A Quad RS-232C Line Receiver 4-4 

Ami 692/3692 Three-State Differential Line Drivers 4-8 

Am25LS240 Octal Buffer; Inverting, Three-State 4-13 

Am25LS241 Octal Buffer; Non-Inverting, Three-State 4-17 

Am25LS242 Quad Three-State Bus Transceiver 4-21 

Am25LS243 Quad Three-State Bus Transceiver 4-21 

Am25LS244 Octal Buffer, Non-Inverting, Three-State 4-17 

Am26LS29 Quad Three-State Single-Ended RS-423 Line Driver 4-26 

Am26LS30 Dual Differential RS-422 Party Line/Quad Single-Ended 

RS-423 Line Driver 4-30 

Am26LS31 Quad RS-422 High-Speed Differential Line Driver 4-36 

Am26LS32 Quad RS-422 and RS-423 Differential Line Receiver 4-40 

Am26LS33 Quad Differential Line Receiver 4-40 

Am26S10 Quad Bus Transceiver 4-57 

Am26S1 1 Quad Bus Transceiver 4-57 

Am26S12 Quad Bus Transceiver 4-62 

Am26S12A Quad Bus Transceiver 4-62 

Am2614 Quad Single-Ended Line Driver 4-67 

Am2615 Dual Differential Line Receiver 4-72 

Am2616 Quad MIL-188C and RS-232C Line Driver 4-78 

Am261 7 Quad RS-232C Line Receiver 4-82 

Am2905 Quad Two-Input OC Bus Transceiver with Three-State Receiver 4-86 

Am2906 Quad Two-Input OC Bus Transceiver with Parity 4-92 

Am2907 Quad Bus Transceiver with Interface Logic 4-98 

Am2908 Quad Bus Transceiver with Interface Logic 4-98 

Am2915A Quad Three-State Bus Transceiver with Interface Logic 4-107 

Am2916A Quad Three-State Bus Transceiver with Interface Logic 4-113 

Am2917A Quad Three-State Bus Transceiver with Interface Logic 4-119 

Am3212 8-Bit Input/Output Port 4-125 

Am3216 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am3226 4-Bit Parallel Bidirectional Bus Driver 4-132 

Am3448A IEEE-488 Quad Bidirectional Transceiver 4-137 

Am54LS/74LS240 Octal Buffer; Inverting, Three-State 4-13 

Am54LS/74LS241 Octal Buffer; Non-Inverting, Three-State 4-17 

Am54LS/74LS242 Quad Three-State Bus Transceiver 4-21 

Am54LS/74LS243 Quad Three-State Bus Transceiver 4-21 

Am54LS/74LS244 Octal Buffer; Non-Inverting, Three-State 4-17 

Am54S/74S240 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am54S/74S241 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am54S/74S242 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-1 42 

Am54S/74S243 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am54S/74S244 Octal Buffer/Line Driver/Line Receiver 

with Three-State Outputs 4-142 

Am55/75107B Dual Line Receiver 4-147 

Am55/75108B Dual Line Receiver 4-147 

Am55/75109 Dual Line Driver 4-153 

Am55/751 10 Dual Line Driver 4-153 

Am71LS/81LS95 Three-State Octal Buffers 4-159 

Am71 LS/81 LS96 Three-State Octal Buffers 4-159 



Line Drivers/Receivers - Section IV (Cont.) 



Am71 LS/81 LS97 
Am71 LS/81 LS98 
Am73/8303B 
Am73/8304B 
Am78/8820 
Am78/8820A 
Am78/8830 
Am78/8831 
Am78/8832 
Am78/8838 
Am8T26 
Am8T26A 
Am8T28 
Am8212 
Am8216 
Am8226 
Am9614 
Am9615 
Am9616 
Am9617 



Three-State Octal Buffers 4-159 

Three-State Octal Buffers 4-159 

Octal Three-State Inverting Bidirectional Transceiver 4-163 

Octal Three-State Bidirectional Transceiver 4-168 

Dual Differential Line Receiver 4-173 

Dual Differential Line Receiver 4-173 

Dual Differential Line Driver 4-178 

Three-State Line Driver 4-182 

Three-State Line Driver 4-182 

Quad Unified Bus Transceiver 4-188 

Schottky Three-State Quad Bus Driver/Receiver 4-190 

Schottky Three-State Quad Bus Driver/Receiver 4-195 

Schottky Three-State Quad Bus Driver/Receiver 4-1 95 

8-Bit Input/Output Port 4-125 

4-Bit Parallel Bidirectional Bus Driver 4-132 

4-Bit Parallel Bidirectional Bus Driver 4-132 

Differential Line Driver 4-200 

Dual Differential Line Receiver 4-72 

Triple EIA RS-232C/MIL-STD-188C Line Driver 4-205 

RS-232C Line Receiver 4-209 



Application Notes 

Use of the Am26LS29, 30, 31 and 32 Quad Driver/Receiver 
Family in EIA-422 and 423 Applications 



4-45 



Am1488 

Quad RS-232C Line Driver 



Distinctive Characteristics: 

• Conforms to EIA specification RS-232C 

• Short circuit protected output 

• Simple slew rate control with external capacitor 



• 100% reliability assurance testing in compliance with 
MIL STD 883 

• TTL/DTL compatible input 



FUNCTIONAL DESCRIPTION 

The Am1488 is a quad line driver that conforms to EIA speci- 
fication RS-232C. Each driver accepts one or two TTL/DTL 
inputs and produces a high-level logic signal on its output. 
The HIGH and LOW logic levels on the output are defined by 
the positive and negative power supplies to the drivers. For 
power supplies of plus and minus nine volts, the output levels 
are guaranteed to meet the ±6-volt specification with a 3kS2 
load. There is an internal 300S2 resistor in series with the 
output to provide current limiting in both the HIGH and LOW 
levels. The Ami 488 driver is intended for use with the 



logic 

Am1489 or Am1489A quad line receivers. 



LOGIC SYMBOL 



B) IN - 
B2 IN - 

CI IN - 
C2 IN - 

D1 IN - 
D2IN- 



-o 
id- 
d- 
id- 



V- = Pin 1 

= Pin 14 
GND = Pin 7 



CIRCUIT DIAGRAM 
(one driver shown) 




Am1488 ORDERING INFORMATION 



Package Temperature Order 

Type Range Number 



Hermetic DIP 
Molded DIP 
Dice 



D C to +75 C 
0°C to +75°C 
0°C to +75°C 



MC1488L 

AM1488PC 

AM1488XC 



CONNECTION DIAGRAM 
Top View 



A IN Q 2 

A OUT f~ 3 

81 IN ^ 4 

B2 IN Q 5 

B OUT Q 6 

GND 7 



14 ^ V* 

|3 ^] D2 IN 

12 □ D1 IN 
11 D OUT 

10 □ C2 IN 

9 ^ CI IN 

8 ^[ C OUT 



4-1 



Ami 488 

MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature — 65°C to +175°C 

Temperature (Ambient) Under Bias 0°C to +75°C 



Supply Voltage 


to Ground Potential 


v- 


+15V 
-15V 


DC Voltage App 


lied to Outputs for High Output State 


(V + +5.0V) > V„ > (V 


-5.0V) 


DC Input Voltac 


e 




±15V 







ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

The following conditions apply unless otherwise specified: 

T A = 0°C to +75° C. V + - +9.0V, V- = -9.0V 



Parameters Description Test Conditions Min. (Notei) Max. Units 



1 1 L. 




Logical "0" Input Current 


V| N = 0V 




—1 .0 


—1 .6 


mA 


■|H 




Logical "1" Input Current 


V| N =+5.0V 




0.005 


1 0.0 


MA 


V H 




High Level Output Voltage 


R|_ = 3.0kfi, 


V+ = 9.0V, V~ = -9.0V 


6 


7 




Volts 




V| N =0.8V 


V+= 13.2V, V- = -13.2V 


9.0 


10.5 




Volts 


vol 




Low Level Output Voltage 


RL - 3.0kS2, 


V + = 9.0V, V- = -9.0V 


—6 


—6 8 




Volts 




V !N = 1.9V 


V+ - *3.2V, V- = -13.2V 


-9.0 


-10.5 




Volts 


"sc+ 




High Level Output 
Short-Circuit Current 


V UT = 0V, V| N = 0.8V 


-6.0 


-10.0 


-12.0 


mA 


•sc- 




Low Level Output 
Short-Circuit Current 


VOUT = OV, V| N = 1.9V 


6.0 


10.0 


12.0 


mA 


R OUT 




Output Resistance 


V+ = V- = 0V. VquT " ±2.0V 


300 






n 










V+ = 9.0V, V- = -9.0V 




15.0 


20.0 


mA 








V| N = 1.9V 


V+ = 12V, V- = -12V 




19.0 


25.0 


mA 


icc+ 




Positive Supply Current 




V+ - 15V, V-= -15V 




25.0 


34.0 


mA 




(Output Open) 




V+- 9.0V, V-= 9.0V 




4.5 


6.0 


mA 








Vim = 0.8V 


V+ = 12V, V- = -12V 




5.5 


7.0 


mA 










V + - 15V, V- = -15V 




8.0 


12.0 


mA 










V+ » 9.0V, V- » -9.0V 




-13.0 


-17.0 


mA 








V|M = 1.9V 


V+ = 12V, V- = -12V 




-18.0 


-23.0 


mA 


'cc- 




Negative Supply Current 




V+ = 15V, V~=-15V 




-25.0 


-34.0 


mA 




(Output Open) 




V+ = 9.0V, V- = -9.0V 




-1.0 


-15 


HA 








V| N = 0.8 V 


V+ = 12 V, V-=-12V 




-1.0 


-15 


MA 










V+ = 15V, V- = -15V 




-0.01 


-2.5 


mA 


Pd 




Power Dissipation 


V+ = 9.0V, V- = -9.0V 




252 


333 


mW 




V+ » 12V, V- - -12V 




444 


576 


mW 



Switching Characteristics (T A = 25°c, v = +9.0V, v = -9.0V) 



Parameters 


Definition 


Test Conditions 


Min 


Typ 


Max 


Units 


tPLH 


Delay from input LOW to output HIGH 






275 


350 


ns 


•PHL 


Delay from input HIGH to output LOW 


Z L = 3.0 kS2 




110 


175 


ns 


t r 


Output rise time 


and 15 pF 




55 


100 


ns 


*, 


Output fall time 






45 


75 


ns 



Note 1 . Tvpical values are for T A = 25° C. 



Ami 488 



TYPICAL CHARACTERISTICS 



Transfer Characteristics Output Slew Rate Output Voltage and 

versus Power-Supply Voltage versus Load Capacitance Current-Limiting Characteristics 




Short-Circuit Output Current 
versus Temperature 




25 75 125 

AMBIENT TEMPERATURE ("CI 



Maximum Operating Temperature 
versus Power-Supply Voltage 



5 12 
g io 








































































































Vl 


,-Of 


EN 













T. TEMPERATURE ("CI 



Metallization and Pad Layout 



2 1 14 13 




6 7 8 



DIE SIZE 0.053" X 0.054" 



4-3 



Am1489«Am1489A 

Quad RS-232C Line Receivers 



Distinctive Characteristics: 

• Compatible with EIA specification RS-232C 

• Input signal range ±30 volts 



• 100% reliability assurance testing in compliance with 
MIL STD 883 

• Includes response control input and built-in hysterisis 



FUNCTIONAL DESCRIPTION: 

The Am1489 and Am1489A are quad line receivers whose electrical char- 
acteristics conform to EIA specification RS-232C. Each receiver has a 
single data input that can accept signal swings of up to ±30 V. The output 
of each receiver is TTL/DTL compatible, and includes a 2kQ resistor 
pull-up to V Cc . An internal feedback resistor causes the input to exhibit 
hysterisis so that AC noise immunity is maintained at a high level even 
near the switching thresholds. For both devices, when a receiver is in a LOW 
state on the output, the input may drop as LOW as 1 .25 volts without 
affecting the output. Both devices are guaranteed to switch to the HIGH 
state when the input voltage is below 0.75 V. Once the output has switched 
to the HIGH state, the input may rise to 1.0 V for the Am1489 or 1.75 V 
for the Am1489A without causing a change in the output. The Am1489 is 
guaranteed to switch to a LOW output when its input reaches 1.5 V and, 
the Am1489A is guaranteed to switch to a LOW output when its input 
reaches 2,25 V. Because of this hysterisis in switching thresholds, the 
devices can receive signals with superimposed noise or with slow rise and 
fall times without generating oscillations on the output. The threshold 
levels may be offset by a constant voltage by applying a DC bias to the 
response control input. A capacitor added to the response control input 
will reduce the frequency response of the receiver for applications in the 
presence of high frequency noise spikes. The companion line driver is 
the Am1488. 



LOGIC SYMBOL 



IN A - 

R.C. A ■ 



9~ 



9- 



INC ■ 

R.C. C ■ 



V CC = PIN 14 
GND = PIN 7 



□ 



CIRCUIT DIAGRAM 
(one receiver) 



Rt = 10k£I (AM1489) 
Rf= 2kn(AM1489A) 



< 



< 



< 



Am1489/Am1489A ORDERING INFORMATION 



Package 
Type 



Temperature 
Range 



Am1489 Am1489A 
Order Order 
Number Number 



14-pin Molded DIP 
14-pin Hermetic DIP 
Dice 



0°Cto +75°C 
0°C to +75°C 
0°C to +75°C 




AM1489APC 
MC1489AL 
IAXC 



CONNECTION DIAGRAM 
Top View 



A IN Q 1* 

A R.C. Q 2 

A OUT Q 3 

B IN Q 4 

B R.C. Q 5 

B OUT □ 6 

GND Q 7 



14 □ V CC 

13 ^] D IN 

12 □ D R.C 

11 ^\ D OUT 

10 ^] C IN 

9 ^] C R.C 

8 ~J C OUT 



NOTE: PIN 1 is marked for orientation. 



4-4 



u~G to +/i>"U 



Supply Voltage to Ground Potential (Pin 14 to Pin 7) Continuous -0.5 V to +10 V 

DC Voltage Applied to Outputs for High Output State -0.5 V to +V CC max 



Input Signal Range -30 V to +30 V 



Output 


Current, Into Outputs 


30 mA 


DC Inpt 


t Current 


Defined by Input Voltage Limits 







ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) 

V CC = 5.0V ±1% Response control pin open 



Am1489. Am1489A T A = 0°C lo +75°C 

Parameters Description 



Test Conditions 



Min 



Typ (Note 1) 



Max 



Units 



V OH 




Output HIGH Voltage 


l 0H = -0.5 mA 

V, N = +0.75 V or open 


2.6 


4.0 




Volts 


Vol 




Output LOW Voltage 


l OL = 10 mA 
V IN = 3.0V 




0.2 


0.45 


Volts 


V,H 




Input HIGH Level Threshold 


T A = 25°C 
V OL = 0.45 V 


Ami 489 


1.0 


1.25 


1.5 


Volts 


Am1489A 


1.75 


1.95 


2 .25 






Input LOW Level Threshold 


T A = 25°C, V OH = +2.5 V 


0.75 




1.25 


Volts 






Input LOW Current 


V IN = -3.0V 


-0.43 






mA 


V IN = -25V 


-3.6 




-8.3 






Input HIGH Current 


V IN = +3.0 V 


0.43 






mA 


V IN = +25 V 


3.6 




8.3 


'sc 




Output Short Circuit Current 


V 1N = 0.0 V 
Vqut = 0.0 V 




3.0 




mA 


'cc 




Power Supply Current 


V cc = MAX. 




20 


26 


mA 



Note: 1) Typical Limits are at V cc = 5.0 V, 25°C ambient and maximum loading. 



Switching Characteristics (T A = 25°C, response control pin open, C L = 15 pFj 



Parameters 


Definition 


Test Conditions 


Min 


Typ 


Max 


Units 


«PLH 


Delay from Input LOW to Output HIGH 


R L = 3.9 k£2 




25 


85 


■ 

ns 


«PHL 


Delay from Input HIGH to output LOW 


R L = 390 !> 




25 


50 


ns 


tr 


Output Rise Time (10% to 90%) 


R L = 3.9 kS2 




120 


175 


ns 


tf 


Output Fall Time (90% to 10%) 


R L = 390 a 




10 


20 


ns 



4-5 



TYPICAL CHARACTERISTICS 



1 489 A 



Input Current 




-25 -15 -5.0 +5 +15 +25 
Vi n , INPUT VOLTAGE (VOLTS) 



Ami 489 Input Threshold 
Voltage Adjustment 





















































R T 

5kft 
Vth 
+5V 


"R 
V 

+ 


r 

k f ,! 

h 


Rt 

-co 




•ii 








kG 






v t 


i 






V 








V 



























































































-3 0-2.0-1.0 +1.0 +2.0 +3.0 +4.0 +5.0 
Vin, INPUT VOLTAGE 



Am1489A Input Threshold 
Voltage Adjustment 







































































^T 
IkSi 






5kil 








Rl 








Vth 












Vth 

sv 




+5 

















































































































-3.0-2,0-1.0 +1.0+2.0+3.0+4.0+5.0 
Vin, INPUT VOLTAGE 






Input Threshold Voltage 
versus Temperature 




-60 +60 +120 

AMBIENT TEMPERATURE IX, 



Input Threshold versus 
Power-Supply Voltage 

























































V| H 1 


89 










V|i_ 1489 










Vil 1 


189A 











































□ 



V+ : POWER SUPPLY VOLTAGE 



4-6 



Ami 489/1 489A 



SWITCHING TIME TEST CIRCUIT & WAVEFORMS 




LIC-324 



LIC-325 



Metallization and Pad Layout 

A IN VCC D IN 



1 14 13 




5 7 8 
B OUT GNDCOUT 



DIE SIZE 0.047" X 0.059" 



4-7 



Ami 692/3692 

Three-State Differential Line Drivers 



DISTINCTIVE CHARACTERISTICS 



Individual three-state enables for each driver 
Dual differential driver or quad single ended line driver 
Short circuit protection for both source and sink outputs 
Individual rise time control for each output 
50O transmission line drive capability 
High capacitive load drive capability 
Low l cc and l EE power consumption 
Differential mode 35mW/driver 
Single-ended mode 26mW/driver 
Low current PNP inputs compatible with TTL, 
Advanced low power Schottky processing 
100% reliability assurance screening to MIL-STD-883 
requirements 



FUNCTIONAL DESCRIPTION 

The Am1692/Am3692 are low power Schottky TTL line drivers 
with three-state outputs. They feature ±10V output common 
mode range in three-state and 0V output unbalance when oper- 
ated with ±5V power supplies. They feature 4 buffered outputs 
with high source and sink current capability with internal short 
circuit protection. 

A mode control input provides a choice of operation either as four 
independent line drivers or two differential line drivers. A rise time 
control pin allows the use of an external capacitor to reduce rise 
time for suppression of near end crosstalk to other receivers in the 
cable. 

The Am 1692/3692 is constructed using advanced low-power 
Schottky processing. 



LOGIC DIAGRAM 
(1/2 Circuit Shown) 



INPUT A (D) O 

INPUT B (C) 
TRI-STATE O- 
DISABLE 



MODE O 




Package 
Type 



ORDERING INFORMATION 



Temperature 
Range 



Order 
Number 



Hermetic DIP 
Hermetic Flat Pak 
Hermetic DIP 
Molded DIP 



-55°C to +125°C 
-55°Cto +125"C 
0°C to +70°C 
0°C to +70°C 



DS1692J 
DS1692F 
DS3692J 
DS3692N 



CONNECTION DIAGRAM 
Top View 




□ RISE TIME CONTROL A 

□ OUTPUT A 

□ OUTPUT B 

□ RISE TIME CONTROL B 

□ RISE TIME CONTROL C 

□ OUTPUT C 

□ OUTPUT D 

□ RISE TIME CONTROL D 



Note: Pin 1 is marked for orientation. 



4-8 



Ami 692/3692 

ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65°C to + 150°C 



Supply Voltage 

V+ 



7.0V 



V- 



-7.0V 



Power Dissipation 



600mW 



Input Voltage 



-0.5 to +15V 



Output Voltage (Power Off) 



;15V 



Lead Soldering Temperature (10 seconds) 



300°C 



ELECTRICAL CHARACTERISTICS over the operating temperature range 
The following conditions apply unless otherwise specified: 

Ami 692 (MIL) T A = -55°C to + 125°C V cc = 5.0V ±10%, V EE = GND 

Am3692 (COM'L) T A = 0°C to +70°C V cc . 

Mode Voltage « 0.8V 

DC CHARACTERISTICS over the operating temperature range 



Parameters 



Description 



Test Conditions (Note 2) 



Min. 



Typ. 

(Note 1) 



Max. 



Units 



v 




Differential Output Voltage, V A>B 


R L = » 


V, N = 2.0V 


2.5 


3.6 


6.0 


Volts 


v 




V IN = 0.8V 


-2.5 


-3.6 


-6.0 


Volts 


V T 


Differential Output Voltage, V AiB 


r l = ioon 


V IN = 2.0V 


2 


2.6 




Volts 


vf 


V| N = 0.8V 


-2 


-2.6 




Volts 


Vos. Vol" 


Common-Mode Offset Voltage 


R L ~ 100fl 




2.5 


3 


Volts 


|v T | - 




Difference in Differential Output Voltage 


r l = ioon 




0.05 


0.4 


Volts 


I Vos I 


- I Vos | 


Difference in Common-Mode Offset Voltage 


r l = ioon 




0.05 


0.4 


Volts 


v S s 




|v T - vF| 


R L = 100S1 


4.0 


4.8 




Volts 


IXA 




Output Leakage Current 


v cc = o 


V = 15V 




10 


150 


^A 


IXB 




V = -15V 




-10 


-150 


/aA 


bx 




Three-State Output Current 


V, N = 2.4V, V * -10V 






-150 


mA 


V, N = 0.4V, V « 15V 






150 


mA 


ISA 




Output Short Circuit Current 


V| N = 2.4V 


V 0A = 6.0V 




80 


150 


mA 


V 0B = 0V 




-80 


-150 


mA 


!SB 




V, N = 0.4V 


V A = ov 




-80 


-150 


mA 


V 0B = 6.0V 




80 


150 


mA 


ice 




Supply Current 






18 


30 


mA 



Notes: 1. Typical limits are at Vcc = 5 0V . v ee = GND, 25°C ambient and maximum loading. 
2. R L connected between each output and its complement. 



4-9 



Ami 692/3692 



ELECTRICAL CHARACTERISTICS over the operating temperature range 
The following conditions apply unless otherwise specified: 

Am1692 (MIL) T A = -55°C to +125°C V cc = 5.0V +10%, V EE = -5.0V ±10% 

Am3692 (COM'L) T A = 0°C to +70°C V cc = 5.0V ±5%, V EE = -5.0V ±5% 

Mode Voltage s 0.8V 

DC CHARACTERISTICS over the operating temperature range unless otherwise noted 



Typ. 



Parameters 


Description 


Test Conditions 


Min. 


(Note 1) 


Max. 


Units 


v 




Output Voltage 


R|_ = co 


V| N = 2.4V 


7 


8.5 


12 


Volts 


v 




V, N = 0.4V 


-7 


-8.5 


-12 


Volts 


v T 




Output Voltage 


R[_ - 200n 


V, N - 2.4V 


6 


7.3 




Volts 


v T 




V, N = 0.4V 


-6 


-7.3 




Volts 


|V T | - |V T 




Output Unbalance 


|V CC I = |V ee |.Rl 


= 200n 




0.02 


0.4 


Volts 


lx + 




Output Leakage Power OFF 


v C c = v EE = ov 


V = 15V 




20 


150 


mA 


hT 




V = -15V 




-20 


-150 


mA 


lox 




Three-State Output Current 


V| N -2.4V, V * -10V 






-150 


liA 




V m = 0.4V, V s 10V 






150 


/iA 


ls + 




Output Short Circuit Current 


V o = 0V 


V m = 2.4V 




-80 


-150 


mA 


is 




V, N = 0.4V 




80 


150 


mA 


'slew 




Slew Control Current 






±140 




fiA 


Ice 




Positive Supply Current 


V, N = 0.4V, R L = =» 




18 


30 


mA 


Iee 




Negative Supply Current 


V !N = 0.4V, R L = co 




-10 


-22 


mA 


V,H 




High Level Input Voltage 






2 






Volts 


V,L 




Low Level Input Voltage 










0.8 


Volts 


l|H 




High Level Input Current 


±5.25 s V EE =s 0V 


V, N = 2.4V 




1 


40 


fj.A 




V m s 15V 




10 


100 


l, L 




Low Level Input Current 




V m = 0.4V 




-30 


-200 


m a 






Input Clamp Voltage 




l| N = -12mA 






-1.5 


Volts 



Note: Typical values are at V cc = 5.0V, V EE = -5.0V, 25°C ambient and maximum loading. 



AC CHARACTERISTICS T A = 25'C 



Parameters 


Description 


Test Conditions 


Min. 


Typ. 


Max. 


Units 


V cc = 5.0V, Mode Select = 8.0V 


tr 




Differential Output Rise Time 


R[_ = 100O, C L = 500pF, (Fig. 1) 




120 


200 


ns 


tf 




Differential Output Fall Time 


R[_ = 100O, C L = 500pF, (Fig. 1) 




120 


200 


ns 


tpDH 




Output Propagation Delay 


R[_ = 1000, C L = 500pF, (Fig. 1) 




120 


200 


ns 


tpDL 




Output Propagation Delay 


R[_ = 100n, C L = 500pF, (Fig. 1) 




120 


200 


ns 


tpZL 




Three-State Delay 


R u = 1000, C L = 500pF, (Fig. 2) 




180 


250 


ns 


tpZH 




Three-State Delay 


R[_ = 100n, C L = 500pF, (Fig. 2) 




180 


250 


ns 


'PLZ 




Three-State Delay 


R L = 1000, C L = 500pF, (Fig. 2) 




80 


150 


ns 


tpHZ 




Three-State Delay 


R u = 100n, C L = 500pF, (Fig. 2) 




80 


150 


ns 


V cc = 5.0V, V EE = -5.0V, Mode Select = 0.8V 


tr 


Differential Output Rise Time 


R[_ = 200n, C L = 500pF, (Fig. 1) 




190 


300 


ns 


tf 


Differential Output Fall Time 


R(_ = 200O, C u = 500pF, (Fig. 1) 




190 


300 


ns 


tpDL 


Output Propagation Delay 


R L = 2000, C L = 500pF, (Fig. 1) 




190 


300 


ns 


tpDH 


Output Propagation Delay 


R[_ = 200n, C L = 500pF, (Fig. 1) 




190 


300 


ns 


tpZL 




Three-State Delay 


R L = 200O, C L = 500pF, (Fig. 2) 




180 


250 


ns 


Wh 




Three-State Delay 


R L = 200O, C L = 500pF, (Fig. 2) 




180 


250 


ns 


tpLZ 




Three-State Delay 


R L = 2000, C L = 500pF, (Fig. 2) 




80 


150 


ns 


tpHZ 




Three-State Delay 


R L = 2000, C L = 500pF, (Fig. 2) 




80 


150 


ns 



4-10 



Ami 692/3692 



Ami 692/3692 FUNCTIONAL TABLE 



Mode 


Inputs 


Outputs 


A(D) B(C) 


A(D) B(C) 








1 





1 


z z 





1 


1 





1 1 


z z 


1 


o o 





1 


1 


1 


1 


1 


1 


1 


1 1 


1 1 



SWITCHING TIME WAVEFORMS AND AC TEST CIRCUIT 



^ \, < 10m 



, OV INPUT O- 



09VSS/RL 



s 

VSS/RL 



°.9Vss/RL 
O.IVss/RL 



v E e - 





■TEKCTR 
CURRENT TRANSF. 
OR EQUIVALENT 



BLI0O9 

•Current probe is the easiest way to display a differential waveform. 



Figure 1. Rise and Fall Time 



Vcc — - 



r 



Vle 





(INPUT A HIGH) 



•TEK CTR 

CURRENT TRANSF. (INPUT A LOW) 

OR EQUIVALENT 



m NT 



l PHZ 



- <PLZ OUTPUT 



•PZH - 



0.1 V SS /R L 



r 



^ ^ 0.5 V ss l 



tpZL — 0.3 V SS /R L 

V S s"<L 



Figure 2. Three State Delays 



4-11 



Ami 692/3692 



Slew Rate (Rise or Fall Time) 
Versus External Capacitor 




Am25LS240«Am54LS/74LS240 

Octal Three-State Inverting Drivers 



DISTINCTIVE CHARACTERISTICS 

• Three-state outputs drive bus lines directly 

• Hysteresis at inputs improve noise margin 

• PNP inputs reduce D.C. loading on bus lines 

• Data-to-output propagation delay times - 18ns MAX. 

• Enable-to-output - 30ns MAX. 

• Am25LS240 specified at 48mA output current 

• 20 pin hermetic and molded DIP packages 

• 100% product assurance testing to MIL-STD-883 
requirements 



FUNCTIONAL DESCRIPTION 

The 'LS240 is an octal inverting line driver fabricated using 
advanced low-power Schottky technology. The 20-pin 
package provides improved printed circuit board density for 
use in memory address and clock driver applications. 

Three-state outputs are provided to drive bus lines directly. 
The Am25LS240 is specified at 48mA and 24mA output sink 
current, while the Am54/74LS240 is guaranteed at 12mA over 
the military range and 24mA over the commercial range. 
Four buffers are enabled from one common line and the 
other four from a second enable line. 

Improved noise rejection and high fan-out are provided by 
input hysteresis and low current PNP inputs. 



LOGIC DIAGRAM 



- 1 Y3 2A3 - 



INPUTS 


OUTPUT 


G 


A 


Y 


H 


X 


z 


L 


H 


L 


L 


L 


H 



Note: All devices have input hysteresis. 



CONNECTION DIAGRAM 
Top View 





1* 


20 


□ v cc 


1A1 |^ 


2 


19 




2Y4 Q 


3 


18 


^ 1Y1 


1A2 Q 




17 


^ 2A4 


2Y3 


S 

LS240 


16 


n iv2 


1A3 £2 


6 


15 


^ 2A3 


2Y2 Q 




14 


1Y3 


1A4 


8 


13 


Z] 2A2 


2Y1 


9 


12 


^ 1Y4 


GND Q 


10 


11 


zi 2ai 



Note: Pin 1 is marked for orientation. 



LOGIC SYMBOL 



2 4 6 



11 13 15 17 



1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 
1G LS240 2G 

1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 



TTTTTTTT 



18 16 14 12 



Vcc = pin 20 
GND = Pin 10 



4-13 



Am25LS/54LS/74LS240 



Am25LS240 

ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Specified: 
COM'L T A = 0°C to +70°C V cc = 5.0V ± 5% (MIN. = 4.75V 
MIL T A = -55°C to + 125°C V cc = 5.0V ± 10% (MIN. = 4.50V 

DC CHARACTERISTICS OVER OPERATING RANGE 



Parameters 



MAX. = 5.25V) 
MAX. = 5.50V) 



Description 



Test Conditions (Note 1) 



Min. 



Typ. 

(Note 2) 



Max. Units 



V 0H 


High-Level Output Voltage 


V cc = MIN., V m = 2.0V 

l 0H = -3.0mA, V, L = V, L MAX. 


2.4 


3.4 




Volts 


V cc = MIN.. 
V, L = 0.5V 


MIL, l 0H = -12mA 


2.0 






COM'L, I h= -15mA 


2.0 






Vol 


Low-Level Output Voltage 


V C C = MIN. 


All l 0L = 12mA 




0.25 


0.4 


Volts 


All l 0L = 24mA 




0.35 


0.5 


COM'L l OL = 48mA 






0.55 


V,H 


High-Level Input Voltage 


Guaranteed input logical HIGH 
voltage for all inputs 


2.0 






Volts 


V,L 


Low-Level Input Voltage 


COM'L 








0.8 


Volts 


MIL 








0.7 


V,K 


Input Clamp Voltage 


V CC = MIN - h = -18mA 






-1.5 


Volts 




Hysteresis (Vj + — Vj_) 


V CC = MIN. 


0.2 


0.4 




Volts 


'OZH 


Off-State Output Current, 
High Level Voltage Applied 


V CC = MAX. 
V, H = 2.0V 
V, L = V, L MAX. 


V = 2.7V 






20 


ma 


bZL 


Off-State Output Current, 
Low-Level Voltage Applied 


V = 0.4V 






-20 


■l 


Input Current at Maximum 
Input Voltage 


V cc = MAX., V, = 7.0V 






0.1 


mA 


>IH 


High-Level Input Current, Any Input 


V cc MAX., V, H = 2.7V 






20 


MA 


■|L 


Low-Level Input Current 


V CC = MAX - Vil = 0.4V 






-200 


mA 


■sc 


Short Circuit Output Current (Note 3) 


V CC = MAX. 


-40 




-225 


mA 


'cc 


Supply Current 


V cc = MAX. 
Outputs open 


All Outputs HIGH 




13 


23 


mA 


All Outputs LOW 




26 


44 


Outputs at Hi-Z 




29 


50 



Notes: 1 . Fo conditions shown as MIN. or MAX., use the appropriate value specified under recommended operating conditions. 

2. All typical values are Vcc = 5.0V, Ta = 25°C. 

3. Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 



MAXIMUM RATINGS above which the useful life may be impaired 



Storage Temperature 


-65°C to +150°C 


Temperature (Ambient) Under Bias 


-55°Cto +125°C 


Supply Voltage to Ground Potential 


-0.5V to +7.0V 


DC Voltage Applied to Outputs for HIGH Output State 


-0.5V to +V CC max. 


DC Input Voltage 


-0.5V to +7.0V 


DC Output Current 


150mA 


DC Input Current 


-30mA to +5.0mA 



4-14 



Am25LS/54LS/74LS240 

Am54LS/74LS240 

ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Specified: 

COM'L T A = 0°C to +70°C V cc = 5.0V ± 5% (MIN. = 4.75V MAX. = 5.25V) 

MIL T A = -55°C to + 125°C V cc = 5.0V ± 10% (MIN. = 4.50V MAX. = 5.50V) 

DC CHARACTERISTICS OVER OPERATING RANGE 



Typ. 

Parameters Description Test Conditions (Note 1) Min. (Note 2) Max. Units 



V H 




High-Level Output Voltage 


V cc = MIN., V| H = 2.0V 

I h = -3.0mA, V, L = V| L MAX. 


2.4 


3.4 




Volts 


V cc = MIN., 
V, L = 0.5V 


MIL, l 0H = -12mA 


2.0 






COM'L, l 0H = -15mA 


2.0 






V 0L 




Low-Level Output Voltage 


V CC = MIN. 


All, l 0L = 12mA 




0.25 


0.4 


Volts 


COM'L, l 0L = 24mA 




0.35 


0.5 







High-Level Input Voltage 


Guaranteed input logical HIGH 
voltage for all inputs 


2.0 






Volts 


V|t 




Low-Level Input Voltage 


COM'L 








0.8 


Volts 


MIL 








0.7 


V,K 




Input Clamp Voltage 


V cc = MIN - 'l = -18mA 






-1.5 


Volts 






Hysteresis (V T+ - V T _) 


V cc = MIN. 


0.2 


0.4 




Volts 


■OZH 




Off-State Output Current, 
High Level Voltage Applied 


V cc = MAX. 
V IH - 2.0V 
V, L = V, L MAX. 


V = 2.7V 






20 


MA 


■oZL 




Off-State Output Current, 
Low-Level Voltage Applied 


V = 0.4V 






-20 


■l 




Input Current at Maximum 
Input Voltage 


V CC = MAX., V, = 7.0V 






0.1 


mA 


■iH 




High-Level Input Current, Any Input I V cc MAX., V m = 2.7V 20 


^A 


■|L 




Low-Level Input Current 


V cc = MAX., V| L = 0.4V 






-200 




■sc 




Short Circuit Output Current (Note 3) 


V cc = MAX. 


-40 




-225 


mA 


ice 




Supply Current 


V cc = MAX. 
Outputs open 


All Outputs HIGH 




13 


23 


mA 


All Outputs LOW 




26 


44 


Outputs at Hi-Z 




29 


50 


Notes: 1. 
2. 
3. 


For conditions shown as MIN. or MAX., use the appropriate value specified under recommended operating conditions. 
All typical values are Vcc = 5.0V, Ta = 25°C. 

Vlot more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 



Metallization and Pad Layout 




DIE SIZE 0.060" X 0.103' 



4-15 



Am25LS/54LS/74LS240 



SWITCHING CHARACTERISTICS 

(T A = +25°C, V cc = 5.0V) 



Parameters 


' " 

Description 


Am25LS240 
Min. Typ. Max. 


Am54LS/74LS240 
Min. Typ. Max. 


Test Conditions 
Units {Notes 1-5) 


tpi_H 


Propagation Delay Time, 
Low-to-High-Level Output 




8.0 


12 




9.0 


14 


ns 


C L = 45pF 
R u = 66711 


tpHL 


Propagation Delay Time, 
High-to-Low-Level Output 




12 


16 




12 


18 


ns 


*PZL 


Output Enable Time to Low Level 




19 


27 




20 


30 


ns 


*PZH 


Output Enable Time to High Level 




14 


20 




15 


23 


ns 


»PLZ 


Output Disable Time from Low Level 




14 


23 




15 


25 


ns 


C L = 5.0pF 
R L = 66711 


*PHZ 


Output Disable Time from High Level 




10 


18 




10 


18 


ns 



Am25LS ONLY 

SWITCHING CHARACTERISTICS 
OVER OPERATING RANGE* 

Parameters Description 


Am25LS COM'L 


Am25LS MIL 


Units Test Conditions 


T A = OX to +70°C 
V cc = 5.0V ±5% 
Min. Max. 


T A = -55°Cto + 125X 
V cc = 5.0V ±10% 
Min. Max. 


*PLH 


Propagation Delay Time, 
Low-to-High-Level Output 




16 




19 


ns 


C u = 45pF 
R L = 667H 


*PHL 


Propagation Delay Time, 
High-to-Low-Level Output 




22 




25 


ns 


*PZL 


Output Enable Time to Low Level 




37 




42 


ns 


*PZH 


Output Enable Time to High Level 




27 




31 


ns 


*PLZ 


Output Disable Time from Low Level 




31 




36 


ns 


C L = 5.0pF 
R L = 66711 


tpHZ 


Output Disable Time from High Level 




25 




28 


ns 



*AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9. 



LOAD CIRCUIT FOR VOLTAGE WAVEFORMS 

THREE-STATE OUTPUTS ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS 




Notes: 7. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 

2. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 

3. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. PRR < 1.0MHz, Z OUT «* 50U 
and t r < 2.5ns, tf < 2.5ns. 



4-16 



Am25LS241 • Am54LS/74LS241 
Am25LS244 • Am54LS/74LS244 

Octal Three-State Buffers 



DISTINCTIVE CHARACTERISTICS 

• Three-state outputs drive bus lines directly 

• Hysteresis at inputs improve noise margin 

• PNP inputs reduce D.C. loading on bus lines 

• Data-to-output propagation delay times - 18ns MAX. 

• Enable-to-output - 30ns MAX. 

• Am25LS241 and 244 specified at 48mA output current 

• 20 pin hermetic and molded DIP packages 

• 100% product assurance testing to MIL-STD-883 
requirements 



FUNCTIONAL DESCRIPTION 

The 'LS241 and 'LS244 are octal buffers fabricated using 
advanced low-power Schottky technology. The 20-pin pack- 
age provides improved printed circuit board density for use 
in memory address and clock driver applications. 

Three-state outputs are provided to drive bus lines directly. 
The Am25LS241 and Am25LS244 are specified at 48mA and 
24mA output sink current, while the Am54LS/74LS241 and 
Am54LS/74LS244 are guaranteed at 12mA over the military 
range and 24mA over the commercial range. Four buffers are 
enabled from one common line and the other four from a 
second enable line. 

The 'LS241 has enable inputs of opposite polarity to allow 
use as a transceiver without overlap. The 'LS244 enables are 
of similar polarity for use as a unidirectional buffer in which 
both halves are enabled simultaneously. 

Improved noise rejection and high fan-out are provided by 
input hysteresis and low current PNP inputs. 



LOGIC DIAGRAMS 



'LS241 



'LS244 



■1Y3 2A3- 



'LS241 



INPUTS 


OUTPUTS 


1G 


2G 


A 


Y 


H 


L 


X 


2 


L 


H 


H 


H 


L 


H 


L 


L 



Note: All devices have input hysteresis. 



LS244 



INPUTS 


OUTPUT 


G 


A 




H 


X 


z 


L 


H 


H 


L 


L 


L 



CONNECTION DIAGRAMS 
Top Views 





Note: Pin 1 is marked for orientation. 



LOGIC SYMBOLS 



11 13 15 17 



1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 
1G 'LS241 2G 

1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 



18 16 14 12 



11 13 15 17 



1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 
1G 'LS244 2G 

1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 



18 16 14 12 9 7 5 3 



GND = Pin 10 



4-17 



Am25LS/54LS/74LS241/244 



Am25LS241 • Am25LS244 
ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Specified: 

COM'L T A = 0°C to +70°C V cc = 5.0V ± 5% (MIN. = 4.75V MAX. = 5.25V) 

MIL T A = -55°C to + 125°C V cc = 5.0V ± 10% (MIN. = 4.50V MAX. = 5.50V) 

DC CHARACTERISTICS OVER OPERATING RANGE 



Typ. 

Parameters Description Test Conditions (Note 1) Min. (Note 2) Max. Units 



V 0H 


High-Level Output Voltage 


V CC = MIN., V| H = 2.0V 

l 0H = -3.0mA, V, L = V| L MAX. 


2.4 


3.4 




Volts 


V cc = MIN.. 
V| L = 0.5V 


MIL, l 0H = -12mA 


2.0 






COM'L, l 0H = -15mA 


2.0 






Vol 


Low-Level Output Voltage 


V CC = MIN. 


All l 0L = 12mA 




0.25 


0.4 


Volts 


All l 0L = 24mA 




0.35 


0.5 


COM'L, l 0L = 48mA 






55 


V| H 


High-Level Input Voltage 


Guaranteed input logical HIGH 
voltage for all inputs 


2.0 






Volts 


V| L 


Low-Level Input Voltage 


COM'L 








0.8 


Volts 


MIL 








0.7 


V,K 


Input Clamp Voltage 


V cc = MIN -. 'l = -18mA 






-1.5 


Volts 




Hysteresis (V T+ - V T _) 


V CC = MIN. 


0.2 


0.4 




Volts 


>OZH 


Off-State Output Current, 
High Level Voltage Applied 


V cc = MAX. 
V, H = 2.0V 
V IU = V IL MAX. 


V = 2.7V 






20 


fA 


■c-ZL 


Off-State Output Current, 
Low-Level Voltage Applied 


V = 0.4V 






-20 


'l 


Input Current at Maximum 
Input Voltage 


V cc = MAX., V, = 7.0V 






0.1 


mA 


■lH 


High-Level Input Current, Any Input 


V CC = MAX., V| H = 2.7V 






20 


mA 


k. 


Low-Level Input Current 


V cc = MAX., V, L = 0.4V 






-200 




■sc 


Short Circuit Output Current (Note 3) 


V CC = MAX. 


-40 




-225 


mA 


Ice 


Supply Current 


V CC = MAX. 
Outputs open 


All Outputs HIGH 




13 


23 


mA 


All Outputs LOW 




27 


46 


Outputs at Hi-Z 




32 


54 



□ 



Notes: 1 . For conditions shown as MIN. or MAX., use the appropriate value specified under recommended operating conditions. 

2. All typical values are Vcc = 5.0V, Ta = 25°C. 

3. Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 



MAXIMUM RATINGS above which the useful life may be impaired 



Storage Temperature 


-65°Cto +150°C 


Temperature (Ambient) Under Bias 


-55°C to +125°C 


Supply Voltage to Ground Potential 


-0.5V to +7.0V 


DC Voltage Applied to Outputs for HIGH Output State 


-0.5V to +V CC max. 


DC Input Voltage 


-0.5V to +7.0V 


DC Output Current 


150mA 


DC Input Current 


-30mA to +5.0mA 



4-18 



Am25LS/54LS/74LS241 /244 

Am54LS/74LS241 • Am54LS/74LS244 
ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Specified: 

COM'L T A = 0°C to +70°C V cc = 5.0V ± 5% (MIN. = 4.75V MAX. = 5.25V) 

MIL T A = -55X to +125X V cc = 5.0V ± 10% (MIN. = 4.50V MAX. = 5.50V) 

DC CHARACTERISTICS OVER OPERATING RANGE 



Parameters 



Description 



Test Conditions (Note 1) 



Min. 



Typ. 

(Note 2) 



Max. Units 



V H 




High-Level Output Voltage 


V cc = MIN., V| H = 2.0V 

l 0H = -3.0mA, V, L = V, L MAX. 


2.4 


3.4 




Volts 


V cc = MIN., 
V, L = 0.5V 


MIL, l 0H = -12mA 


2.0 






COM'L, l 0H = -15mA 


2.0 






Vol 




Low-Level Output Voltage 


V CC = MIN. 


All, l 0L = 12mA 




0.25 


0.4 


Volts 


COM'L, l 0L = 24mA 




0.35 


0.5 


V IH 




High-Level Input Voltage 


Guaranteed input logical HIGH 
voltage for all inputs 


o n 
z.u 






Volts 


Vii 

IL 




Low-Level Input Voltage 


COM'L 








0.8 


Volts 


MIL 








0.7 


V,K 




Input Clamp Voltage 


V CC = MIN., 1, = -18mA 






-1.5 


Volts 






Hysteresis (Vx+ - V T _) 


V CC = MIN. 


0.2 


0.4 




Volts 


'OZH 




Off-State Output Current, 
High Level Voltage Applied 


V CC = MAX. 
V| H = 2.0V 
V, L = V, L MAX. 


V = 2.7V 






20 




■OZL 




Off-State Output Current, 
Low-Level Voltage Applied 


V = 0.4V 






-20 


l| 




Input Current at Maximum 
Input Voltage 


V C c = MAX., V, = 7.0V 






0.1 


mA 


l|H 




High-Level Input Current, Any Input 


V cc = MAX., V| H = 2.7V 






20 




III 




Low-Level Input Current 


V cc = MAX., V, u = 0.4V 






-200 


MA 


■sc 




Short Circuit Output Current (Note 3) 


V cc = MAX. 


-40 




-225 


mA 


■cc 




Supply Current 


V cc = MAX. 
Outputs open 


All Outputs HIGH 




13 


23 


mA 


All Outputs LOW 




27 


46 


Outputs at Hi-Z 




32 


54 



Notes: 1 . For conditions shown as MIN. or MAX., use the appropriate value specified under recommended operating conditions. 

2 All typical values are Vcc = 5.0V, = 25°C. 

3 Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 



Metallization and Pad Layouts 



'LS241 



'LS244 




DIE Size 0.060" X 0.103" DIE SIZE 0.060" X 0.103" 



4-19 



Am25LS/54LS/74LS241 /244 



SWITCHING CHARACTERISTICS 

(T A = +25°C, V cc = 5.0V) 



Parameters 


Description 


Am25LS241 
Am25LS244 

Min. Typ. Max. 


Am54LS/74LS241 
Am54LS74LS244 

Min. Typ. Max. 


Test Conditions 
Units (Notes 1-5) 


*PLH 


Propagation Delay Time, 
Low-to-High-Level Output 




10 


15 




12 


18 


ns 


C L = 45pF 
R L = 6670 


*PHL 


Propagation Delay Time, 
High-to-Low-Level Output 




12 


18 




12 


18 


ns 


*PZL 


Output Enable Time to Low Level 




20 


30 




20 


30 


ns 


tpZH 


Output Enable Time to High Level 




15 


23 




15 


23 


ns 


*PLZ 


Output Disable Time from Low Level 




15 


25 




15 


25 


ns 


C L = 5.0pF 
R L = 66711 


*PHZ 


Output Disable Time from High Level 




10 


18 




10 


18 


ns 



Am25LS < 
SWITCHir 
OVER OP 

Parameters 


3NLY 

JG CHARACTERISTICS 
ERATING RANGE* 

Description 


Am25LS COM'L 


Am25LS MIL 


Units Test Conditions 


T A = OX to +70°C 
V cc = 5.0V ±5% 
Min. Max. 


T A = -55°Cto + 125X 
V cc = 5.0V ±10% 
Min. Max. 


*PLH 


Propagation Delay Time, 
Low-to-High-Level Output 




21 








C L = 45pF 
R L = 667n 


*PHL 


Propagation Delay Time, 
High-to-Low-Level Output 




25 




28 


ns 


*PZL 


Output Enable Time to Low Level 




41 




47 


ns 


*PZH 


Output Enable Time to High Level 




31 




47 


ns 


*PLZ 


Output Disable Time from Low Level 




34 




36 


ns 


C L = 5.0pF 
R L = 667fl 


tpHZ 


Output Disable Time from High Level 




25' 




28 


ns 


*AC performance over the operating temperature range is guaranteed by testing defined in Group A, Subgroup 9. 



LOAD CIRCUIT FOR VOLTAGE WAVEFORMS 

THREE-STATE OUTPUTS ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS 




Notes: 1. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 

2. Waveform 2 Is for an output with internal conditions such that the output is high except when disabled by the output control. 

3. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. 

4. Pulse generator characteristics: PRR s 1.0MHz, Zqut 50 ^. l r s 15ns, tf « 6ns. 

5. When measuring t PLH and t PHL , switches S 1 and S 2 are closed. 



Am25LS242 • Am54LS/74LS242 
Am25LS243 • Am54LS/74LS243 

Quad Bus Transceivers with Three-State Outputs 



Disni 

• Thn 

• Hyi 



/E CHARACTERISTICS 



state outputs drive bus lines directly 
eresis at inputs improve noise margin 
PNP inputs reduce D.C. loading on bus lines 
Data to output propagation delay times - 18ns MAX. 
Enable to output - 30ns MAX. 

Am25LS242 and Am25LS243 are specified at 48mA output 
current 

100% product assurance testing to MIL-STD-883 
requirements 



FUNCTIONAL DESCRIPTION 

The 'LS242 and 'LS243 are quad bus transceivers designed 
for asynchronous two-way communications between data 
buses. 

The 'LS242 and 'LS243 have the two 4-line data paths con- 
nected input-to-output on both sides to form an asynchron- 
ous transceiver/buffer with complementing enable inputs. 
The 'LS242 is inverting, while the 'LS243 presents non- 
inverting data at the outputs. 

Three-state outputs are provided to drive bus lines directly. 
The Am25LS242 and Am25LS243 are specified at 48mA and 
24mA output sink current, while the Am54/74LS242 and 243 
are guaranteed at 12mA over the military range and 24mA 
over the commercial range. 

Improved noise rejection and high fan-out are provided by 
input hysteresis and low current PNP inputs. 



LOGIC DIAGRAMS 
Am54LS/74LS242 Am54LS/74LS243 





devices have input hysteresis. 



CONNECTION DIAGRAMS 
Top Views 




LIC-347 



Note: Pin 1 is marked for orientation 



LOGIC SYMBOLS 



4 5 6 



3 4 5 6 



1A 2A 3A 4A 

-O] GAB 'LS242 GBA 

IB 2B 3B 4B 



TTTT 



13 1 



1A 2A 3A 4A 
GAB LS243 GBA 

18 2B 3B 4B 



11 10 9 



Vcc = Pin 14 
GND = Pin 7 



Am25LS/54LS/74LS242/243 



Am25LS242 • Am25LS243 
ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply unless Otherwise Specified: 

COM'L T A = 0°C to +70°C V cc = 5.0V ± 5% (MIN. = 4.75V MAX. 

MIL T A = -55°C to + 125°C V cc = 5.0V ± 10% (MIN. = 4.50V MAX. 

DC CHARACTERISTICS OVER OPERATING RANGE 



Parameters 



5.25V) 
5.50V) 



Description 



Test Conditions (Note 1) 



Min. 



Typ. 

(Note 2) 



Max. Units 



V H 


Hi 


gh-Level Output Voltage 


V cc = MIN., V| H = 2.0V 

l 0H = -3.0mA, V| L = V| L MAX. 


2,4 


3.4 




Volts 


V cc = MIN., 
V, L = 0.5V 


MIL, l 0H = -12mA 


2.0 






COM'L, l 0H = -15mA 


2.0 






Vol 


Low-Level Output Voltage 


V CC = MIN. 


All l 0L = 12mA 




0.25 


0.4 


Volts 


All l 0L = 24mA 




0.35 


0.5 


COM'L, l OL = 48mA 






n cc 


Vim 


Hi 


gh-Level Input Voltage 


Guaranteed input logical HIGH 
voltage for all inputs 


2.0 






Volts 


V,L 


Low-Level Input Voltage 


COM'L 








0.8 


Volts 


MIL 








0.7 


V,K 


Input Clamp Voltage 


V cc = MIN., I, = -18mA 






-1.5 


Volts 




Hysteresis (V T+ - Vj_) 


V CC = MIN. 


0.2 


0.4 




Volts 


'OZH 


Off-State Output Current, 
High Level Voltage Applied 


V cc = MAX. 
V m = 2.0V 
V, L 4 V, L MAX. 


V = 2.7V 






40 


fiA 


■OZL 


Off-State Output Current, 
Low-Level Voltage Applied 


V = 0.4V 






-200 


'l 


Input Current at Maximum 
Input Voltage 


V cc = MAX. 


V, = 7.0V, GAB or GBA 






0.1 


mA 


V, = 5.5V, A or B 






0.1 


mA 


■|H 


High-Level Input Current, Any Input 


V CC = MAX., V, H = 2.7V 






20 


MA 


ht 


Low-Level Input Current 


V cc = MAX., V, L = 0.4V 






-200 


ma 


•sc 


Short Circuit Output Current (Note 3) 


V cc = MAX. 


-40 




-225 


mA 


ice 




V CC = MAX. 
Outputs open 
(Note 4) 


All Outputs 
HIGH 


'LS242, 'LS243 




22 


38 


mA 


Si 


pply Current 


All Outputs 
LOW 


'LS242, 'LS243 




29 


50 


Outputs at 


'LS242 




29 


50 


Hi-Z 


'LS243 




32 


54 



Notes: 1 . For conditions shown as MIN. or MAX., use the appropriate value specified under recommended operating conditions. 

2. All typical values are V cc = 5.0V, T A = 25°C. 

3. Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 

4. For 'LS242 and 'LS243 \qq is measured with transceivers enabled in one direction only, or with all transceivers disabled. 



MAXIMUM RATINGS above which the useful life may be impaired 



Storage Temperature 


-65°C to +150°C 


Temperature (Ambient) Under Bias 


-55°Cto +125°C 


Supply Voltage to Ground Potential 


-0.5V to +7.0V 


DC Voltage Applied to Outputs for HIGH Output State 


-0.5V to +Vcq max. 


DC Input Voltage 


-0.5V to +7.0V 


DC Output Current 


150mA 


DC Input Current 


-30mA to +5.0mA 



Am25LS/54LS/74LS242/243 



Am54LS/74LS242 • Am54LS/74LS243 
ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply unless Otherwise Specified: 

COM'L T A = 0°C to +70"C V cc = 5.0V ± 5% (MIN. = 4.75V MAX. = 5.25V) 

MIL T A = -55T to +125°C V cc = 5.0V ± 10% (MIN. = 4.50V MAX. = 5.50V) 

DC CHARACTERISTICS OVER OPERATING RANGE 

Test Conditions (Note 1) 




Min. 



Typ. 

(Note 2) 



Max. Units 



V H 




High-Level Output Voltage 


V cc = MIN., V| H = 2.0V 

l 0H = -3.0mA, V| L = V| U MAX. 


2.4 


3.4 




Volts 


V cc = MIN., 
V| U = 0.5V 


MIL, Iqh = -12mA 


2.0 






COM'L, l 0H = -15mA 


2.0 








Vol 




Low-Level Output Voltage 


V CC = MIN. 


All, l 0L = 12mA 




0.25 


0.4 


Volts 


COM'L, l 0L = 24mA 




0.35 


0.5 


v IH 


High-Level Input Voltage 


Guaranteed input logical HIGH 
voltage for all inputs 


2.0 






Volts 


W 


COM'L 








0.8 


Volts 


MIL 




V,K 


Input Clamp Voltage 


V cc = MIN-. I| = -18mA 






-1.5 


Volts 




Hysteresis (V T+ - Vf_) 


V CC = MIN. 


0.2 


0.4 




Volts 


'OZH 




Off-State Output Current, 
High Level Voltage Applied 


V cc = MAX. 
V| H - 2.0V 
V,L = V IL MAX. 


V = 2.7V 






40 


*A 


"OZL 




Off-State Output Current, 
Low-Level Voltage Applied 


V = 0.4V 






-200 






Input Current at Maximum 
Input Voltage 


V CC = MAX. 


V| = 7.0V, GAB or GBA 






0.1 


mA 


V, = 5.5V, A or B 






0.1 


mA 


•|H 




High-Level Input Current, Any Input 


V cc MAX., V| H = 2.7V 






20 


MA 


■|L 




Low-Level Input Current 


V cc = MAX., V, L = 0.4V 






-200 


^A 


"sc 




Short Circuit Output Current (Note 3) 


V cc = MAX. 


-40 




-225 


mA 


•cc 




Supply Current 


V cc = MAX. 
Outputs open 
(Note 4) 


All Outputs 
HIGH 


'LS242, 'LS243 




22 


38 


mA 


All Outputs 
LOW 


'LS242, 'LS243 




29 


50 


Outputs at 
Hi-Z 


'LS242 
'LS243 




29 
32 


50 
54 



Notes: 1 . For conditions shown as MIN' or MAX ., use the appropriate value specified under recommended operating conditions. 

2. All typical values are Vqq = 5.0V, = 25°C. 

3. Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 

4. For 'LS242 and 'LS243 Iqc is measured with transceivers enabled in one direction only, or with all transceivers disabled. 




Am25LS/54LS/74LS242/243 



Am25LS242 • Am54LS/74LS242 



SWITCHING CHARACTERISTICS 

(T A - +25X, V cc - 5.0V) 
Parameters Description 


Am25LS242 


Am54LS/74LS242 




Test Conditions 

(Notes 1-5) 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Units 


*PLH 




Propagation Delay Time, 
Low-to-High-Level Output 




8.0 


12 




9.0 


14 


ns 




*PHL 




Propagation Delay Time, 
High-to-Low-Level Output 




12 


16 




12 


18 


ns 


Cl = 45pF 
R L = 6670 


*PZL 




Output Enable Time to Low Level 




20 


30 




20 


30 


ns 




*PZH 




Output Enable Time to High Level 




15 


23 




15 


23 


ns 




tpLZ 




Output Disable Time from Low Level 




15 


25 




15 


25 


ns 


C L = 5.0pF 


*PHZ 




Output Disable Time from High Level 




10 


18 




10 


18 


ns 


R[_ = 6670 



Am25LS242 ONLY 
SWITCHING CHARACTERISTICS 
OVER OPERATION RANGE* 

Parameters Description 


Am25LS COM'L 


Am25LS MIL 


Units Test Conditions 


T A = 0°C to +70X 
V cc = 5.0V ±5% 
Min. Max. 


T A = -55°Cto +125°C 
V cc = S.OV ±10% 
Min. Max. 


tpLH 


Propagation Delay Time, 
Low-to-High-Level Output 




16 




19 


ns 


C L = 45pF 
R L = 667JI 


tpHL 


Propagation Delay Time, 
High-to-Low-Level Output 




22 




25 


ns 


l PZL 


Output Enable Time to Low Level 




37 




42 


ns 


*PZH 


Output Enable Time to High Level 




29 




33 


ns 


tpLZ 


Output Disable Time from Low Level 




33 




38 


ns 


C L = 5.0pF 
R L = 667ft 


«PHZ 


Output Disable Time from High Level 




25 




28 


ns 



Am25LS243 • Am54LS/74LS243 



SWITCHI 

(T A = +25° 
Parameters 


MG CHARACTERISTICS 

Z, V cc = 5.0V) 

Description 


Am25LS243 


Am54LS/74LS243 


Test Conditions 
Units (Notes 1 -5) 


Min. Typ. Max. 


Min. Typ. Max. 


*PLH 


Propagation Delay Time, 
Low-to-High-Level Output 




10 


15 




12 


18 


ns 


C L = 45pF 
R L = 667J1 


«PHL 


Propagation Delay Time, 
High-to-Low-Level Output 




12 


18 




12 


18 


ns 


*PZL 


Output Enable Time to Low Level 




20 


30 




20 


30 


ns 


*PZH 


Output Enable Time to High Level 




15 


23 




15 


23 


ns 


*PLZ 


Output Disable Time from Low Level 




15 


25 




15 


25 


ns 


C L = 5.0pF 
R L = 667(1 


*PHZ 


Output Disable Time from High Level 




10 


18 




10 


18 


ns 



Am25LS243 ONLY 
SWITCHING CHARACTERISTICS 
OVER OPERATION RANGE* 

Parameters Description 


Am25LS COM'L 


Am2SLS MIL 


Units Test Conditions 


T A = OX to +70X 

V C c = 5 0V ±5% 
Min. Max. 


T A = -55Xto +125X 
V cc = 5.0V ±10% 
Min. Max. 


*PLH 


Propagation Delay Time, 
Low-to-High-Level Output 




21 




24 


ns 


C L = 45pF 
R L = 667JI 


tpHL 


Propagation Delay Time, 
High-to-Low-Level Output 




25 




28 


ns 


*PZL 


Output Enable Time to Low Level 




41 




47 


ns 


*PZH 


Output Enable Time to High Level 




33 




49 


ns 


*P1_Z 


Output Disable Time from Low Level 




36 




38 


ns 


C L = 5.0pF 
R[_ = 667n 


tpHZ 


Output Disable Time from High Level 




25 




28 


ns 



4-24 



/74LS242/243 



SWITCHING CHARACTERISTICS TEST CONDITIONS 



LOAD CIRCUIT FOR VOLTAGE WAVEFORMS 

THREE-STATE OUTPUTS ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS 




LIC-351 



Notes: 1 . Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 

2. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 

3. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. 

4. Pulse generator characteristics: PRR < 1MHz, Zquj w 50J2, t r < 1 5ns, tf < 6ns. 

5. When measuring tpLH ar| d T PHL' switches S-| and S2 are closed. 



FUNCTION TABLES 



Am54LS/74LS242 



Am54LS/74LS243 



CONTROL 


DATA 


INPUTS 


OUTPUTS 


GAB GBA 


A B 


H H 


0~ I 


L H 


» * 


H L 


ISOLATED 


L L 


I 


I = Input 


H = HIGH 


= Output 


L - LOW 


= Inverting Output 





CONTROL 
INPUTS 


DATA 
OUTPUTS 


GAB GBA 


A B 


H H 

L H 
H L 
L L 


I 
* # 

ISOLATED 
I 



"Possible destructive oscillation may occur if the transceivers are enable in both directions at once. 



4-25 



Am26LS29 

Quad Three-State Single Ended RS-423 Line Driver 



DISTINCTIVE CHARACTERISTICS 

• Four single ended line drivers in one package for maximum 
package density 

• Output short-circuit protection 

• Individual rise time control for each output 

• 50fl transmission line drive capability 

• High capacitive load drive capability 

• Low l cc and l EE power consumption (26mW/driver typ.) 

• Meets all requirements of RS-423 

• Three-state outputs for bus oriented systems 

• Outputs do not clamp line with power off or in hi-impedance 
state over entire transmission line voltage range of RS-423 

• Low current PNP inputs compatible with TTL, MOS and CMOS 

• Available in military and commercial temperature range 

• Advanced low power Schottky processing 



100% 
requirements 



irance screening to MIL-STD-883 



FUNCTIONAL DESCRIPTION 

The Am26LS29 is a quad single ended line driver, designed for 
digital data transmission. The Am26LS29 meets all the require- 
ments of El A Standard RS-423 and Federal STD 1 030. It features 
four buffered outputs with high source and sink current, and 
output short circuit protection. 

A slew rate control pin allows the use of an external capacitor to 
control slew rate for suppression of near end cross talk to receiv- 
ers in the cable. 

The Am26LS29 has three-state outputs for bus oriented systems. 
The outputs in the hi-impedance state will not clamp the line over 
the transmission line voltage of RS-423. A typical full duplex 
system would use the Am26LS29 line driver and up to twelve 
Am26LS32 line receivers or an Am26LS32 line receiver and up to 
thirty-two Am26LS29 line drivers with only one enabled at a time 
and all others in the three-state mode. 

The Am26LS29 is constructed using advanced low-power 
Schottky processing. 



LOGIC DIAGRAM 




SR CONTROL A 



SR CONTROL B 



SR CONTROL C 



SR CONTROL D 



ENABLE 



ORDERING INFORMATION 



Package Temperature 
Type Range 



Order 
Number 



Hermetic DIP 
Hermetic Flat Pak 
Dice 
Hermetic DIP 
Molded DIP 
Dice 



-55°C to +125°C 
-55°C to +125°C 
-55°C to +125°C 
0°C to +70°C 
0°C to +70°C 
0°C to +70"C 



AM26LS29DM 
AM26LS29FM 
AM26LS29XM 
AM26LS29DC 
AM26LS29PC 



CONNECTION DIAGRAM 
Top View 



VccC 

INPUT A Q 
INPUT B 



ENABLE 

GND Q 
INPUT C □ 
INPUT D □ 

veeC 



□ SLEW RAT! 
CONTROL 

^ OUTPUT A 
^ OUTPUT B 
□ 



SLEW RATE 
CONTROL B 



CONTROL C 
^ OUTPUT C 

10 OUTPUT D 



Note: Pin 1 is marked for orientation. 



4-26 



Am26LS29 

ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired) 



Qtnrano Tom nora+i iro 
OlUldyc 1 cm JJcl d lul c 


-65°Cto+150°C 


ouppiy vuiTdgt; 




v+ 


7.0V 


V- 


-7.0V 


Power Dissipation 


600mW 


Input Voltage 


-0.5 to +15.0V 


Output Voltage (Power Off) 


±15V 



300 C 



ELECT 

The folh 

Am26L! 
Am26L: 

DC CH 




CHARACTERISTICS over the operating temperature range 
ns apply unless otherwise specified: 

T A = -55°C to+125°C V CC = 5.0V +10, -5%, V EE = -5.0V -10, +5% 
T A = 0°C to +70°C V CC - 5.0V ±5%, V EE = -5.0V ±5% 

STICS over the operating temperature range (Notes 1 and 2) 



Paramete 


rs 


Description 


Test Conditions 


Min. 


Typ. 

(Note 1 ) 


Max. 


Units 


v 




Output Voltage 


R|_ ■ ~ 


V| N » 2.4V 


4.0 


4.4 


6.0 


Volts 


vo 




V| N = 0.4V 


-4.0 


-4.4 


-6.0 


Volts 


Vt 




Output Voltage 


R L =45012 


V| N = 2.4V 


3.6 


4.1 




Volts 


v t 




V| N = 0.4V 


-3.6 


-4.1 




Volts 


|v t I- 


IvtI 


Output Unbalance 


Wccl=IV EE |, R L = 450n 




0.02 


0.4 


Volts 


ix+ 




Output Leakage Power Off 


V CC = V EE = 0V 


V ■ 10V 




2.0 


100 


uA 


ix- 




V " -10V 




-2.0 


-100 


MA 


is+ 




Output Short Circuit Current 


V - OV 


V| N = 2.4V 




-70 


-150 


mA 


is- 




V| N = 0.4V 




60 


150 


mA 


'Slew 




Slew Control Current 


V S LEW = V EE + 0.9V 




±110 




„A 


'cc 




Positive Supply Current 


V| N = 0.4V, R L = ~ 




18 


30 


mA 


' E E 




Negative Supply Current 


V| N = 0.4V, R[_ = °° 




-10 


-22 


mA 


io 




Off State (High Impedance! 


Vec = MAX. 


V = 10V 




2.0 


100 


MA 






Output Current 


V " -10 V 




-2.0 


-100 


eA 


V| H 




High Level Input Voltage 




2.0 






Volts 


VlL 




Low Level Input Voltage 








0.8 


Volts 


■IH 




High Level Input Current 


V| N = 2.4V 




1.0 


40 


mA 




V| N < 15V 




10 


100 


uA 


IlL 




Low Level Input Current 


V| N = 0.4V 




-30 


-200 


mA 


V| 




Input Clamp Voltage 


l|M = -12mA 






-1.5 


Volts 



AC CHARACTERISTICS 

V CC = 5.0V, V EE = -5.0V, T A = 25°C 



Typ. 



Parameters 


Description 






Test Conditions 




Min. 


(Note 1) 


Max. 


Units 


«r 


Rise Time 


R L = 


450n, C u = 


500pF, Rg. 1 




C C = 


50pF 




3.0 




lis 




C C = 


OpF 




120 


300 


ns 


tf 


Fall Time 


R L = 


450fl, C L = 


500pF, Rg. 1 




C C = 


50pF 




3.0 




/J.S 




C C = 


OpF 




120 


300 


ns 


Src 


Slew Rate Coefficient 


R L = 


45011, C L = 


500pF, Fig. 1 










.06 




MS/pF 


tLZ 




R L = 


450O, C L = 


500pF, C c = 


OpF, Fig. 2 






180 


300 




tHZ 


Output Enable to Output 






250 


350 


ns 


•2L 




450fl, C L = 


500pF, C c = 


OpF, Fig. 2 






250 


350 


<ZH 










180 


300 





Notes: 1. Typical limits are at V cc = 5.0V, V EE = -5.0V, 25°C ambient and maximum loading. 
2. Symbols and definitions correspond to EIA RS-423 where applicable. 



4-27 



Am26LS29 



SWITCHING TIME WAVEFORMS AND AC TEST CIRCUITS 



INPUT t r <10ro 



0-9VSS 
0.1 Vss 



dm \ 


^ t,<10ru ^ 


i 


- 20|i> — 







«cc 

".PL. " O- 



vss 



09V SS 

O.Wjs 



r 



v E E- 



Figure 1. Rise Time Control. 



«=0 



1 



(INPUT A HIGH) 



(INPUT A LOW) 



IPHZ 
0.9 V SS /R L 



■ tpLZ OUTPUT 



r 



Vss/"l 



<pzl|- — 0.3 v s5 y( 

0.5 V SS /R L 




i 



Figure 2. Three State Delays. 



Am26LS29 EQUIVALENT CIRCUIT 




15 A OUT 
(Ifl) B OUT 
C OUT 
(10( D OUT 



2 A INPUT 
A (3) a INPUT 

(6) C INPUT 

(7) D INPUT 



16 A SLEW 
A (131 B SLEW 
(12) C SLEW 
(9) D SLEW 



Am26LS29 

. 



TYPICAL APPLICATION 




COMMON GROUND 
RETURN 




* 

BLI-012 



Slew Rate (Rise or Fall Time) 
Versus External Capacitor 




10 100 1k 10k 



CAPACITANCE - pF BLI-010 



Metallization and Pad Layout 



SLEW RATE 

INPUT A «CC CONTROL A 
2 1 16 




7 8 9 OUTPUT D 

INPUT D V EE SLEW RATE 



CONTROL D 

DIE SIZE 0.070" X 0.094" 



4-29 



Am26LS30 

Dual Differential RS-422 Party Line/Quad Single Ended RS-423 Line Driver 



DISTINCTIVE CHARACTERISTICS 

• Dual RS-422 line driver or quad RS-423 line driver 

• Driver outputs do not clamp line with power off or in 
hi-impedance state 

• Individually three-state drivers when used in differential mode 

• Low l cc and l EE power consumption 

RS-422 differential mode 35mW/driver typ. 
RS-423 single-ended mode 26mW/driver typ. 

• Individual slew rate control for each output 

• 50fl transmission line drive capability (RS-422 into virtual 
ground) 

• Low current PNP inputs compatible with TTL, MOS and CMOS 

• High capacitive load drive capability 

• Exact replacement for DS16/3691 

• Advanced low power Schottky processing 

• 100% reliability assurance screening to MIL-STD-883 
requirements 



LOC 



Logic for Am26LS30 with 
Mode Control HIGH (RS-423) 




SR CONTROL A 



SR CONTROL B 



SR CONTROL C 



SR CONTROL D 



FUNCTIONAL DESCRIPTION 

The Am26LS30 is a line driver designed for digital data transmis- 
sion. A mode control input provides a choice of operation either as 
two differential line drivers which meet all of the requirements of 
EIA Standard RS-422 or four independent single-ended RS-423 
line drivers. 

In the differential mode the outputs have individual three-state 
controls. In the hi-impedance state these outputs will not clamp 
the line over a common mode transmission line voltage of ± 1 0V. 
A typical full duplex system would be the Am26LS30 differential 
line driver and up to twelve Am26LS32 line receivers or an 
Am26LS32 line receiver and up to thirty-two Am26LS30 differen- 
tial drivers. 

A slew rate control pin allows the use of an external capacitor to 
control slew rate for suppression of near end cross talk to receiv- 
ers in the cable. 

The Am26LS30 is constructed using Advanced Low Power 
Schottky processing. 



RAMS 



Logic for Am26LS30 with 
Mode Control LOW (RS-422) 




ORDERING INFORMATION 






CONNECTION DIAGRAM 


- Top View 




Package 
Type 


Temperature 
Range 


Order 
Number 




INPUT A Q 
INPUT/ENABLE B 

MODE £~ 


i« 


16 
15 


— 1 SLEW RATE 
—J CONTROL A 

12 OUTPUT A 
^ OUTPUT B 

— | SLEW RATE 
— 1 CONTROL B 




Hermetic DIP 
Hermetic Flat Pak 
Dice 


-55°C to +125°C 
-55°C to +125°C 
-55°C to +125°C 


AM26LS30DM 
AM26LS30FM 
AM26LS30XM 




3 
4 

A 


14 

13 

n26LS30 




Hermetic DIP 


0°C to +70°C 


AM26LS30DC 




GND 


5 


12 


— 1 SLEW RATE 
—1 CONTROL C 




Molded DIP 


0°C to + 70°C 


AM26LS30PC 




INPUT/ENABLE C 


6 


11 


OUTPUT C 




Dice 


0°C to +70°C 


AM26LS30XC 


Note 


INPUT D 




10 


OUTPUT D 










Pin 1 is marked v EE p 
fnr nrifintatinn 


8 


9 


— i SLEW RATE 
— 1 CONTROL D 


BLI-005 



















4-30 



Am26LS30 

ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 




-65° C to +150°C 


Supply Voltage 








7.0V 


-T 




-7.0V 


— 

Power Dissipation 




600mW 


Input Voltage 




-0.5 to +15.0V 


Output Voltage (Power Off) 




±15V 


Lead Soldering Temperature (10 seconds) 




300° C 



ELECTRICAL CHARACTERISTICS over the operating temperature range 
The Following Conditions Apply Unless Otherwise Specified: 
Am26LS30XM (MIL) T A - -55°C to +125°C VfjC = 5.0V ±10%, V EE = GND 

Am26LS30XC (COM'L) T A = 0° C to +70° C VfJC = 5.0V ±5%, V EE = GND 

EIA RS-422 Connection, Mode Voltage = 0.8V 

DC CHARACTERISTICS over the operating temperature range 

Typ. 

Parameters Description Test Conditions (Note 3) Min. INotel) Max. Units 



v 
vo 




Differential Output Voltage, V Aj r 


R L = °° 


V| N = 2.0V 




3.6 


6.0 


Volts 


V| N - 0.8V 




-3.6 


-6.0 


Volts 


v T 
v T 




Differential Output Voltage, V Aj r 


r l = i oon 


V| N - 2.0V 


2.0 


2.4 




Volts 


V| N =0.8V 


-2.0 


-2.4 




Volts 


Vos. v OS 


Common Mode Offset Voltage 


R L = 100J2 




2.5 


3.0 


Volts 


[v-rl-IWl 


Difference in Differential Output Voltage 


R L = 100S2 




0.005 


0.4 


Volts 


Nosl-I 


vosl 


Difference in Common Mode Offset Voltage 


r l = ioon 




0.005 


0.4 


Volts 


v S s 




Ivt-VtI 


r l = ioon 


4.0 


4.8 




Volts 


V CMR 




Output Voltage Common Mode Range 


VENABLE = 24V 


110 






Volts 


IXA 




Output Leakage Current 


Vcc - ov 


V C MR = 10V 






100 


A"A 


>XB 




v C mr = -iov 






-100 


fiA 


'ox 




Off State (High Impedance) 
Output Current 



Vcc = MAX. 


V C MR < 10V 






100 


fA 


VCMR > -iov 






-100 


MA 


'SA. 'SB 




Output Short Circuit Current 


V|N - 2.4V 


V 0A = 6.0V 




80 


150 


mA 


VOB = 0V 




-80 


-150 


mA 


V|N =0.4V 


V 0A = OV 




-80 


-150 


mA 


V 0B = 6.0V 




80 


150 


mA 


ice 




Supply Current 






18 


30 


mA 


V|H 




High Level Input Voltage 




2.0 






Volts 


VlL 




Low Level Input Voltage 








0.8 


Volts 


iiH 




High Level Input Current 


V| N = 2.4V 




1.0 


40 


mA 


V| N < 15V 




10 


100 


ma 


• 1 1_ 




Low Level Input Current 


V| N = 0.4V 




-30 


-200 


HA 


V| 




Input Clamp Voltage 


l|M - -12mA 






-1.5 


Volts 


AC CHA 

EIA RS-42: 

Parameter 


RACTERISTICS 

1 Connection, V cc = 5.0V, V EE = GND, Mode = 0.4V, T A * 25°C 

Typ. 

s Description Test Conditions Min. (Note 1) Max. Units 




tr 




Differential Output Rise Time I Fig. 2, R L = 100J1, C L = 500pF 




120 


200 


ns 


tf 




Differential Output Fall Time 


Fig. 2, R[_ = 100H, C(_ = 500pF 




120 


200 


ns 


'PDH 




Output Propagation Delay 


Fig. 2, R L = 100n, C L = 500pF 




120 


200 


ns 


tpDL 


Output Propagation Delay 


Fig. 2, R L = 100n, C L = 500pF 




120 


200 


ns 


«LZ 


Output Enable to Output 


R L = 450n, C L = 500pF, C c = OpF, Fig. 3 




180 


300 


ns 


<HZ 




250 


350 


t ZL 


R L = 4500, C L = 500pF. C c = OpF, Fig. 3 




250 


350 






180 


300 



Notes: 1. Typical limits are at V cc = 5.0V, V EE = GND, 25°C ambient and maximum loading. 

2. Symbols and definitions correspond to EIA RS-422 where applicable. 

3. R L connected between each output and its complement. 



4-31 



Am26LS30 



ELECTRICAL CHARACTERISTICS over the operating temperature range 
The following conditions apply unless otherwise specified: 

Am26LS30XM (MIL) T A = -55°C to + 125°C V cc =5.0V ±10%, V EE = -5.0V ±10% 
Am26LS30XC (COM'L) T A = 0° C to +70° C V cc = 5.0V ±5%, V EE = -5.0V ±5% 

RS-423 Connection, Mode Voltage > 2.0V 

DC CHARACTERISTICS over the operating temperature range (Notes 1 and 2) 



Typ. 



Parameters 


Description 


Test Conditions 


Min. 


(Note 1) 


Max. 


Units 


vo 




Output Voltage 




V| N = 2.4V 


4.0 


4.4 


6.0 


Volts 


v 




|V C c|= |Vee| = 4.75V 


V| N = 0.4V 




4 4 


Q Q 


Volts 


Vt 
l 




Output Voltage 


R L = 45012, 


V||M = 2.4V 


3.6 


4.1 




Volts 


vT 




|Vcd= |VeeI = 4-75V 


V| N = 0.4V 


-3.6 


-4.1 




Volts 


|v T l-,v T 




Output Unbalance 


1 V CC | = |V EE |, R L = 450J2 




0.02 


0.4 


Volts 


'x+ 




Output Leakage Power Off 


vcc = v EE = ov 


V = 6.0V 




2.0 


100 


MA 


ix- 




V = -6.0V 




-2.0 


-100 


ma 


is+ 




Output Short Circuit Current 


V -0V 


V| N = 2.4V 




-80 


-150 


mA 


is- 




V| N = 0.4V 




80 


150 


mA 






Slew Control Current 


VSLEW - V E E + 0.9V 




±140 




mA 


ice 




Positive Supply Current 


V|N = 0.4V, R L = ~ 




18 


30 


mA 


'ee 




Negative Supply Current 


V| N =0.4V, R L = ~ 




-10 


-22 


mA 


Vim 




High Level Input Voltage 




2.0 






Volts 


V|L 


Low Level Input Voltage 








0.8 


Volts 


m 




High Level Input Current 


V| N 2.4 V 




1.0 


40 


MA 




V|N '> 15V 




10 


100 


mA 


IlL 




Low Level Input Current 


V| N = 0.4V 




-30 


-200 


ma 


V| 




Input Clamp Voltage 


l| N - -12mA 






-1.5 


Volts 



AC CHARACTERISTICS 

RS-423 Connection, V cc = 5.0V, V EE = -5.0V, Mode = 2.4V, T A = 25°C 



Parameters 



Description 



Test Conditions 



Min. 



Typ. 

(Note 1 ) 



Max. 



Units 



tr 




Rise Time 


Fig. 1, R L = 450n, C L = 500pF 


C c = 50pF 




3.0 




ps 


C c = 




120 


300 


ns 


tf 




Fall Time 


Fig. 1 , R|_ — 450fl, C L = 500pF 


C c = 50pF 




3.0 




pS 


C c = o 




120 


300 


ns 


Src 




Slew Rate Coefficient 


Fig. 1 , R[_ = 450H, C L m 500pF 




.06 




MS/pF 


'pdh 




Output Propagation Delay 


Fig. 1, R L = 450n, C L = 500pF, C c = 




180 


300 


ns 


'PDL 


Output Propagation Delay 


Fig. 1, R L = 450O, C L = 500pF, C c = 




180 


300 


ns 



Notes: 1. Typical limits are at V cc = 5.0V, V EE = -5.0V, 25°C ambient and maximum loading. 
2. Symbols and definitions correspond to EIA RS-423 where applicable. 




Am26LS30 



SWITCHING TIME WAVEFORMS AND AC TEST CIRCUITS 
FOR EIA RS-423 CONNECTION 



v cc - 



INPUT t. 



, < 10ns ^1.5V t f M 10ns ^ 
20;*s ~\— 20»js 

/ T V 



r 



v EE - 



J-006 




J 50 pF 



Figure 1. Rise Time Control for RS-423. 



SWITCHING TIME WAVEFORMS AND AC TEST CIRCUIT 
FOR RS-422 CONNECTION 



/ 



. 0V INPUT O- 



"-9VSS/RL -I" 



I 

VSS/RL 

_L_ 




O.lVss/RL 
— 





k 

> ioor 



•TEK CTR 

CURRENT TRANSF. 
OR EQUIVALENT 



BLI-006 



•Current probe is the easiest way to display a differential waveform. 
Figure 2. 



(INPUT A HIGH) 

(INPUT A LOW) 

LIC-329 



-V- INPUT B 



v cc 



*PHZ 
0.9 V SS /R L 



- tpLZ OUTPUT 



'pzhI- 



r 



0.1 V SS /R L 



Ipzl|- 0.5 V SS /R L 

0.5V SS /R L 




> 



A 

-O- 



\ 



OUTPUT 
•TEK CTR 



Figure 3. Three-State Delays. 



4-33 



Am26LS30 



Am26LS30 FUNCTION T, 



MODE 


1 MPI ITQ 
1 1 V r U 1 o 


Ol ITPI ITQ 
UU 1 rU 1 o 


AID) B(C) 


A(D) B(C) 








1 







1 


Z Z 







1 


1 







1 1 


Z Z 


1 










1 




1 


1 


1 




1 


1 


1 




1 1 


1 1 



Slew Rate (Rise or Fall Time) 
Versus External Capacitor 



i ioo 




100 Ik 10k 

CAPACITANCE - pF BLI-010 



Am26LS30 EQUIVALENT CIRCUIT 




Am26LS30 



TYPICAL APPLICATION 





DIE SIZE 0.070" X 0.094" 



Am26LS31 

Quad High Speed Differential Line Driver 



DISTINCTIVE CHARACTERISTICS 

• Output skew — 2.0ns typical 

• Input to output delay — 12ns 

• Operation from single +5V supply 

• 16-pin hermetic and molded DIP package 

• Outputs won't load line when Vcc = 

• Four line drivers in one package for maximum package 
density 

• Output short-circuit protection 

• Complementary outputs 

• Meets the requirements of EIA standard RS-422 

• High output drive capability for 1000 terminated trans- 
mission lines 

• Available in military and commercial temperature range 

• Advanced low-power Schottky processing 

• 100% reliability assurance screening to Ml L-STD-883 
requirements 



FUNCTIONAL DESCRIPTION 

The Am26LS31 is a quad differential line driver, designed for 
digital data transmission over balanced lines. The Am26LS31 
meets all the requirements of EIA standard RS-422 and federal 
standard 1020. Is is designed to provide unipolar differential 
drive to twisted-pair or parallel-wire transmission lines. 

The circuit provides an enable and disable function common 
to all four drivers. The Am26LS31 features 3-state outputs 
and logical OR-ed complementary enable inputs. The inputs 
are all LS compatible and are all one unit load. 
The Am26LS31 is constructed using advanced low-power 
Schottky processing. 



LOGIC DIAGRAM 




OUTPUT OUTPUT 



Package 
Type 



ORDERING INFORMATION 



Temperature 



Range 



Order 
Number 



Hermetic DIP 
Flat Pak 

Dice 
Hermetic DIP 
Molded DIP 

Dice 



-55 C to +125 C 
-55°C to +125°C 
-55°Cto+125°C 
0°C to +70°C 
0°Cto +70°C 
0°C,o+70°C 



AM26LS31 DM 
AM26LS31 FM 
AM26LS31XM 
AM26LS31 DC 
AM26LS31 PC 



CONNECTION DIAGRAM 
(Top View) 




Note: Pin 1 is marked for orientation. 



ftm?fii sat 



Storage Temperature Range 



5.5V 



-65°Cto +150°C 



ELECTRICAL CHARACTERISTICS over the operating temperature range 
The following conditions apply unless otherwise specified: 
T A = -55°C to +125°C 
Ta = 0°C to +70° C 



Am26LS31XM (MIL) 
Am26LS31XC ICOM'LI 



"CC 



' 5V ± 10% 

! 5V + 5% 



Parameters 


Description 


Test Conditions 


Min. 




Max. 


Units 


V H 


Output HIGH Voltage 


Vqc ■ Min., loH = -20mA 


2.5 


3.2 




Volts 


vol 


Output LOW Voltage 


Vcc = Min -. 'OL = 20mA 




0.32 


0.5 


Volts 


V| H 


input Mlun voltage 


Vcc = Min. 


2.0 






Volts 


V| L 




Input LOW Voltage 


VCC " Max - 






0.8 


Volts 


'IL 




Input LOW Current 


V C c " Max., V| N =»0.4V 




-0.20 


-0.36 


mA 


■iH 




Input HIGH Current 


V C c = Max., V|N 1 2.7V 




0.5 


20 


ma 


'l 




Input Reverse Current 


V C c = Max -. V |N " 7-OV 




0.001 


0.1 


mA 


io 




Off-State (High Impedance) 


Vcc = Max. 


V - 5.5V 




0.5 


20 


MA 






Output Current 


V " 0.5V 




0.5 


-20 


V| 




Input Clamp Voltage 


Vcc = Min., I|N => 18mA 




-0.8 


-1.5 


Volts 


[ sc 




Output Short Circuit Current 


VcC = Max. 


-30 


-60 


-150 


mA 


'cc 




Power Supply Current 


Vcc = Max., all outputs disabled 




60 


80 


mA 


«PLH 




Input to Output 


V C c " 5.0V, T A = 25°C. Load = Note 2 




12 


20 


ns 


*PHL 




Input to Output 


V c c = B.0V, T A = 25°C, Load = Note 2 




12 


20 


ns 


SKEW 




Output to Output 


V C c * 5.0V, T A = 25°C, Load = Note 2 




2.0 


6.0 


ns 


«LZ 




Enable to Output 


V C C * 5.0V, T A i 25°C, C L - 10pF 




23 


35 


ns 


«HZ 




Enable to Output 


V C c = 5.0V, T A - 25°C, C L - lOpF 




17 


30 


ns 


«ZL 




Enable to Output 


V C c * 5.0V, T A = 25°C, Load m Note 2 




35 


45 


ns 


tZH 




Enable to Output 


V CC = 5.0V, T A - 25°C, Load - Note 2 




30 


40 


ns 


Notes: 1. 


All typical values are V cc = 5.0V, T A = 25° C. 



2. C L - 30pF, V m - 1.3V to V OUT = 1.3V, V PULSE m 0V to +3.0V, See Below. 



AC LOAD TEST CIRCUIT 
FOR THREE-STATE OUTPUTS 



PROPAGATION DE 

(Notes 1 and 3) 



LAY 



TEST 
POINT 
O 



C L INCLUDES 
PROBE AND JIG ^ 
CAPACITANCE 



Si 

-or o — wv- 



1 



V 0H 



ENABLE AND DISABLE TIMES 

(Notes 2 and 3) 

Enable Disable 



OUTPUT 
NORMALLY 

LOW S 2 OPEN 



<ZL Kz- 
- -4.5 V 



OUTPUT 
NORMALLY „ , 
HIGH b l 1 



»|~ r 2H 'H 
-J ~0V 



3.0 V 
1.3 V 



£: — r v n 



,5 V 
OL 
OH 
1.5V 



Notes: 1. Diagram shown for Enable LOW. 

2. and S 2 of Load Circuit are closed except where shown. 

3. Pulse Generator for All Pulses: Rate < 1.0MHz; Z„ = 5012; t r < 15ns; tf < 6.0ns. 



4-37 



Am26LS31 



EQUIVALENT CIRCUIT (1/4 Am26LS31) 




BLI-023 



TYPICAL APPLICATION 




SHIELD OR COMMON GROUND RETURN 



LIC-357 



4-38 



Am26LS31 



Guaranteed Voh ar| d Vol 
(TA = -55°Cto+125°C) 



I 20 



















































v 0H ® v cc = 5.5V 










Voh ■ v C c - 5.ov 










MM! 












•'OH V CC - 4.5V 
















































V 0L ©1 


.5V < V cc «E 5.5V 


- 









LIC-3S6 



4.0 8.0 12 16 20 

Iql ° r -'oh l mfl l 



VquT Versus Vcc 



5.0 

4.0 

5 3.0 

O 

> 

8 2.0 
1.0 









































-55° 

2s;c 

+ 125 
















c — 










s 




c 










n 










/> 


"'PIN 4 « 0.8V. PIN 12 > 2.0V 
-R L - 10k£2 TO GROUND 
AREA INSIDE ENVELOPE 
IS LOW IMPEDANCE. (-5012) 
^AREA OUTSIDE ENVELOPE 
IS HIGH IMPEDANCE (>1/4Mn) 



1.0 2.0 3.0 

VQUT (VOLTS) 



Metallization and Pad Layout 

♦5.0V 



ENABLE 4 



15 INPUT D 




DIE SIZE 0.067" X 0.084' 



4-39 



Am26LS32 • Am26LS33 



Differential Line Receivers 



DISTINCTIVE CHARACTERISTICS 

• Input voltage range of 15V (differential or common mode) 
on Am26LS33; 7V (differential or common mode) on 
Am26LS32 

• ±0.2V sensitivity over the input voltage range on Am26LS32; 
±0.5V sensitivity on Am26LS33 

• The Am26LS32 meets all the requirements of RS-422 and 
RS423 

• 6k minimum input impedance 

• 30mV input hysteresis 

• Operation from single +5V supply 

• 16-pin hermetic and molded DIP package 

• Fail safe input-output relationship. Output always high 
when inputs are open. 

• Three-state drive, with choice of complementary output 
enables, for receiving directly onto a data bus. 

• Propagation delay 17ns typical 

• Available in military and commercial temperature range 

• Advanced low-power Schottky processing 

• 100% reliability assurance screening to Ml L-STD-883 
requirements 



FUNCTIONAL DESCRIPTION 

The Am26LS32 is a quad line receiver designed to meet the 
requirements of RS-422 and RS-423, and Federal Standards 
1020 and 1030 for balanced and unbalanced digital data 
transmission. 

The Am26LS32 features an input sensitivity of 200mV over 
the input voltage range' of ±7V. 

The Am26LS33 features an input sensitivity of 500mV over 
the input voltage range of ±15V. 

The Am26LS32 and Am26LS33 provide an enable and disable 
function common to all four receivers. Both parts feature 3- 
state outputs with 8mA sink capability and incorporate a fail 
safe input-output relationship which keeps the outputs high 
when the inputs are open. 

The Am26LS32 and Am26LS33 are constructed using Ad- 
vanced Low-Power Schottky processing. 



LOGIC DIAGRAM 




GND V cc OUTPUT D 



ORDERING INFORMATION 



Package 
Type 



Temperature 
Range 



Am26LS32 



Order 
Number 



Am26LS33 



Order 
Number 



Hermetic DIP 
Flat Pak 
Dice 
Hermetic DIP 
Molded DIP 
Dice 



-55 C to + 125 C 
-55°Cto+125°C 
-55°Cto+125°C 
0°C to +70° C 
0°C to +70° C 
0°Cto +70° C 



AM26LS32DM 
AM26LS32FM 
AM26LS32XM 
AM26LS32DC 
AM26LS32PC 
AM26LS32XC 



AM26LS33DM 
AM26LS33FM 
AM26LS33XM 
AM26LS33DC 
AM26LS33PC 
AM26LS33XC 



CONNECTION DIAGRAM 
Top View 



l-C 

OUTPUT A 
OUTPUT C Q 



IE 

GND £ 



"r^^t" | INPUTS 8 
' ^ OUTPUT B 



IMS 



^ ENABLE 
3 OUTPUT D 



Note: Pin 1 is marked for orientation. 



4-40 



Am26LS32 • Am26LS33 

ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired) 



Supply Voltage 



7.0V 



Common Mode Range 



±25V 



Differential Input Voltage 



±25V 



Enable Voltage 



7.0V 



Output Sink Current 



50 mA 



Storage Temperature Range 



-65 Cto +165°C 



ELECTRICAL CHARACTERISTICS Over the operating temperature range 
The following conditions apply unless otherwise specified: 

Am26LS32XM, Am26LS33XM (MIL) T A = -55° C to +1 25° C V CC =5.0V±10% 

Am26LS32XC, Am26LS33XC (COM'L) T A = 0°C to +70° C V cc - 5.0V ± 5% 



Parameters Description 


Test Conditions 




Min. 


Typ. 

(Note 1) 


Max. 


Units 


\/_. , 

V TH 


Differential Input Voltage 


v out - Vol or v oh 


Am26LS32, -7V < V CM < +7V 


0.2 


0.06 


0.2 


Volts 


Am26LS33, -15V < V C M < +15V 


0.5 


0.12 


0.5 


R IN 


Input Resistance 


-1 5V < Vcm «S +1 5V (One input AC ground) 


6.0k 


8.5k 




n 


'in 


Input Current (Under Test) 


V| N = +15V, Other Input -15V < V| N < +15V 






2.3 


mA 


Iim 

MINI 


Innut Pnrrent (l InHor Toctl 


V| N = -15V, Other Input -15V < V| N s; +15V 






-2.8 


mA 


V H 


Output HIGH Voltage 


V cc = Min., A V|N = +1 .0V 


COM'L 


2.7 


3.4 




Volts 


VENABLE =0.8V, l 0H = 


-440,uA 


MIL 


2.5 


3.4 






vol 


Output LOW Voltage 


Vcc = Min - AV IN °° -1.0V 


Iql = 4.0mA 






0.4 


Volts 


VENABLE =0.8V 




Iql = 8.0mA 






0.45 


Vn 
" 1 L 


Enable LOW Voltage 








0.8 


Volts 


ViH 


Enable HIGH Voltage 




2.0 






Volts 


V| 


Enable Clamp Voltage 


V CC = Win.. I|N = —18mA 






-1 .5 


Volts 


'0 


Off-State (High Impedancel 


V CC - Max. 


V - 2.4V 






20 


fiA 


Output Current 


V = 0.4V 






-20 


hL 


Enable LOW Current 


V|N = 0.4V 




-0.2 


-0.36 


mA 


1 IH 


Enable HIGH Current 


V| N = 2.7V 




0.5 


20 


MA 


M 


Enable Input High Current 


V| N - 5.5V 




1 


100 


m a 


•sc 


Output Short Circuit Current 


V = 0V, V CC = Max., AV| N = +1 .0V 


-15 


-50 


-85 


mA 


'cc 


Power Supply Current 


Vqc - Max., All V|N - GND, Outputs Disabled 




52 


70 


mA 


V HYST 


Input Hysteresis 


T A = 25°C, V CC = 5.0V, V CM = 0V 




30 




mV 


«PLH 


Input to Output 


T A " 25°C, Vcc = 5.0V, Cl = 15pF, see test cond. below 




17 


25 


ns 


«PHL 


Input to Output 


T A = 25°C, Vcc =5.0V,Cl " 1SpF, see test cond. below 




17 


25 


ns 


tLZ 


Enable to Output 


T A = 25°C, Vcc 1 5.0V, Cl " 5pF, see test cond. below 




20 


30 


ns 


«HZ 


Enable to Output 


T A = 25°C, Vcc = 5.0V, Cl = 5pF, see test cond. below 




15 


22 


ns 


«ZL 


Enable to Output 


T A = 25°C, Vcc = 5.0V, Cl - 15pF, see test cond. below 




15 


22 


ns 


«ZH 


Enable to Output 


Ta » 25°C, Vcc = 5.0V, Cl - 15pF, see test cond. below 




15 


22 




Note: 1. A 


1 typical values are V cc - 5.0 V, T A 


- 25° C. 















LOAD TEST CIRCUIT 
FOR THREE-STATE OUTPUTS 



PROPAGATION DELAY 

(Notes 1 and 3) 



ENABLE AND DISABLE TIMES 

(Notes 2 and 3) 



C L INCLUDES 
PROBE AND JIG Z± 
CAPACITANCE 




OPPOSITE 
PHASE 
INPUT 
TRANSITION 



1 -u 

f— — J-'PLH f— — l- l PHL 

I j +2.! 



OUTPUT 
NORMALLY 
LOW 



OUTPUT 
NORMALLY . 
HIGH ' 



PENl\ 

T 

en7T 



3.0V 
1.3V 



T 



1.3V 
~0V 



, li5V 

0.5 V 

LIC-363 



Notes: 

1 . Diagram shown for Enable LOW. 

2. S-] and S2 of Load Circuit are closed except 
where shown. 

3. Pulse Generator for All Pulses: Rate < 1 .0MHz; 
Z Q = 5012; t r < 15ns;tf < 6.0ns. 



4-41 



Am26LS32 • Am26LS33 



EQUIVALENT CIRCUIT (1/4 Am26LS32 OR Am26LS33) 



r 



"20 



L 



:«ia < R 13 



L 



R 2 , 



I 



"27 > 

— Mi 



— K Q 



~M— i 

Q 2 3 D 12 



^ 




Note: B3 and R4 value for Am26LS32 is 2 times Am26LS33 value. 



TYPICAL APPLICATION 






■ 

SHIELD OA COMMON GROUND RETURN 




4-42 



Am26LS32 • Am26LS33 





DATA OUTPUT 



Two Wire Balanced System. 



DATA 



V SS|| A m26LS29 ^ 



\-~ 2 




DATA OUTPUT 



_ GROUND RETURN COMMON 
TO SEVERAL SIGNAL Wl RES 



Single Wire With Common Ground Unbalanced System. 







LINE TERMINATION 

It is important in a digital communication system to have the 
minimum amount of noise generated by undesired reflections 
at the driver and receiver. There are numerous ways of match- 
ing to the line. The line can be matched at the driver, at the 
receiver or both, each method has advantages and disadvan- 
tages. Generally for any but the longest lines it is sufficient 
to match at one place, and only when there are discontinuities 
in the line, party line operation, or lack of a reasonable match 
at the opposite end of the line is the extra hardware of match- 
ing at both ends justified. The majority of transmission lines 
have fairly low characteristic impedances (in the range of 
50 to 200 ohms) and the currents involved for a reasonable 
voltage swing are quite large. It is more difficult to couple 
noise into this low impedance, but it is also more difficult to 
drive, and line drivers must have the ability to supply large 
currents. 

Various matching techniques that can be employed are shown 
in Figure 1 . These impedance charts are useful in showing what 
happens to wave fronts traveling down a line, when the line 
delay is longer than the wave front transition. The DC input 
characteristic of the receiver, including any external compo- 
nents, is plotted on the V-l graph together with the output 
characteristic of the driver, including any external components 
used at the driving end. There are always quiescent points - 
points where the driver and receiver characteristics cross. These 
points represent the DC voltage/current conditions, which must 
eventually be satisfied. To determine the effect of switching 
from one quiescent point to the other, a line with a slope 
equal to the characteristic impedance of the transmission line 
is plotted, starting at the initial quiescent point and ending at 
the applicable output impedance characteristic. The point of 
intersection gives the voltage and current at the output of the 
driver (and the input of the transmission line immediately after 
the driver switched states). From this point a line having an 
equal but opposite slope is drawn to the input characteristic 
and, at the intersection shows the voltage/current conditions 
of the wave front at the input of the receiver. This procedure 
is repeated to the output characteristic and so on at each 
intersection of the characteristic, the voltage/current relation- 
ship for a particular reflection is given. The resulting time/ 



voltage relationships for the traveling wavefront at the two 
ends of the transmission line are shown alongside. 

From the graphs several important features can be seen. If the 
line is not matched at either end considerable transient voltage 
swings can occur. In fact if the input and output character- 
istics are at right angles to one another, the reflections con- 
tinue for an infinite time if the line is assumed to have zero 
loss. Most lines have extremely low losses, and, therefore, 
a very undesirable situation exists if the line is not matched at 
either end. 

If the line is matched at the receiver, a voltage wave of con- 
stant amplitude travels down the line and is absorbed at the 
termination. Note whether the line is terminated to ground or 
to the power supply the system consumes DC power, either 
in the HIGH logic level or in the LOW logic level. In order 
to reduce the power dissipation, a blocking capacitor can be 
used in series with the receiver termination. The capacitor can 
be chosen to look like a short circuit to the voltage wavefront 
but stop DC (current) flow. Since the capacitor must be charged 
and discharged through the line, the data rate is reduced, when 
this technique is employed. 

If the line is matched with a series resistor at the driver, then 
the line input initially rises to one half the final voltage. This 
wave front travels down the line and is reflected at the receiver. 
When the reflection reaches the driver the voltage at the driver 
rises to its final amplitude. The receiver, however, sees one 
transition from the initial to the final amplitude. When the 
driver switches from HIGH to LOW a similar situation occurs, 
in which the input of the line sees at first a step to one half the 
final value and, two line delays later, the final LOW condition. 
This back matching mode of operation consumes no DC power 
if the input impedance of the receiver is infinite. The advantage 
of the method is that if the input impedance of the receiver 
is high, very little power is dissipated and current only flows 
during the transition time, which is twice the line delay time. 
If back matching is used in a balanced system the terminating 
series resistance must be divided into two equal resistances 
with resistors inserted in series with each wire in order to 
maintain a balanced system. 



4-43 



Am26LS32 • Am26LS33 



SWITCHING FROM LOW TO HIGH 



Z 0ut L Zoot H 



SWITCHING FROM HIGH TO LOW 

Zout L 2 Out H 



VOLTAGE VERSUS TIME 




INPUT 
OF LINE 



r 

1 

















MATCHING AT 
RECEIVER TO 
GROUND 



MATCHING AT 
RECEIVER TO - 
SUPPLY 

Zo = Zin*Z L*ZoH 



INPUT 
OF LINE 



OUTPUT 
OF LINE 



INPUT 
OF LINE 




ZoutH 1 




Zout L 










/ V 



OUTPUT 
OF LINE 



IMPEDANCE PLOTS 

Figure 1. Line Matching Methods 



h. 



Metallization and Pad Layout 

vcc 




13 OUTPUT B 



ENABLE 
OUTPUT D 



'"] INPUTS D DIE SIZE 

1 0.087" X 0.059" 



EIA RS-422 AND 423 APPLICATIONS 



By David A. Laws and Roy J. Levy 



HODUCTION 

Today's high-performance data processing systems de- 
mand significantly faster data communications rates than 
are possible with the EIA RS-232 specifications in use for the 
past ten years. 

Two new standards prepared by the Electronic Industries 
Association address this need. EIA RS-423 is an unbalanced, 
bipolar voltage specification designed to interface with RS- 
232C, while greatly enhancing its operation. It permits the 
communication of digital information over distances of up to 
2000 feet and at data rates of up to 300 Kilobaud. EIA 
RS-422 is a balanced voltage digital interface for com- 
municaton of digital data over distances of 4000 feet or 
data rates of up to 10 megabaud. 

Advanced Micro Devices has developed a family of 
monolithic Low-power Schottky quad line drivers and re- 
ceivers to meet the requirements of these specifications. 

The Am26LS29 and 30 line drivers and the Am26LS32 re- 
ceiver meet all requirements of RS-423 while the 
Am26LS31 differential line driver and the Am26LS32 re- 
ceiver meet the requirements of RS-422. 

A second receiver element, the Am26LS33 is available for 
use in high common mode noise environments, exceeding 
the common mode voltage requirements of RS-422 and RS- 
423. 



This application note reviews the use of these devices in 
implementing the new standards. Emphasis is given to the 
EIA RS-422 balanced interface. 



EIA STANDARD SPECIFICATIONS 

Two basic forms of operation are available for transmission 
of digital data over interconnecting lines. These are the 
single ended and differential techniques. 

The single-ended form uses a single conductor to carry the 
signal with the voltage referenced to a single return conduc- 
tor. This may also be the common return for other signal 
conductors. Figure 1a. 

The single-ended form is the simplest way to send data as it 
requires only one signal line per circuit. This simplicity, how- 
ever, is often offset by the inability of this form to allow 
discrimination between a valid signal produced by the 
driver, and the sum of the driver signal plus externally in- 
duced noise signals. 

A solution to some of the problems inherent in the single- 
ended form of operation is offered by the differential form of 
operation. Figure lb. This consists of a differential driver 
(essentially two single-ended drivers with one driver always 
producing the complementary output signal level to the 
other driver), a twisted pair transmission line and a differen- 
tial line receiver. The driver signal appears as a differential 
voltage to the line receiver, while the noise signals appear as 
a common mode signal. The two signals, therefore, can be 
discriminated by a line receiver with a sufficient common 
mode voltage operating range. 

The Electronic Industries Association, EIA, has defined a 
number of specifications standardizing the interface be- 
tween data terminal equipment and data circuit terminating 
equipment based on both single-ended and differential op- 
eration. 



a) Single Wire With Common Ground. 




b) Two Wire Balanced System. 



DATA - 
ENABLE - 





Figure 1. Data Communication Techniques. 



4-45 



Use of the Am26LS29, 30, 31, and 32 



The most widely used standard for interfacing between data 
terminal equipment and data communications equipment 
today, is EIA RS-232C, issued in August 1969. The RS-232C 
electrical interface is a single-ended, bipolar-voltage, unter- 
minated circuit. This specification is for serial binary data 
interchange over short distances (up to 50 feet) at low rates 
(up to 20 Kilobaud). It is a protocol standard as well as an 
electrical standard, specifying hand shaking signals and 
functions between terminal and the communications 
equipment. As already noted, single-ended circuits are sus- 
ceptible to all forms of electromagnetic interference. Noise 
and cross talk susceptibility are proportional to length and 
bandwidth. RS-232C places restrictions on both. It limits slew 
rate of the drivers (30V//xs) to control radiated emission on 
neighboring circuits and allows bandwidth limiting on the 
receivers to reduce susceptibility to cross talk. The length 
and slew rate limits can adequately control reflections on 
unterminated lines, and the length and bandwidth limits are 
more than adequate to reduce susceptibility to noise. 



Like EIA RS-232C, the new EIA RS-423 is also a single-ended, 
bipolar-voltage unterminated circuit. It extends the distance 
and data rate capabilities of this technique to distances of up 
to 4000 feet at data rates of 3000 baud, or at higher rates of up 
to 300 Kilobaud over a maximum distance of 40 feet. 

EIA RS-422 is a differential, balanced voltage interface capa- 
ble of significantly higher data rates over longer distances. It 
can accommodate rates of 100 Kilobaud over a distance of 
4000 feet or rates of up to 10 megabaud. These performance 
improvements stem from the advantages of a balanced con- 
figuration which is isolated from ground noise currents. It is 
also immune to fluctuating voltage potentials between sys- 
tem ground references and to common mode electromag- 
netic interference. Figure 2 compares the driver output 
waveforms for the three EIA standard configurations, while 
Table I compares the key characteristics required by drivers 
and receivers intended for these applications. Since RS-232C 
has been in use for many years, RS-422 and 423 parameter 
values have been selected to facilitate an orderly transition 
from existing designs to new equipment. 







a) EIA RS-232C Generator Output. 





Vss = lv t - v,| 

V S s = Difference in steady 

state voltages 
R u = 3KH to 7KH 

Vss m ' n - = ±5V; Vss max - = -25V 



b) EIA 



RS-422 Generator Output. 

r 





t D = Time duration of the unit interval 
at the applicable modulation rate 
t r s 0.1t D when t 3 200ns 
t r s= 20ns when t D < 200ns 



V S s = Difference in steady state voltages 
V S S = |V t - Vtl 

V ss min. = 2V; V ss max. = 6V 



c) EIA RS-423 Generator Output. 






<son 

I 


3 


c 




v ss = Iv, - v t | 

Vss = Difference in steady 

state voltages 
V S s min. - 3:3.6V; V S s max. = 



Figure 2. Driver Output Waveforms. 



4-46 



Use of the Am26LS29, 30, 31, and 32 



TABLE I 

KEY PARAMETERS OF EIA SPECIFICATIONS 





Characteristics 


EIA RS-232C 


EIA RS-423 


EIA RS-422 


Units 


Fc 


rm of Operation 


Single Ended 


Single Ended 


Differential 




Max. cable length 


50 


2000 


4000 


Feet 


M 


ax. data rate 


20K 


300K 


10M 


Baud 


Driver output 
voltage, open 
circuit* 


±25 


±6 


6 volts 

between 

outputs 


Volts (Max.) 


Driver output 
voltage, Loaded 

nutnnt* 


±5 to ±15 


±3.6 


2 volts 

between 

outputs 


Volts (Min.) 


Driver output resis- 
tance power off 

Driver output short 
circuit current l sc 


no = 30011 
±500 


100/xA between 
-6 to +6V 

±150 


100/iA between 
+6 and -.25V 

±150 


Min. 

mA (Max.) 


Driver output slew 
rate 


30 VVsec Max. 


Slew rate must be 
controlled based 
upon cable length 
and modulation 
rate 


No control 
necessary 




Receiver input 
resistance R, n 


3K to 7K 




3=4K 


n 


Receiver input 
thresholds 


-3 to +3 


-0.2 to +0.2 


-0.2 to +0.2 


Volts (Max.) 


Receiver input 
voltage 


-25 to +25 


-12 to +12 


-12 to +12 


Volts (Max.) 



± indicates polarity switched output. 



INTEGRATED CIRCUIT CHARACTERISTICS 

Most semiconductor manufacturers offer integrated circuits 
designed to satisfy the old RS-232C standard. A number of 
them have designs in progress to meet the new EIA specifica- 
tions. Products available from Advanced Micro Devices to 
meet these needs are shown in Table II. 

The Am26LS29, 30, 31 and 32 are a family of quad drivers and 
receivers designed specifically to meet the new EIA stan- 
dards. These products utilize Low-Power Schottky technol- 
ogy to incorporate four drivers or four receivers, together 
with control logic, in the standard 16-pin package outlines. 

The Am26LS29/30 and the Am26LS32 are driver and receiver 
pairs designed to implement the single-ended EIA RS-423 
standard. The Am26LS31 is a differential line driver designed 
for use with the Am26LS32 receiver in a differential mode to 
meet EIA RS-422. 

Am26LS29 AND Am26LS30 QUAD 
RS-423 LINE DRIVERS 

The Am26LS29 and 30 consist of four single-ended line driv- 
ers designed to meet or exceed the requirements of RS-423. 
The buffered driver outputs are provided with sufficient 
source and sink current capability to drive 50 ohm to a virtual 
ground transmission line and high capacitive loads. The 
Am26LS29 has a three-state output control while the 
Am26LS30 has a Moae Control input that allows it to operate 
as a dual RS-422 driver (with suitable power supply change- 
si, Figure 3. 



input loading, one-half the normal fan-in. Since there are two 
inverters from each input to output, the driver is non- 
inverting. When operating in the RS-423 mode, the 
Am26LS29 and 30 require both +5V and -5V nominal value 
power supplies. This allows the outputs to swing symmetri- 
cally about ground - producing a true bipolar output. The 
Mode Control (Pin 4) of the Am26LS30 should be HI ortied to 

TABLE II 
ADVANCED MICRO DEVICES' 
EIA COMPATIBLE DEVICES 



Each of the four driver inputs, as well as the Enable/Mode 
Control input is a PNP Low-Power Schottky input for reduced 



EIA Standard 


Drivers 


Receivers 


RS-232C 


Am1488 
Quad Driver 

Am9616 

Triple Driver with 
logic control 

Am2616 

Quad Driver also 
specified for CCITT 
V.24 and MIL-188C 


Am 1489, 1489A 
Quad Receivers with 
response control pin 

Am9617 

Triple Receiver with 
optional hysteresis 

Am2617 

Quad Receiver specified 
over MIL range 


RS-422 


Am26LS31 
Quad Differential 
with three-state 
control gating 


Am26LS32 

Quad Differential Driver 
single-ended Receiver 


RS-423 


Am26LS29 
Quad Driver with 
three-state output 

Am26LS30 
Quad Driver with 
slew rate control 


Am26LS32 

Quad single-ended/ 

Differential Receiver 



4-47 



Use of the Am26LS29, 30, 31, and 32 




Figure 3. Am26LS29 and Am26LS30 Drivers. 



V cc . Each output is designed to drive the RS-423 load of 50 
ohms with an output voltage equal or greaterthan +3.6 volts 
in the HI state and -3.6 volts in the LO state. Each output is 
current limited to 150mA max. in either logic state. A Slew 
Rate control pin is brought out separately for each output to 
allow output ramp rate (rise and fall time) control. This pro- 
vides suppression of near end cross talk to other receivers in 
the cable. Connecting a capacitor from this node to that 



driver's respective output will produce a ramp (10^ to 909t) 
of 50ns typical for each picofarad of capacitance in that 
capacitor. RS-423 establishes recommended ramp rates ver- 
sus length of line driven and modulation rate, Figure 4. 

The Am26LS30 can be used at low data rates as a dual EIA 
RS-422 driver with three-state outputs by connecting the V E g 
supply and the mode control input to ground. 



Use of the Am26LS29, 30, 31, and 32 



Am26LS31 QUAD RS-422 DRIVER 

The Am26LS31 is a quad differential line driver designed to 
meet the RS-422 specification while operating with a single 
+5 volt supply. A common enable and disable function con- 
trols all four drivers, Figure 5. The driver features highspeed, 
de-skewed differential outputs with typical propagation de- 
lays of 12ns and residual skew of 2ns. Both differential line 
outputs are designed for three-state operation to allow 
two-way half duplex and multiplex, data bus applications. 



Table III is a summary of the essential requirements of the 
RS-422 standard. Section A describes the key characteristics 
satisfied by the Am26LS31 driver. 

The balanced differential line driver consists of two halves, 
each of which is similar to a Low-power Schottky TTL gate 
with equal source and sink current capability. The two halves 
are emitter coupled in a differential input configuration. One 
side of the input circuit is tied to a fixed TTL bias threshold 
and the other side is tied to a sink diode in normal DTUTTL 
fashion. This configuration offers complementary outputs 
with very low skew, dependent only upon component match- 
ing, a necessity to meet RS-422. 



The circuit diagram of the driver is shown in Figure 6. The 
emitter-coupled input circuit is formed by Q2 and Q3, which 
are biased by a current source. This source is a current 
mirror, formed by Q1 which supplies the current, and D6 
which is diode connected transistor matched to Q1 . The fixed 
bias for Q3, formed by D5 and D6, is 2V BE . A 2V BE bias, less 
the D2 Schottky diode drop, provides the normal Low-power 
Schottky TTL threshold, V, L = 0.7V. R19 provides a boost to 
0.8V for a full 400mV TTL noise margin. The differential 
outputs of the emitter coupled stage, A and A, drive emitter 
followers Q14 and Q15, which provide the required speed 
and matching characteristics. The emitter followers, drive 
phase splitters Q4 and Q5, which in turn drive totem-pole 
outputs. The outputs at the line interface are of standard 
Low-power Schottky TTL configuration, except that circuit 
values are modified to provide high sourcing capability. The 
outputs are designed to source or sink 20mA each, so that 
they can generate a voltage of at least 2.0V across a 1 00 ohm 
load, as required by RS-422. Additional circuitry has been 
included to make the line outputs three-state for two-way 
bus applications. The Am26LS31 meets the RS-422 require- 
ment that the driver not load the line in the powered down 
condition (l x « 100/xA) or if the power supply to that device 
should fail. 



Am26LS32 QUAD RS-422 AND 423 RECEIVER 

The Am26LS32 is a quad line receiver which, operating from 
a single 5 volt supply, can be used in either differential or 
single-ended modes to satisfy RS-422 and 423 applications 
respectively. A complementary enable and disable feature, 
similar to that on the driver, controls all four receivers, Figure 
7. The device's three-state outputs, which can sink 8mA, 
incorporate a fail-safe input-output relationship which keeps 
the outputs high when the inputs are open. 

The Am26LS32 meets the receiver input specification of 
Table III, a 200mV threshold sensitivity with common mode 
rejection exceeding the supply line potentials, (greater than 7 
volts). The same design feature of the input circuit which 
provides the common mode rejection also insures excellent 
power supply ripple rejection, which is important when 
switching the high currents involved in a system's interfaces. 
Furthermore, unlike operational amplifiers, where the DC 
common mode and power supply rejection ratios roll off 
with open loop gain, the full rejection capability of this line 
receiver is maintained at high frequencies. The receiver hys- 
teresis of typically 30mV, provides differential noise immuni- 
ty. Signals received on long lines can have slow transition 
times, and without hysteresis, a small amount of noise 
around the switching threshold can cause errors in the re- 
ceiver output. 




BLI-022 



Figure 5. Am26LS31 Logic Diagram. 



4-49 







1M 


10k 
K 4k 
I 

CO 

3 

100 
10 

1 


























































































































CM 

DATA MODULATION RATE - BAUDS 


























>) 


























4 












































































































































































































































V 


































- 






















































































































































k 300 100 10 
RISETIME-^s 



Figure 4. Data Modulation Rate or Cable Length 
Versus Risetime for EIA RS-423. 



Use of the Am26LS29, 30, 31, and 32 



TABLE III 

SUMMARY OF EIA RS-422 STANDARD FOR A BALANCED DIFFERENTIAL INTERFACE 



A. Line Driver 

Open Circuit Voltage (either logic state) 

Differential |V d0 | s 6.0V 

Common Mode l v cmo I * 3 °V 

Differential Output Voltage (across 100 ohm load) 
Either logic state |V(j| s max (0.5V do , 2.0V) 

Output Impedance 
Either logic state R G s 100 ohms 

Mark-Space Level Symmetry (across 100 ohm load) 
Differential |V ds | - |V dM | s 0.4V 

Common Mode |V cmS | - |V cmM | s 0.4V 

Output Short Circuit Current (to ground) 

Either Output |l sc | « 150mA 

Output Leakage Current (power off) 
Voltage Range -0.25V « V x « +6.0V 

Either Output at V x |l x | « 100piA 

Rise and Fall Times (across 100 ohm load) 
T = Baud Interval (t r , t f ) s max (0.1T, 20ns) 

Ringing (across 100 ohm load) 
Definitions 
V dS s = V d (steady state) 
V S s = V ds -V dM (steady state) 

Limits (either logic state) 
Percentage 
Absolute 



|V d -V dss l«0.1V ss 
2.0V « |V d | « 6.0V 



B. Line Receiver 

Signal Voltage Range 

Differential |V d | « 6.0V 

Common Mode |V cM | s 7.0V 

Single-Ended Input Current (power ON or OFF) 
Either Input at V x |V X | = 10V 

Other Input Grounded |l v | « 3.25mA 

Single-Ended Input Bias Voltage (other input grounded) 
Either Input Open Circuit |V B | « 3.0V 

Single-Ended Input Impedance (other input grounded) 
Either Input R L s» 4000 ohms 

Differential Threshold Sensitivity 
Common Mode Voltage Range |V cm | ss 7.0V 

Either Logic State |V T | « 200mV 

Absolute Maximum Input Voltage 
Differential |V d |=s12V 
Single-Ended |V X | s 10V 

Input Balance (threshold shift) 
Common Mode Voltage Range |V cm | « 7.0V 

Differential Threshold (500 ohms in series with each 

input) 

Either Logic State |V t |« 400mV 

Termination (optional) 
Total Load Resistance (differential) R T > 90 ohms 

Multiple Receivers (bus applications) 
Up to 10 receivers allowed. Differential threshold sen- 
sitivity of 200mV must be maintained. 

Hysteresis (optional) 
As required for applications with slow rise/fall time at 
receiver, to control oscillations. 

Fail Safe (optional) 
As required by application to provide a steady MARK or 
SPACE condition under open connector or driver 

power 
OFF condition. 



C. Interconnecting Cable 

Type 

Twisted Pair Wire or Flat Cable Conductor Pair 



Conductor Size 
Copper Wire (solid or stranded) 
Other (per conductor) 

Capacitance 
Mutual Pair 
Stray 

Pair-to-Pair Cross Talk (balanced) 
Attenuation at 150KHz 



24 AWG or larger 
R =s 30 ohms/1000 ft. 



C *s 20pF/ft. 
C s 40pF/ft. 



A 3 40dB 



4-50 



Use of the Am26LS29, 30, 31, and 32 




BLI-023 



Figure 6. Am26LS31 Circuit Diagram (Only one driver shown). 



The balanced differential line receiver is a three-stage circuit. 
The input stage consists of a low-impedance differential cur- 
rent amplifier with series resistor inputs to convert line signal 
voltage to current and provide a moderate input impedance. 
The input resistors provide an impedance greater than 6Kon 
each input, power on or power off, which exceeds the re- 
quirements of RS-422 and RS-423. This is one advantage of 
the current amplifier input circuit. Another advantage is that 
is can operate with immunity to common mode voltages 
above V cc and below ground. The differential threshold 
sensitivity of this circuit is 200mV, as required by RS-422. The 
second stage is a differential voltage amplifier, which inter- 
faces to the single-ended output stage through an emitter 
follower. The output stage is a standard Low-power Schottky 
TTL totem-pole output with three-state capability. 

The full circuit is shown in Figure 8. Resistors R 2 o and R 2 i, 
which connect the non-inverting input to V cc and the invert- 
ing input to ground, provide the fail-safe feature, which 
guarantees a HIGH logic state for the receiver output when 
there is no signal on the line. The differential voltage 
amplifier in the second stage is formed by Q6 and Q3 which 
are biased by current source Q9. The hysteresis in the re- 



ceiver switching characteristic is provided by Q4 and Q5, a 
differential pair biased by current source Q6, whose collec- 
tors are connected in positive feedback to the input pull-up 
circuits. A small amount of current is switched by 0.4 and Q5, 
which must be overcome by the different voltage signal, 
resulting in the hysteresis. The output stage is driven from 
one side of the differential second stage by emitter follower 
Q17, which is a multiple emitter transistor, the second emit- 
ter is the control point for the three-state output.Q17 drives 
the phase splitter Q12, which in turn drives the three-state 
totempole output. The remainder of the circuit is the output 
enable control logic. This three-state capability on t|»e re- 
ceiver TTL side of the interface is a useful feature for mod- 
ularizing two-way bus design. 

A mask option of the input resistors (R 1; R 2 , R 2 o and R 2 -|) 
modifies the receiver characteristics to improve operation 
in high common mode noise environments. This device, 
known as the Am26LS33, has these resistors at twice the 
value of the Am26LS32. An input differential or common 
mode voltage range of ± 1 5 volts is achieved at the expense 
of a minor decrease of input threshold sensitivity, to 
±500mV from ±200mV. 



4-51 



Use of the Am26LS29, 30, 31, and 32 



ABLE ENABLE IN D2 IN n 







Figure 7. Am26LS32 Logic Diagram. 



I *~1 



LJ 



I 



: R i8 < R i3 



V Ps 



<«19 



£3 




n 3i ; 



°21 



023 



■H3 

: ;»29 



022 



025 



"16> "17 




Note: R3 and R4 values for Am26LS32 are half the Am26LS33 values. 



Figure 8. Am26LS32 and Am26LS33 Circuit Diagram (Only one receiver shown). 



4-52 



Use of the Am26LS29, 30, 31, and 32 



APPLICATIONS IN MIXED RS-232 AND 422/3 
SYSTEMS 

A system implemented with the RS-422 differential output 
cannot be used to drive an RS-232C system directly. An 
RS-423 single-ended, driver, such as the Am26LS29 or 
Am26LS30, may be used provided certain precautions are 
obser 



1. Although the RS-423 driver output specification of be- 
tween 4 to 5V does not meet the RS-232C specification of 
6V, operation is usually satisfactory with RS-232C receiv- 
ers. This is achieved because the short cable lengths per- 
mitted by RS-232C cause very little signal degredation 
and because of the low source impedance of the RS-423 
driver. 

2. RS-232C specifies that the rise time for the signal to pass 
through the ±3.0V transition region shall not exceed 4% 
of the signal element duration. RS-423 requires much 
slower rise times, specified from 10% to 90% of the total 
signal amplitude, to reduce cross talk for operation over 
longer distances. Therefore, the RS-423 driver in the 
equipment must be waveshaped. This is achieved by 
selection of a capacitor value for the Am26LS30 to simul- 
taneously meet the requirements of both RS-423 and RS- 
232C for data rates covered by RS-232C. 

3. RS-423 specifies one common return ground for each 
direction of transmission, RS-232C requires only one 
for both directions of transmission. Care must be taken 
to insure that a return ground path has been created 
when interfacing between the two systems. 

4. RS-232C does not require termination, while it may be 
necessary for RS-422 and 423. Detailed consideration of 
termination is covered in the next section. 

Note that RS-422 and RS-423 specifies that receivers should 
not be damaged by voltages up to 12V, while RS-232C allows 
drivers to produce output voltages up to 25V. The Am26LS32 
receiver has been designed to avoid this hazard and can 
withstand input voltages of ±25 volts. 



RS- 



TRANSMISSION LINE FEATURES 



Any time a receiver and transmitter are connected with more 
than a few inches of a wire, problems due to reflections can 
arise if care is not exercised to terminate the line correctly. 
RS-422 describes the cable as a twisted pair of approximately 
12011 impedance terminated in a resistor R T . R T is not 
specified because there are two extreme values which may 
be chosen for the two following general classes of usage: (1) 
single direction transmission; and (2) multi-direction and 
multiple source transmission (party line). Considering the 
cable impedance only, the termination should equal the 
cable impedance of 120O. However this reduces the termi- 
nated cable resistance as seen by the driver to only 60fi, with 
resulting loading of the output signal. This loading causes a 
reduction of S/N ratio at the received terminal due to the 
decrease in signal voltage swing. The solution lies in a com- 
promise between an R T of 120H which provides maximum 
power transfer at a reduced S/N ratio or R T of 240fl which 
causes a mis-match of 2-to-1 but no S/N reduction. The 
choice is left to the user as it is system dependent. Both 
schemes will work for an average line length and should only 
approach the margins at maximum line length and 
maximum bit rates. 

Electronic Industries Association, when preparing EIA Stan- 



dard RS-422 conducted their tests with 24 gauge twisted pair 
wire. The resulting length vs. data rate, is published as a 
guideline in RS-422 (Figure 9). This shows two important 
results: (1) Unmodulated baseband (NRZ) signalling is not 
recommended at distances greater than 4000 feet; (2) At data 




100k 1M 
DATA RATE - BAUDS 



Figure 9. Data Rate Versus Cable Length for Balanced, 
Twisted Pair Cable (From EIA RS-422). 

rates above about 100KHz, the maximum cable length for 
acceptable signal quality is inversely proportional to data 
rate. 

Result (1) above is due to the DC resistance of the cable. For a 
4000 foot cable with a DC resistance of 30 ohms/1 000 feet, the 
DC series loop resistance is 240fl. The minimum allowable 
terminated differential load impedance is 90ft. The DC vol- 
tage attentuation is 90/(90 -240) = 1/4(6db), which is arbitrar- 
ily chosen as the maximum allowable limit. 

Result (2) is due to line losses. Laboratory tests using the 
26LS31 Line Driver connected to the 26LS32 Line Receiver by 
800 feet of ordinary 20 AWG twisted pair (Beldon #8205 
plastic-jacketed wire), terminated in its characteristic impe- 
dance of 100f! were evaluated. The input waveform was a 
500KHz square wave with (109? to 90%) rise and fall times of 
less than 10ns. The output waveform produced rise and fall 
times which together accounted for approximately one-half 
the period (t r + t f = 500ns). This was due to line loss and 
constant capacity. The energy per cycle of the output 
waveform is approximately 25% lowerthan that of the input. 
The input rise and fall times are not a function of line length, 
assuming matching termination. The output rise and fall 
times are dependent upon length in a complex manner. 
Furthermore, it can be shown by observation that they build 
up along the line. 

Many good reference sources are available on the subject of 
transmission lines (References 1, 2, 3 and 4). These will 
provide background information to the following discussion. 

Seshadri in Reference (1) has analyzed a line with series 
resistance losses and has shown that rise time varies with 
the square of the length. This shows series resistance to be a 
function of the square root of frequency. However when one 
tries to use this result in combination with the previous 
result, it becomes apparent just how difficult the problem is. 
In Reference (2), the authors point out that skin depth implies 
a frequency dependent series inductance as well as resis- 
tance, and that one cannot be considered without the other. 



4-53 



Use of the Am26LS29. 30, 31, and 32 



They go on to show how this leads to the same result; 
namely that rise and fall times vary with the square of dis- 
tance. 

No attempt will be made to explain here why Figure 5 shows 
maximum length varying inversely with frequency rather 
than with the square of frequency. Certainly many complex 
factors are involved. Our laboratory observations showed a 
dependence somewhere in between linear and square law. 

The Am26LS31 Quad Line Driver and the Am26LS32 Quad 
Line Receiver are capable of good, clean operation to the 
distance I mits and data rate limits of RS-422. 

SYSTEM APPLICATIONS 

The Am26LS30, 31, 32 and 33 can be combined in various 



signaling networks. Using Am26LS29, Am26LS30 and 
Am26LS32, Figure 10, a unidirectional RS-423 communica- 
tion can be constructed. Allowing for the voltage variation 
described earlier, RS-232C requirements can be satisfied. It 
should be noted that the Am26LS29 or Am26LS30 is used 
above to meet the bipolar requirements. If a single-ended 
line, Figure 11, is required without a bipolar requirement, the 
Am26LS31 can be used by biasing the reference terminal of 
the receiver to approximately 1 .5 volts. Note that additional 
resistors will enhance fail safe operation. 

Figu re 1 2 shows the use of the Am26LS31 and Am26LS32 to 
meet a balanced line, single direction RS-422 application. If 
bidirectionality is required, an additional termination should 
be added as shown in Figure 1 3. 



Am26LS29 OR 
Am26LS30 



i r\ 


t>| 


50S! COAX 


) 


' RT 










Figure 10. Unidirectional RS-423 (partial RS-232C). 












50fi COAX 


>RT I 




• 






2 VOLT 
BAIS 



Figure 11. Single-Ended Line Without Bipolar Requirement. 




TWISTED PAIR 

a) RS-422 Application. 





lk 




b) Improved Fail-Safe Margin. 
Figure 12. 



4-54 



Use of the Am26LS29, 30, 31, and 32 




BLI-031 



Figure 13. Bidirectional RS-422. 




BLI-032 

Figure 14. Party Line Configuration. 



a) Full Duplex Four-Wire Data Communication RS-422 Interface (with Data Modem). 



Am26LS30/32 Am26LS30/32 Am26LS30/32 Am26LS30/32 




BLI-033 



Figure 15. 



4-55 



Use of the Am26LS29, 30, 31, and 32 



b) Full Duplex Four-Wire Data Communication 
RS-422 Interface (without Data Modem). 





BLI-034 



Figure 15. (Cont.) 



The high speed capability of RS-422 has attracted the in- 
terest of many computer designers for use in the party 
line mode (Figure 14). The most common usage is that of 
a four wire full duplex exchange system (Figure 15). This 
mode of operation involves two pairs of wires each han- 
dling a single direction of traffic. The outgoing direction 
consists of one driver (Am26LS30 or Am26LS31) and n 
receivers (Am26LS32 or Am26LS33). The incoming direc- 
tion consists of one receiver (Am26LS32 or Am26l_S33) 
and n drivers (Am26LS30 or Am26LS31). This seems ex- 
tremely simple to organize. However, problems arise 
when system ground is considered. If the network of re- 
ceiver and driver span a moderate to long physical dis- 
tance, ground loop noise or differences are developed 
changing the voltage that appears at the terminals of all 
receivers and drivers except for the one driver that is ac- 



tive. It Temains the system reference as long as it is ac- 
tive. This induced or system developed voltage is referred 
to as Common Mode voltage (CMV) and as such must be 
considered as a device parameter. All manufacturers 
specify CMV capability of their receiver in compliance 
with RS-422 (approx. 7 volts plus signal) but there is no 
specification for drivers. If the dimensions of the system 
are short compared to 1/4 wave length of the maximum 
date rise and fall times, the CMV can be assumed to be 
minimal and drivers with single voltage supply and lim- 
ited negative CMV can be used, i.e., Am26LS31. If the sys- 
tem dimensions are large, the CMV will cause problems 
in that the driver will clamp to the ground the moment 
the collective or apparent voltage swings below minus 0.5 
volts relative to the driver ground, causing a short in the 
line and increasing level shift and noise. The clamping is 
caused in part by conduction of the l/C substrate diode. 
The problem can be avoided by using a driver with an 
output common mode range (Am26LS30). The Am26LS30 
guarantees an output CMV range of ±10 volts about the 
driver ground reference. New international standards are 
under consideration to specify this mode of operation. In 
conclusion, a good system of 4 wire full duplex for data 
communication would use as an outgoing pair an 
Am26LS30 line driver and up to 12 - Am26LS32 line re- 
ceivers, with a termination at the near and far ends of the 
cable. The same system would use as an incoming pair 
an Am26LS32 line receiver and up to 32 - Am26LS30 line 
drivers with only one enabled at a time and all others in 
three-state mode with cable termination at both near and 
far ends of the cable. 



Many other applications are possible using this family of 
devices. Although the designs are based on the require- 
ments of the EIA data communications specifications, 
they are not limited to these situations. Aircraft buses and 
internal equipment interconnections will benefit from the 
features offered by these products. 



REFERENCES 

1. Seshadri, S. R., Fundamental of Transmission Lines and Electromagnetic Fields, (U. of Wisconsin), Addison-Wesley, 
Reading, Mass., 1971. 

2 Adler, R. B., L. J. Chu, and R. M. Fano, Electromagnetic Energy Transmission and Radiation, (MIT), John Wiley & Sons, 
New York, 1963. 

3. Matick, R. E., Transmission Lines for Digital and Communication Networks, (IBM), McGraw-Hill, New York, 1969. 

4. Reference Data for Radio Engineers, (ITT), Fifth Edition, Howard W. Sams & Company, Indianapolis, 1974. 

5. Electronic Industries Association, 2001 Eye Street, N.W. Washington, D.C., RS Standard Proposal, RS-232C, August, 
1969. 

6. Electronic Industries Association, 2001 Eye Street, N.W. Washington, D.C., RS Standard Proposal 1220, Rev. RS-422, 
September 21, 1976. 

7. Electronic Industries Association, 2001 Eye Street, N.W. Washington, D.C., RS Standard Proposal 1221, Rev. RS-423, 
September 21, 1976. 







4-56 



Am26S10 •AirtfeSH 



Quad Bus Transceivers 



Distinctive Characteristics 

• Input to bus is inverting on Am26S10 

• Input to bus is non-inverting on Am26S1 1 

• Quad high-speed open collector bus transceivers 

• Driver outputs can sink 100mA at 0.8V maximum 



• Bus compatible with Am2905, Am2906, Am2907 

• Advanced Schottky processing 

• PNP inputs to reduce input loading 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 



FUNCTIONAL DESCRIPTION 

The Am26S10 and Am26S1 1 are quad Bus Transceivers 
consisting of four high-speed bus drivers with open-collector 
outputs capable of sinking 100mA at 0.8 volts and four 
high-speed bus receivers. Each driver output is connected 
internally to the high-speed bus receiver in addition to being 
connected to the package pin. The receiver has a Schottky 
TTL output capable of driving ten Schottky TTL unit 
loads. 

An active LOW enable gate controls the four drivers so 
that outputs of different device drivers can be connected 
together for party-line operation. The enable input can 
be conveniently driven by active LOW decoders such as 
the Am25LS139. 

The bus output high-drive capability in the LOW state 
allows party-line operation with a line impedance as low 
as 100S2. The line can be terminated at both ends, and still 
give considerable noise margin at the receiver. The receiver 
typical switching point is 2.0 volts. 

The Am26S10 and Am26S1 1 feature advanced Schottky 
processing to minimize propagation delay. The device 
package also has two ground pins to improve ground current 
handling and allow close decoupling between Vcc and 
ground at the package. Both GNDi and GND 2 should be 
tied to the ground bus external to the device package. 



ORDERING INFORMATION 



Package 
Type 



Temperature 
Range 



Am26S10 
Order 
Number 



Am26S11 
Order 
Number 



Molded DIP 
Hermetic DIP 

Dice 
Hermetic DIP 
Hermetic Flat Pack 
Dice 



C to +70 C 
0°Cto +70° C 
0°C to +70° C 
-55°Cto +125°C 
-55°Cto+125°C 
-55°C to +125°C 



AM26S1 0PC 
AM26S1 0DC 
AM26S1 0XC 
AM26S10DM 
AM26S10FM 
AM26S10XM 



AM26S1 1 PC 
AM26S1 1 DC 
AM26S1 1 XC 
AM26S11DM 
AM26S11FM 
AM26S11XM 



CONNECTION DIAGRAMS 
Top Views 



"CC "3 ^3 



E" l 2 Z 2 B 2 V CC ^3 z 3 '3 I '2 z 2 B 2 

nnnnnnnn, nnnnnnnn 



15 14 13 12 11 10 



UUUULJLJUU 



16 15 14 13 12 11 10 9 



GND, B Q Z i 



3 4 5 6 7 8 

uuuuuuuu 



67 GND 2 GND 1 2 



Note: Pin 1 is marked for orientation. 



Zf 8, GND 2 
LIC-369 



LOGIC SYMBOLS 



12 4 5 11 13 



"O h '2 '3 

zo 

Am26S10 z 1 
QUAD z_ 
TRANSCEIVER '* 



TTTT 

2 7 9 15 



12 4 5 11 13 



!Q h "2 '3 

zo 

Am26S11 z 1 
QUAD Z - 
TRANSCEIVER * 



TTTT 

2 7 9 15 



Vcc " Pin 16 
GND-, = Pin 1 
GNO, = Pin 8 



LOGIC DIAGRAMS 
Am26S10 



E 

t 



t t t t 



Am26S11 



E lg l 1 l 2 '3 







t 



4-57 



Am26S10« Am26S11 



MAXIMUM RATINGS (Above which the useful life may be impaired) 



^tnranp Tpmnpraturp 

o tt_n aye i cinpti oiui c 




-65°Cto +150°C 


Tom norati iro f A mhi pntl 1 InHpr Riac 

1 cl I 1 \JC 1 d L U 1 c 1 IUICI 1 L / Ul IUCI LJIclb 




-55°C to +125°C 


Qiir^nlv \/nltanP tri firminH Pntpntial 
ou yj [j i y vuiLuvjc L lj \J i uui iu r uLciiiiai 




—0.5V to +7V 


Clf \/rvltano Annlio/H tn Ontni itc fnr Minh Oiitniit ^tatp 




fl PiV tn +V^^ max 


DC Input Voltage 




-0.5V to +5.5V 


Output Current, Into Bus 




200 mA 


Output Current, Into Outputs (Except Bus) 




30 mA 


DC Input Current 




-30mA to +5.0 mA 



ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted) 

Am26S10XC, Am26S11XC T A - 0° C to +70° C V cc = 5.0 V i 5% (COM'L) MIN. = 4.75V MAX. = 5.25V 

Am26S10XM, Am26S11XM T A = -55° C to +1 25° C v cc = 5.0 V ± 10% (Ml L) MIN. = 4.5V MAX. = 5.5V 

Typ. 

Parameters Description Test Conditions (Note i) Min. (Note 2) Max. Units 



V H 




Output HIGH Voltage 
(Receiver Outputs) 


V CC = MIN., I 0H = -1.0mA 
V| N = V| L or V m 


MIL 


2.5 


3.4 




Volts 


COM'L 


2.7 


3.4 




v L 




Output LOW Voltage 
(Receiver Outputs) 


V CC = MIN., I 0L = 20mA 
V| N =V| L orV| H 






0.5 


Volts 


V| H 




Input HIGH Level 
(Except Bus) 


Guaranteed input logical HIGH 
for all inputs 


2.0 






Volts 


V| L 




Input LOW Level 
(Except Bus) 


Guaranteed input logical LOW 
for all inputs 






0.8 


Volts 


V| 




Input Clamp Voltage 
(Except Bus) 


V CC = MIN., I| N = -18mA 






-1.2 


Volts 


'IL 




Input LOW Current 
(Except Bus) 


V CC - MAX., V| N - 0.4V 


Enable 






-0.36 


mA 


Data 






-0.54 


'IH 




Input HIGH Current 
(Except Bus) 


V CC = MAX., V| N = 2.7V 


Enable 






20 


uA 


Data 






30 


'l 




Input HIGH Current 
(Except Bus) 


V CC = MAX., V| N = 5.5V 






100 


fA 


'sc 




Output Short Circuit Current 
(Except Bus) 


V CC = MAX. (Note 3) 


MIL 


-20 




-55 


mA 


COM'L 


-18 




-60 


'CCL 




Power Supply Current 
(All Bus Outputs LOW) 


V CC = MAX. 
Enable = GND 


Am26S10 




45 


70 


mA 


Am26S11 






80 



Bus Input/Output Characteristics 

Typ. 



Parameters 


Description 


Test Conditions (Nota 1) 


Min. 


(Note 2) 


Max. 


Units 










Iql = 40mA 




0.33 


0.5 










MIL 


lOL " 70mA 




0.42 


0.7 




v 0L 


Output LOW Voltage 


V cc = MIN. 




Iql "' 100mA 




0.51 


0.8 


Volts 




Iql = 40mA 




0.33 


0.5 








COM'L 


Iql = 70mA 




0.42 


0.7 












Iql " 100mA 




0.51 


0.8 












V = 0.8V 






-50 




io 


Bus Leakage Current 


V CC - MAX. 


MIL 


V = 4.5V 






200 


MA 








COM'L 


V - 4.5V 






100 




•off 


Bus Leakage Current (Power Off) 


V = 4.5V 






100 


«A 


V-TH 


Receiver Input HIGH Threshold 


Bus Enable = 2.4V 


MIL 


2.4 


2.0 




Volts 


V CC - MAX 




COM'L 


2.25 


2.0 




V-TL 


Receiver Input LOW Threshold 


Bus Enable = 2.4V 


MIL 




2.0 


1-6. 


Volts 


V CC = MIN 




COM'L 




2.0 


1.75 



Notes: 1 . For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type. 

2. Typical limits are at V cc = 5.0V, 25° C ambient and maximum loading. 

3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 



4-58 



Am26S10. Am26S11 

Switching 
Parameters 



istics (Ta = +25 C, V C C 
Description 



■■ 5.0V) 



Test Conditions 



Min. 



Typ. 



Max. 



Units 



«PLH 


Data Input to Bus 


Am26S10 


Rb = son 

CB = S0pF (NoteD 




10 


15 


ns 


tPHL 




10 


15 


tPLH 


Am26S1 1 




12 


19 


«PHL 






12 


19 


tPLH 


Enable Input to Bus 


Am26S10 




14 


18 


ns 


«PHL 




13 


18 


*PLh 




Am26S11 




1 5 


20 


«PHL 






14 


20 


*PL> 




Bus to Receiver Out 


R B = 500, R L = 280S2 
C B = 50pF (Note 1), C L = 15pF 




10 


15 


ns 


«PHl 






10 


15 


«r 




Bus 


Rg = 50n 
C B = 50pF (NoteD 


4.0 


10 




ns 


tf 




Bus 


2.0 


4.0 




ns 



Note 1 



Includes probe and jig capacitance. 



TRUTH TABLES 



Am26S10 
Inputs Outputs 



Am26S11 
Inputs Outputs 



E I 


B Z 


L L 
L H 
H X 


H L 
L H 

Y Y 



E I 


B Z 


L L 

L H 
H X 


L H 
H L 
Y Y 



H = HIGH Voltage Level 
L = LOW Voltage Level 
X = Don't Care 

Y = Voltage Level of Bus (Assumes Control by 
Another Bus Transceiver) 



Am26S10/Am26S11 SCHEMATIC DIAGRAM 



1 



D, 

X 



(15} 



TO ONE 
OTHER 
DRIVER 



'cc 



= Pin 16 
GND] = Pin 1 
GND 2 - Pin 8 

— Connect for Arp26S1 

Remove R 1( Q 1 , D-| for Am26S10 

LIC-374 



4-59 



Am26S10. Am26S11 



TYPICAL PERFORMANCE CURVES 



Typical Bus Output Low Voltage 
Versus Ambient Temperature 



Receiver Threshold Variation 
Versus Ambient Temperature 



V 


x " 


■5.C 


w 


































BUS 


= 100mA 










'bus 


- 70mA 










-t-t-r- 














BUS 


-- 4 


rn A 





























0.2 


-55 -35-15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - "C 











































; - 5.5V 


















V CC -5 


25V 








_ I. 








75V 






M'L 






"C: 


; = 4 




ICC 






V 
















• = - 


SV 

















































-55 -35-15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - "C 



TYPICAL APPLICATION 



l/2 0FAm25l_S139 



l 'I 12 l 3 

Am26S10 Z 2 
*3 




E 


l '1 


! 


















1 




Am26S10 
















B, B 2 


3:- 





B, B 2 B 3 
7 



1111 




100ft PARTY-LINE OPERATION. 



Am26S10 



GND] 1 



*0 3 




Metallization and Pad Layout 



15 B 3 



Am26S11 



10 z 2 




DIE SIZE 0.059" X 0.075" 



DIE SIZE 0.059" X 0.075" 



4-60 



Am26S10 • Am26S11 



SWITCHING CHARACTERISTICS 



TEST CIRCUIT 



PULSE 
GENERATOR 
NO. 1 



PULSE 
GENERATOR 
NO. 2 



I50pF 
(Note 1} 



TEST 
POINT 
O 



15pF 
(Note 1) 



ALL DIODES 
1N916 OR 
EQUIVALENT 



Note 1. Includes Probe and Jig Capacitance. 



B TEST POINT 



Z TEST POINT 



[- l PHL -J f- — \- "PLH — 



r 



4-61 



Am26Sl2-Am26S12A 

Quad Bus Transceiver 



Distinctive Characteristics 

• Quad high-speed bus transceivers 

• Driver outputs can sink 100mA at 0.7V typically 



• 100% reliability assurance testing in compliance with 
MIL-STD-883 

• Choice of receiver hysteresis characteristics 



FUNCTIONAL DESCRIPTION 



The Am26S1 2 • Am26S1 2A are high-speed quad Bus Transceivers con- 
sisting of four high-speed bus drivers with open-collector outputs 
capable of sinking 100mA at 0.7 volts and four high-speed bus receivers. 
Each driver output is brought out and also connected internally to the 
high-speed bus receiver. The receiver has an input hysteresis charac- 
teristic and a TTL output capable of driving ten TTL Loads. 
An active LOW, two-input AND gate controls the four drivers so that 
outputs of different device drivers can be connected together for party- 
line operation. The enable inputs can be conveniently driven by active 
LOW decoders such as the Am54S/74S1 39. 

The high-drive capability in the LOW state allows party-line operation 
with a line impedance as low js "\Q0Cl. The line can be terminated at 
both ends, and still give conoiderable noise margin at the receiver. The 



hysteresis characteristic of the Am26S12 receiver is chosen so that the 
receiver output switches to a HIGH logic level when the receiver input 
is at a HIGH logic level and moves to 1.4 volts typically, and switches 
to a LOW logic level when the receiver input is at a LOW logic level and 
moves to 2.0 volts typically. This hysteresis characteristic makes the 
receiver very insensitive to noise on the bus. 

The Am26S12A is functionally identical to the Am26S12 but has a 
different hysteresis characteristic so that the output switches with the 
input being typically at 1.2 volts or 2.25 volts. In both devices 
the threshold margin, the difference between the switching points, is 
greater than 0.4 volts. 



LOGIC DIAGRAM /SYMBOL 



7 9 

ft 



2 5 11 14 



Z 

Am26S12»Am26S12A Z, 
QUAD z 
TRANSCEIVER 2 

23 



t t t t 



1 a 12 15 



V CC = PIN 16 
GND = Pin 8 



Package 
Type 



ORDERING INFORMATION 

Am26S12 Am26S12A 

Temperature Order Order 

Range Number Number 



Molded DIP 
Hermetic DIP 

Dice 
Hermetic DIP 
Flat Pak 
Dice 



0°C to +75° C 
0°C to +75° C 
0°Cto +7S°C 
-55° C to +125°C 
-55°Cto +125°C 
-S5°Cto +12S°C 



AM26S12PC 
AM26S12DC 
AM26S12XC 
AM26S12DM 
AM26S12FM 
AM26S12XM 



AM26S1 2APC 
AM26S12ADC 
AM26S12AXC 
AM26S1 2ADM 
AM26S1 2AFM 
AM26S12AXM 



CONNECTION DIAGRAM 
Top View 




uuuuuuuu 

% l 2 B"i I 1 Z, E GND 
Note: Pin 1 is marked for orientation. 



i26S12/Am26S12A 
MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65 C to +150 C 



Temperature (Ambient) Under Bias 



-55 Cto+125 u C 



Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous 



-0.5V to +7V 



DC Voltage Applied to Outputs for High Output State 



-0.5V to +V C c max. 



DC Input Voltage 



-0.5V to +5.5V 



Output Current, Into Outputs (BUS) 



200mA 



Output Current, Into Outputs (Receiver) 



30m,a 



DC Input Current 



-30mA to +5.0mA 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) 



Am26S12XC Am26S12AXC 
Am26S12XM Am26S1 2AXM 



■ C to + 75 C 



Parameters 



T A « -55 C to +125 C 

Description 



V cc = 5.0V ±5% (COM Range) 

V cc = 5.0V +10% (MIL Range) Note 1 



Units 



'cc 




Power Supply Current 


Vcc = MAX. 




46 


70 


mA 


'BUS 




Bus Leakage Current 


Vcc = max. or °v; 

Vbus = 4.0V; Driver in OFF State 






100 


nA 


Driver 


Characteristics 


vol 

(Not« 


i) 


Output LOW Voltage 


V CC = MM. 

V| N = V IH orV IL 


COM'L 


'OL = 100mA 




0.7 


0.8 


Volts 


MIL 


lOL = 60mA 




0.55 


0.7 


Volts 


Iql = 100mA 




0.7 


0.85 


V| H 




Input HIGH Voltage 




2.0 






Volts 


V| L 




Input LOW Voltage 








0.8 


Volts 


v. 




Input Clamp Voltage 


V CC = MIN., I| N = -18mA 






-1.2 


Volts 


l| 




Input Current 

at Maximum Input Voltage 


Vcc = MAX., V| = 5.5V 






1.0 


mA 


'IH 


Unit Load 

Input HIGH Current 


V CC = MAX., V| N 2.4V 




1.0 


40 


mA 
mA 


'IL 


Unit Load 

Input LOW Current 


V CC = MAX., V|= 0.4V 




-0.4 


-1.6 



Receiver Characteristics 



V H 




Output HIGH Voltage 


V CC = MIN., l OH = -800uA 
V IN = V |L (Receiver) 


2.4 






Volts 


vol 




Output LOW Voltage 


Vcc = MIN - 'OL = 20mA 
V|l\| = V|l (Receiver) 




0.4 


0.5 


Volts 


V| H 




Input HIGH Level Threshold 


E = H 


Am26S12 


1.8 


2.0 


2.2 


Volts 


Am26S12A 


2.05 


2.25 


2.45 


V| L 




Input LOW Level Threshold 


E = H 


Am26S12 


1.2 


1.4 


1.6 


Volts 


Am26S12A 


1.0 


1.2 


1.4 


v T m 




Input Threshold Margin 


E = H 


0.4 






Volts 


'OS 




Output Short Circuit Current 


Vcc = MAX., V 0UT = 0.0V 


-20 




-55 


mA 



Notes: 1. For the Am26S12FM, Am26S 1 2AFM the output current must be limited at 60mA or the maximum case temperature limited to 1 25 C for correct 
operation. 

2. Typical limits are at Vcc ™ 5.0V, 25 C ambient and maximum loading. 



Switching Characteristics (T A = 25°C, Vcc = 5.0V) 



Parameters 


Description 


Conditions 


Min. 


Typ. 


Max. 


Units 


«PLH 


Turn Off Delay Input to Bus 


Clb " 15pF, Rlb = ioon 




7 


11 


ns 


tPHL 


Turn On Delay Input to Bus 


C LB = 300pF, R LB ■ 500 




14 


21 


ns 


'PLH 


Turn Off Delay Enable to Bus 


Clb = 15P F . r lb = 5012 




10 


15 


ns 


»PHL 


Turn On Delay Enable to Bus 


Clb = ispf, Rlb - son 




10 


15 


ns 


tPLH 


Turn Off Delay Bus to Output 


C L = 15pF 




18 


26 


ns 


tPHL 


Turn On Delay Bus to Output 


C L = 15pF 




18 


26 


ns 



4-63 



Am26S12/Am26S12A 



SWITCHING CIRCUITS AND WAVEFORMS 




Frequency 5MHz 

t r = tf = 2 ns Measured Between 

1 V to 2 V Levels. 



f— - l PHL 

v — 



1. 



-3 



■ 1.5V 

■ ov 



Figure 1. Bus Propagation Delays 




i 



1. 



\ - r 



Figure 2. Receiver Propagation Delays 



Am26S12/Am26S12A 



TRUTH TABLE 
Am26S12/26S12A 
Inputs Outputs 





B Z 


L L 
L H 
H X 


H L 
L H 

Y Y 



H = HIGH Voltage Level 
L = LOW Voltage Level 
X - Don't Care 
Y = Voltage Level of Bus 



Table I 



MSI INTERFACING RULES 

Equivalent 

Interfacing Input Unit Load 

Digital Family HIGH LOW 



Advanced Micro Devices 9300/2500 Series 


1 


1 


FSC Series 9300 


1 


1 


Tl Series 54/7400 


1 


1 


Signetics Series 8200 


2 


2 


National Series DM 75/85 


1 


1 


DTL Series 930 


12 


1 



Table II 



PERFORMANCE CURVES 



Atti26S1 2 Typical 
Receiver Input Characteristic 

3.6 
3.2 



Am26S12A Typical 
Receiver Input Characteristic 



LIC-387 















































































































































































L 












H 







































1.2 1.4 1.6 1.8 2.0 2.2 2.4 
V| N -INPUT VOLTAGE-VOLTS 



1.2 1.4 1.6 1.8 2.0 2.2 
V| nj— INPUT VOLTAGE - VOLTS 



Figure 3 



Figure 4 



INPUT/OUTPUT CIRCUITRY 




Am26S12/Am26S12A 



Am26S12/26S12A APPLICATION 




Am26S12/26S12A 



' RECEIVER 
. OUTPUTS 











E l h 12 13 




H "2 '0 '3 












Z, 

Am26S12/26S12A % 


RECEIVER 

OUTPUTS 


Mi 

Am26S12/26S12A z? 








Z3 




B B 5 B 2 B 3 




Bq B] B 2 83 





■ RECEIVER 
. OUTPUTS 



Am26S12'26S12A 



Bo B, B2 B3 

6 6 



• RECEIVER 

. OUTPUTS 




100n PARTY-LINE OPERATION 



Figure 6 




Am 2614 

Quad Single-Ended Line Driver 



Distinctive Characteristics 



Quad single-ended driver for multi-channel common 
ground operation 
Single 5V power supply 
• DTL, TTL compatible 





• Short-circuit protected outputs 

• Capable of driving 50f2 terminated transmission lines 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 



FUNCTIONAL DESCRIPTION 

The Am2614 is a DTL, TTL compatible line driver operating 
off a single 5V supply. The Am2614 is a quad inverting driver 
with two separate inputs and one common-strobe input for 
each pair of drivers. The device has active pull-up outputs for 
high-speed and HIGH capacitance drive. The Am2614 is ideal 
for sinyle-ended transmission line driving, or as a high-speed, 
high-fan-out driver for semiconductor memory decoding, buf- 
fering, clock driving and general logic use. 

The Am2614 has short" circuit protected active pull-ups, and 
incorporates input clamp diodes to reduce the effect of line 
transients, and also is capable of driving 50f2 terminated trans- 
lines. 



LOGIC DIAGRAM 



DRIVERS A,, A 2 




DRIVERSB,, B 2 




v cc = 

GND : 



Pin 16 
Pin 8 



CIRCUIT DIAGRAM 




O 7(91 



Package 
Type 



ORDERING INFORMATION 



Temperature 
Range 



Order 
Number 



Hermetic DIP 
Flat Pak 

Dice 
Hermetic DIP 
Molded DIP 

Dice 



-55 C to +125 C 
-55°C to +125°C 
-55°C to + 125°C 
0°C to +70°C 
0°C to +70°C 
0°C to +70°C 



AM2614DM 
AM2614FM 
AM2614XM 
AM2614DC 
AM2614PC 
AM2614XC 



CONNECTION DIAGRAM 
Top View 



STROBE A 
INPUT A, [2 
INPUT A, £ 
OUTPUT A, £ 
INPUT A 2 £ 
INPUT A 2 Q 
OUTPUT A 2 [~J 
GNO 



15 □ STROBE B 
14 □ INPUTS, 
13 ^ INPUT B, 
12 □ OUTPUT B, 
,, ^ INPUT B 2 
,0 3] INPUT B 2 
1 I OUTPUT B 2 



Note: Pin 1 is marked for orientation. 



4-67 



Am2614 



MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65°C to +150°C 



Temperature (Ambient) Under Bias 



-55°Cto +125°C 



Supply Voltage to Ground Potential (Pin 16 to Pin 8) Continuous 



-0.5 V to +7V 



DC Voltage App ied to Outputs for HIGH Output State 



-0.5 V to +V CC max 



DC Input Voltage 



-0.5 V to +5.5 V 



Output Current, 



Into Outputs 



mA 



DC Input Current 



Note 1 



ELECTRICAL 

The following 

Am2614XM (Ml 
Am2614XC (CO 



CHARACTERISTICS 

conditions apply unless otherwise noted: 

T A « -55° C to +125° C V CC MIN. =• 4.50V 

) T A - 0°C to +70°C V CC MIN. =4. 75V 



:>m 



DC Characteristics (Note 2) 



Parameters 



Description 



Test Conditions 



V CC MAX. 1 5.50V 
V CC MAX. - 5.25V 



TaMIISI. 
Min. Max. 



Min. 



LIMITS 

+25° C 
Typ. Max. 



TaMAX. 
Min. Max. 



Units 



V H 





itput HIGH Voltage 


V C c = MIN., 
Iqh = —10mA 




2.4 




2.4 


3.2 




2.4 




Volts 


vol 





utput LOW Voltage 


V C c = MIN., 
Iql = 40mA 


MIL 




0.4 




0.2 


0.4 




0.4 


Volts 


COM'L 




0.45 




0.2 


0.45 




0.45 


V| H 


In 


put HIGH Voltage 


V cc = MIN. 


MIL 


2.0 




1.7 


1.5 




1.4 




Volts 


COM'L 


1.9 




1.8 


1.5 




1.6 




V| L 


In 


put LOW Voltage 


V CC = MAX. 


MIL 




0.8 




1.3 


0.9 




0.8 


Volts 


COM'L 




0.85 




1.3 


0.85 




0.85 


if 


In 


put Load Current 


V CC = MAX. 


V F -0.4V, MIL 




-2.4 




-1 .65 


-2.4 




-2.4 


mA 


V F = 0.45V, COM'L 


|r 


R 


3verse Input Current 


Vcc = MAX. 
V R • 4.5V 






90 






90 




90 


M A 


•sc 


S 


lort Circuit Current 


Vcc - MAX., 
V = OV 








-40 


-90 


-120 






mA 


IPD 


P< 


>wer Supply Current 


Vcc * MAX., 
Inputs = 0V 






48.7 




33 


48.7 




48.7 




V CC " 7.0V, 
Inputs = V 


COM'L 








46 


70 








MIL 








46 


65.7 








'CEX 


R 


everse Output Current 


V CC -MAX. 


V C EX 5.5V, MIL 




100 




10 


100 




200 


MA 


V CEX = 5.25V,COM'L 




100 




10 


100 




200 


v OLC 


O 


utput Low Clamp Voltage 


V CC ' MAX., 
lOLC = —40mA 










-0.8 


-1.5 






Volts 


Vic 




put Clamp Voltage 


V C c ' MIN.. 
I|C = -12mA 










-1.0 


-1.5 






Volts 



Switching Characteristics (T A = 25°C unless otherwise specified) 



Am2614XM 



Am2614XC 



Parameters 


Description 


Test Conditions 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Units 




Turn Off Delay 


V C c = 5 -°V, C|_ = 30pF, 




8 


12 




8 


15 


ns 


«pd- 


Turn On Delay 


V M = 1 .5V, Refer to Fig. 92 




7 


10 




7 


12 


ns 



Notes: 1. Maximum current defined by DC input voltage. 

2. For conditions shown as MIN. or MAX., use the 
grade. 



value specified under Electrical Characteristics for the applicable device type or 



4-68 



Am2614 



TYPICAL ELECTRICAL CHARACTERISTICS 



Output Low Current Versus 
Output Low Voltage 



T A .25'C 










! 












v cc ■ 55 v -h 














)V^__ 
































s 


cc ■ 4 5 v 



























































0.1 0.2 0.3 0.4 0.5 0.6 0.7 
V 0L - OUTPUT VOLTAGE - VOLTS 



Output High Current Versus 
Output High Voltage 



T fl -25-C 










h 


















"cc 


■4.5 


V 

V^ 






















"CC 




v— 



















































































3.6 



V OH - OUTPUT VOLTAGE - VOLTS 



4.0 



Logic Levels Versus 
Ambient Temperature 




V OL @I OL .40 mA- 

" M i l l" 



-20 20 60 100 
- AMBIENT TEMPERATURE - 



Supply Current Versus 
Supply Voltage 



NO LOAD 

T A -25"C 




























































■2/7 


















/, 
















































A 


w 



























































































2 4 6 8 10 

V cc - SUPPLY VOLTAGE - VOLTS 



Supply Current Versus 
Temperature 



1 1 1 

V rr = 5.0 V 















_;tp 


JTS 


OP 


.N 


































-< — 






An 


26 


-1 

























































































-20 20 60 100 1 40 
- AMBIENT TEMPERATURE - "C 



Supply Current Versus 
Operating Frequency 



-= 5 V | 
' ■ 30 pF 
= 25 C 



0-5 1.0 2.C 50 10 
- FREQUENCY - MHz 



Propagation Delay Time 
Versus Temperature 



i [ 

V CC -5.0V 


















30 


>F 




































































PL 








1PHL 





















































-60 -20 20 60 100 140 
T. - AMBIENT TEMPERATURE - "C 



Transfer Characteristics 
Versus Temperature 



V CC =5.0V 






















































t~ 





















^ ■ 


" A = 1 25 C 
r A - 25 C" 
r. = 5S"r_ 
























r 


-i 












— 




































J 















1.0 1.5 2 2.5 3.0 3 5 
- INPUT VOLTAGE - VOLTS 



Transfer Characteristics 
Versus Supply Voltage 











V rr • 5.5 V 








1 

■ 5 V — 














V CC • 4.5 V 


















' 




























- - 

■ 









































1.0 1.5 2.0 2.6 3.0 3.5 
- INPUT VOLTAGE - VOLTS 



4-69 



USER NOTES 

SINGLE ENDED LINES. The Am2614 quad line driver and 
the Am2615 dual differential amplifier allow data to be trans- 
mitted with only a single data wire per channel and a common 
ground for typically 8 data wires. This single-ended mode of 
interconnection offers considerable savings in integrated cir- 
cuit packages required and effectively halves the number of 
interconnections as compared to a balanced differential system. 
The method still gives ±15V common mode rejection and DC 
noise margin of interconnected TTL logic. The common ground 
wire should be twisted in with the data wires so that any 
injected noise is common to all wires. If a multiwire cable 
with screen is used one of the wires is used as the common 
ground line, and the screen is tied to ground at the driving 
end only. 

MATCHING. Transmission lines can be matched in a number 
of ways. The most widely used method is to terminate the 
line at the receiving end in its characteristic impedance. This 
impedance is connected across the input terminals of the 
receiver. A 130X2 resistor is included at the + input of each 
receiver for matching twisted pairs and this resistor, or if 
the characteristic impedance is not 130J2, a discrete resistor is 
connected between the two receiver inputs. This method of 



Am2614 



matching causes a DC component in the signal. Power is dis- 
sipated in the resistor and the signal is attenuated. The DC 
component can be effectively removed by connecting a large 
capacitor in series with the terminating resistor. 

The transmission line can also be terminated through the 
receiver power supply by placing equal value resistors from 
the + input of the receiver to Vqc and from the - input to 
ground. This method again has the disadvantage that a DC 
signal component exists, attenuation occurs, and power is 
dissipated in the terminating resistors but it does allow multi- 
plexed operation in the balanced differential mode. 

An alternate method of matching at the receiver is to back 
match at the driver. A resistor is placed in series with the line 
so that the signal from the driver which is reflected at the 
high input impedance of the receiver is absorbed at the driver. 
This method does not have a DC component and therefore no 
attenuation occurs and power is not dissipated in the resistor. 
For balanced differential driving a resistor is required in series 
with each line. The table below shows the value of each 
matching resistor required for lines of different characteristic 
impedance. 



TYPICAL DC CHARACTERISTICS 

FOR MATCHING TO TRANSMISSION LINE 




BACK MATCHING TABLE 



Zo 


R u (ohms) 


SINGLE ENDED 


50 


24 


75 


51 


92 


68 


100 


75 


130 


110 


300 


280 


600 


580 



-4 -2 2 4 6 8 
V 0UT - OUTPUT VOLTAGE - VOLTS 



LOADING RULES 

Input Output 



Fanout 



Output 



Input/Output 


Pin No.'s 


Unit Load 


HIGH 


LOW 


Strobe A 


1 


3 






Input A, 


2 


1.5 






Input A, 


3 


1.5 






Output A, 


4 




166 


25 


Input A z 


5 


1.5 






Input A 2 


6 


1.5 






Output A 2 


7 




166 


25 


GND 


8 








Output B 2 


9 




166 


25 


Input B 2 


10 


1.5 






Input B 2 


11 


1.5 






Output B 2 


12 




166 


25 


Input B, 


13 


1.5 






Input B, 


14 


1.5 






Strobe B 


15 


3 






Vcc 


16 









4-70 



Am2614 



APPLICATIONS 



Single-Ended Back-Matched Operation 
With Common Ground 



1/2 Am2614 



3 1— V 4 "M 

2 JO- Wr- 

OUTPUT Is 

STROBE J 




Am2615 



7> 





SWITCHING CIRCUITS AND WAVEFORMS 





- *PHL tpLH - 



» \ 

"out iai \ v 



- l PLH *PHL - 




INPUT PULSE 
Frequency = 500 kHz 
Amplitude = 3.0 ±0.1 V 
Pulse Width — 110 ±10 ns 
t, — t, < 5.0 ns 



Figure 1. 



4-71 



Am2615/9615 

Dual Differential Line Receivers 



Distinctive Characteristics: 

• Dual differential receiver (Am9615) pin-for-pin 
equivalent to the Fairchild 9615 

• Dual differential receiver for single-ended data 
(Am2615) 

• Single 5-volt supply 

• High common-mode voltage range (±15 volts) 



• Frequency response control, strobe, and internal ter- 
minating resistor 

• Am2615 has fail safe capability 

• Choice of uncommitted collector or active pull-up 
outputs 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 



FUNCTIONAL DESCRIPTION 

The Am2615 and Am9615 are dual differential line receivers 
designed to receive digital data from transmission lines and 
operate over the military and industrial temperature ranges 
using a single 5 volt supply. The Am2615 can receive 3 volt 
single ended and the Am9615 ±500 mV differential data in 
the presence of high level (±15 V) common mode voltages 
and deliver undisturbed logic levels to the following DTL 
or TTL circuitry. The response time of each receiver and 
thereby immunity to AC noise can be controlled by an ex- 
ternal capacitor. A strobe is provided for each receiver to- 
gether with a 130J2 input terminating resistor. Each output has 
an uncommitted collector with an active pull-up network avail- 
able on an adjacent pin. 

The Am2615 is identical to the Am9615 except for the 
input offset (threshold) voltage. The Am2615 has an input 
threshold of ~1.5V compatible with DTL & TTL logic. The 
Am9615 has an input threshold of ~0 V. The Am2615 can 
directly replace the Am9615 and give fail safe protection in 
differential systems where the input difference is >2.0 V. 



LOGIC DIAGRAM 



13 14 




12 15 




Vcc = 
GND . 



PIN 16 

: PIN 8 



CIRCUIT DIAGRAM 




Am2615 0NLV 



ORDERING INFORMATION 



Part 


Package 


Temperature 


Order 


Number 


Type 


Range 


Number 




Hermetic DIP 


-55°Cto +12B°C 


AM2615DM 




Flat Pak 


-55° C to +125°C 


AM2615FM 


Am2615 


Dice 


-55° C to +125°C 


AM2615XM 


Hermetic DIP 


0°C to +75°C 


AM2615DC 




Molded DIP 


0°C to +75°C 


AM2615PC 




Dice 


0°C to +75°C 


AM2615XC 




Hermetic DIP 


-55°Cto+125°C 


961 5DM 




Flat Pak 


-55°Cto+125°C 


9615FM 


Am9615 


Dice 


-55"C to +12S°C 


AM9615XM 


Hermetic DIP 


0°C to +75°C 


9615DC 




Molded DIP 


0°C to +75°C 


961 5PC 




Dice 


0°C to +75°C 


AM9615XC 



CONNECTION DIAGRAM 
Top View 



ACTIVE PULL UP A Q 2 
STROBE A ^ 3 
RESPONSE CONTROL A Q 4 
+ INPUT A Q 5 
130J1 6 
-INPUT A C 7 
GNDf-L— 



OUTPUT B 

□ ACTIVE PULL UP B 

□ STROBE B 

□ RESPONSE CONTROL B 

□ ♦ INPUT B 
JO ZJf30S3 B 

-INPUT 8 



NOTE: PIN 1 is marked for orientation. 



4-72 



Am2615/9615 

MAXIMUM RATINGS 

Storage Temperature 



(Above which the useful life may be impaired) 



-65°Cto +150°C 



Temperature (Ambient) Under Bias^ 



-55-C to +125°C 



Supply Voltage Jo Ground PotentialJPin 16 to Pin 8) C ontinuous 



-0.5 V to +7 V 



DC Voltage Applied to Outputs for HIGH Output State 



-0.5 V to +13.2 V 



DC Strobe Input Voltage 



-0.5 V to +5.5 V 



DC Data Input Voltage 



-20V to + 20 V 



Output Current, Into Outputs 



30 mA 



DC Inpu C urrent 



maximum current is defined by DC Input Voltage 



Am2615 ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE 

cc = 4.5V to 5.5V 



Am2615XM 
Arr.2615 



T A - -55°C to +125°C 
V CC = 4.75V to 5.25V T A = 0° C to + 75° C 



(Ml L grade) 
(COM' L grade) 



Parameters Description 



Test Conditions 



LIMITS 

T A = Min T A = 25°C T A = Max 
Min Max Min Typ Max Min Max 



Units 



^OH 




Output HIGH Voltage 


V cc = MIN, l OH = -5.0 mA 
V IN+ = +0.8V, V IN _ = 0V 


2.4 


2.4 3.2 


2.4 


Volts 


Vol 




Output LOW Voltage 


V cc = MAX 

l OH = 15.0 mA 

V IN+ = +2.0V, V IN _ = 0V 


Ml L grade 


0.40 


.18 0.40 


0.40 


Volts 


COM'L grade 


0.45 


.25 0.45 


0.45 


'ceX 




Output Leakage Current 


V cc = MIN 

v, N+ - ov 

V lN _=4.5V 


V CEX = 12V 


MIL grade 


100 


100 


200 


„A 


V CEX = 5.25 V 


COM'L grade 


'sc 




Output Short Circuit 
Current 


V cc = MAX 
V OUT = 0V 
V IN+ = +0.8V 

v IN _ = ov 


MIL grade 


-15 -80 


-15 -39 -80 


-15 -80 


mA 


COM'L grade 


-14 -100 


-14 -39 -100 


-14 -100 


V 




Input Load Current 


V cc - MAX 

V| N = V OL maX 1 other input = V cc 


-0.9 


-0.49 -0.7 


-0.7 


mA 


'|L(ST| 




Strobe Input Low 
Current 


V cc = MAX V IN+ = + 2.0V 
V ST = V OL MAX V IN _ =0V 


-2.4 


-1.15 -2.4 


—2.4 


mA 


'|L|RC| 




Response Control Input 
Load Current 


V CC = MAX V IN+ = +2.0V 
V RC = V OL MAX V IN _ = 0V 




-1.2 -3.4 




mA 


^CM 


Common Mode Voltage 


V CC = 5.0V V IN+ -V IN _ =0.4 or 2.4 V 


-15 +15 


-15 ±17.5 +15 


-15 +15 


V 


'iHisri 




Strobe Input HIGH 
Current 


Vcc = MIN 
V ST = 4.5 V 
V, N+ = +0-8 V 
V| N - = o V 


MIL grade 




2.0 


5.0 


(* 


COM'L grade 




5.0 


10.0 


"in 




Input Resistor 


V cc = 5.0 V 

v, N+ = ov 

V RES =1.0V 


MIL grade 




77 130 167 




52 


COM'L grade 




74 130 179 




Vth 




Differential Input 
Threshold Voltage 


V cu = V 


+0.8 +2.0 


+0.8 +1.5 +2.0 


+0.8 +2.0 


V 


'cc 




Power Supply Current 


V cc = MAX 
V IN+ = +2.0V 

v IN _ = ov 


MIL grade 


50 


28.7 50 


50 


mA 


COM'L grade 


50 


28.7 50 


50 



Switching Characteristics tj A 

Parameters 



Test Conditions 



Min 



Am2615XM 

Typ Max 



Min 



Am2615XC 

Typ Max Units 



t pd+ Turn Off Delay R L = 3.9 kSl 


V cc = 5.0 V, C L = 30 pF 
Refer to figure 4 


30 50 


30 75 


ns 


tpj_ Turn On Delay R L — 390 f2 


30 50 


30 75 


•p<i+ Turn 0,f Delay Strobe to Output 


R L = 3.9 kSl, C L = 30 pF 


7 12 


7 15 


ns 


tpd_ Turn On Delay Strobe to Output 


R L = 390 £2 


10 15 


10 20 



4-73 



Am2615/9615 



Am9615 ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE 



Parameters Description 



V cc = 4.5V to 5.5V 
V cc = 4.75V to 5.25V 



T A = -55 C to + 125 C 
T A - 0°C to +75°C 



Test Conditions 



(MIL grade) 
(COM'L grade) 



LIMITS 

: Min T A = 25°C T A = Max 
Max Min Typ Max Min Max 



Units 



V OH 


Output HIGH Voltage 


V CC = MIN, l OH = -5.0 mA 
V IN+ = -0.5V, V IN _=0V 


2.4 


2.4 3.2 


2.4 


Volts 


Vol 


Output LOW Voltage 


V cc = MAX 

'oh = 15 mA 

V IN+ = +0.5V, V IN _ = 


Ml L grade 


0.40 


.18 0.40 0.40 


Volts 


COM'L grade 


0.45 


.25 0.45 


0.45 


'ceX 


Output Leakage Current 


V cc = MIN 

v iN+ - o V 
v, N _ = v cc 


V CEX =12V 


M I L grade 


100 


1 nn 
I uu 


200 


■* 


V CEX = 5.25 V 


COM'L grade 


Uc 


Output Short Circuit 
Current 


V cc = MAX 

Vout = V 
V, N+ = -0.5 V 

v IN - = ov 


M I L grade 


— 1 5 — 80 


-15 -39 -80 


-15 -80 


mA 


COM'L grade 


-14 -100 


-14 -39 -100 


-14 -100 


'|L 


Input Load Current 


V cc = MAX 

V| N = V OL max. otner i n P ut = v cc 


-0.9 


-0.49 -0.7 


-0.7 


mA 


'lL(ST) 


Strobe Input Low 
Current 


V cc = MAX V IN+ = +0.5V 

V ST = V LMAX V |N _=0V 


-2.4 


-1.15 -2.4 


—2.4 


mA 




Response Control Input 
Load Current 


V cc = MAX V IN | = +0.5 V 

v RC = v OLMAX V IN _ = 0V 




-1.2 -3.4 




mA 


— 


Common Mode Voltage 


V CC = 5.0V V IN+ -V IN _ = ±2.0V 


-15 +15 


-15 ±17.5 +15 


-15 +15 


V 


'lH[ST| 


Strobe Input HIGH 
Current 


V cc = MIN 
V ST =i4.5V 
V IN+ =-0.5V 

v IN _ = V 


MIL grade 




2.0 


5.0 


fA 


COM'L grade 




5.0 


10.0 


"in 


Input Resistor 


V cc = 5.0 V 

v, N+ = ov 

V RES = 1.0V 


MIL grade 




77 130 167 




S2 


COM'L grade 




74 130 179 




V IH 


Differential Input 
Threshold Voltage 


V C m = 0V 


-0.5 +0.5 


-0.5 ±0.02 +0.5 1 -0.5 +0.5 


V 


'cc 


Power Supply Current 


V cc = MAX 
V, N+ = +0.5 V 

v, N - = ov 


MIL grade 


50 


28.7 50 


50 




COM'L grade 


50 


28.7 50 


50 


mA 



Switching Characteristics it, = 25°o 

Parameters 



Test Conditions 



Min 



Am9615XM 

Typ Max 



Min 



Am9615XC 

Typ Max Units 



W Turn 0ff Dela y r l = 3 - 9 kn 


V CC = 5.0V, C L = 30pF 
Refer to figure 4 


30 50 


30 75 


ns 


\ pd _ Turn On Delay R L = 390 SI 


30 50 


30 75 


«pd+ Turn c 


ff Delay Strobe to Output 


R L = 3.9 kS2, C L = 30 pF 


7 12 


7 15 


ns 


t p(S _ Turn 


n Delay Strobe to Output 


R L = 390 a 


10 15 


10 20 



4-74 



Am2615/9615 



D. C. CHARACTERISTICS 



Output Low Voltage 

Versus 
Output Low Current 




5 10 15 20 

- OUTPUT LOW CURRENT - mA 



Output High Voltage 

Versus 
Output High Current 

















T A - 25-C 
























































X. ' 


5.5 










































u 






















5.0 














C - 
















1 1 













-10 -20 -30 -40 -50 
l 0H -OUTPUT HIGH CURRENT - mA 



Output Voltage Versus 
Ambient Temperature 



























v c 


■I 


V CC - 4.5V 

'OH " -5.0 mA 

V DIFF " 
III! 




















y 


( v ar 46V 

11 In, . 15 mA 
















Fr 


= -0 


5 V 































































-60-40-20 20 40 60 80 100120140 
T. - AMBIENT TEMPERATURE - X 



Strobe Input-Output 
Transfer Characteristic 
Versus V rr 













T A -25'C 










-5. 
•5 


iV 
0V- 






r 

"nr.-* 


V 













































Strobe Input-Output 
Transfer Characteristic 
Versus Ambient 1 



>° o 













V CC = 5.0V 










r A- 


125"C 
25- C 










b 


T . = -FiRT" i 








-A 























































- STROBE INPUT VOLTAGE - VOLTS 



1 2 3 

INPUT VOLTAGE - VOLTS 



Output Voltage Versus Common 
Mode Voltage (Am9615) 




2Z 



-25-20-15-10 -5 5 10 15 20 25 
VCM~ COMMON MODE VOLTAGE - VOLTS 



Input Current Versus 
Input Voltage 



v cc" 


5.0V 1 








UNTESTED INPUT = OV 










^ = 25' C 



































































































































































































-25-20-15-10 -5 5 10 15 20 25 
V |N - INPUT VOLTAGE - VOLTS 



Power Supply Current 

Versus 
Power Supply Voltage 















25 C 




+ 


NPL1T 


s-v 


DC 






_ ON 


IY 


"■/PUT 


5 = 


\ 






WITH 
ACTIVE N 












PUL 


L-UP 


N 
- + 


1 




K 










1/ 
















-INPUTS = 
1 


:>. - 





v cc- 



1 2 3 4 5 6 7 
POWER SUPPLY VOLTAGE -- VOLTS 



Power Supply Current 

Versus 
Ambient Temperature 



.INPUT - V cc 
-INPUT = OV 



20 
10 


-60-40-20 20 40 60 80 100 120 140 
T. - AMBIENT TEMPERATURE - "C 



Switching Time 
Versus 
Ambient Temperature 




-60-40-20 20 40 60 80 100 120140 
T A - AMBIENT TEMPERATURE -"C 



4-75 



Am2615/9615 



Input-Output 
Characteristic 
Versus W C r, 









- T A = 25-C 
















I 

^ V CC" 55V 
M -Rnv 










' tt 

v cc 


- 4.5 


V 






i 


It 

























2 3 
INPUT VOLTAGE - VOLTS 



INPU 



THRESHOLD CHARACTERISTICS 



Am2615 



Input-Output Transfer 

Characteristic 
Versus Temperature 



V CC .5.0V 




V CC I 

V... i2 
































A --55-C 












A -125'C 





































12 3 4 

INPUT VOLTAGE — VOLTS 



Am9615 



Input-Output Transfer 
Characteristic 
Versus V cc 



o 

-0.05 





"\ - T A -25'C 




I I 
V cc = 5.5V 

1_ v cc = s nv 
-^ V C C -4.SV 


< 


- . 1 



0.00 0.05 0.10 
- INPUT VOLTAGE - VI 



Input-Output Transfer 

Characteristic 
Versus Temperature 



V cc = 5.0V 












































T 


A --55'C 

. = 25°C 














A -125-C 










>* 



























V IN - INPUT VOLTAGE — VOLTS 



SWITCHING TIME TEST CIRCUIT & WAVEFORMS 



1PIN 4 OR 121 
CAPACITANCE 
<5pF 



V CC 




F 



3 



■USE V, N OR V, 
GROUND OTHER INPUT. 1 



■ +3.0V 

■ o.ov 

■ -3.0V 

■ *3.0V 

- O.OV 

- -3.0V 



Figure 4 



FREQUENCY RESPONSE CONTROL 



Am2615/9615 LOADING RULES 



Input 



Fanout 




Frequency Response 
Versus Capacitance 




CAPACITANCE - «F 



Input/ Output 


Pin 
No.'s 


Unit 
Load 


Output 
HIGH 


Output 
LOW 


Out 


1 




o/c 


10 


Active Pull-Up 


2 




83 




Response Control 


3 








Strobe 


4 


1.5 






+ In 


5 


0.5 






130 n 


6 








- In 


7 


0.5 






GND 


8 








- In 


9 


0.5 






130 12 


10 








+ In 


11 


0.5 






Response Control 


12 








Strobe 


13 


1.5 






Active Pull-Up 


14 




83 




Out 


15 




o/c 


10 


Vcc 


16 









4-76 



Am2615/9615 



Am2615 STANDARD USAGE 

Single-Ended-Back Matched Operation 
With Common Ground 



Vz Am2614 



Am2615 




Am9615 STANDARD USAGE 
Differential Operation 



Am9614 



Vz Am9615 



' ^ 1 INPUT STROBE 



Photograph of an Am9615 
switching differential data in 
the presence of high common 
mode noise. 



Vertical = 2.0 V/Div. Horizontal = 50 ns/Div. 



mimi*:' fat 




OUT A 




lliilli 




il . siaii , ni 



Metallization and Pad Layout 




10 13012 B 
9 -INPUTS 



4-77 



Am2616 



Quad MIL-188C and RS-232C Line Driver 



Distinctive Characteristics 

• Conforms to EIA RS-232C, CCITT V.24 and 
MIL-188C specifications 

• Short circuit protected output 

• Internal slew rate limiting 



• Supply independent output swing 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 

• TTL/DTL compatible input 



FUNCTIONAL DESCRIPTION 

The Am2616 is a quad line driver specifically designed to meet the 
EIA RS-232C, CCITT V.24 and MIL-188C interface requirements. 
Each driver accepts DTL/TTL logic levels and converts them to the 
requisite levels for data transmission between equipment. The output 
slew rate of each driver is internally limited, but can be lowered 
by an external capacitor. All outputs are short circuit protected, and 
protected against fault conditions specified in RS-232C. A HIGH 
logic level on the inhibit input forces the driver output to Vql or 
mark state. For 188C interface the output impedance is guaranteed 
to be less than 100 ohms and the positive and negative output 
voltage amplitudes are guaranteed to be within 10 percent of 
each other. 



INPUT A 2 
INHIBIT A 



LOGIC SYMBOL 

j 

Zr=D-j =£>^ 



O- 



LIC-411 INHIBIT D - 



V EE = Pin 9 
V cc = Pin 16 
GND - Pin 8 



CIRCUIT DIAGRAM 
(One Driver Shown) 




ORDERING INFORMATION 



Package Temperature 
Type Range 



Order 
Number 



Hermetic DIP 
Molded DIP 

Dice 
Hermetic DIP 
Flat Pack 
Dice 



Cto +75 C 
0°C to +75° C 
0°C to +75° C 
-55°Cto+125°C 
-55°C to +125°C 
-55°Cto+125°C 



AM2616DC 
AM2616PC 
AM2616XC 
AM2616DM 
AM2616FM 
AM2616XM 



CONNECTION DIAGRAM 
Top View 



INPUT A, 
INPUT A 2 C 
INHIBIT A 
OUTPUT A Q 
INPUT BE 
INHIBIT BQ 
OUTPUT Bf^ 
GND 



]V C C 



15 □ INPUT 
14 ^~ J INHIBIT D 
13 ~ J OUTPUT D 
12 ~ ] INPUT C 
11 ^JlNHIBITC 
10 ^OUTPUT C 

H vff 



Note: Pin 1 is marked for orientation. 



4-78 



Am2616 

MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65 C to +150 C 



Temperature (Ambient) Under Bias 



-55 Cto +125 C 



Supply Vo tage to Ground Potential 

Vcc 
V EE 



+15V 
-15V 



DC Voltage Applied to Outputs 







t15 V 



DC Input Voltage 



-1.5 V to +6V 



Lead Temperature (Soldering, 30 sec.) 



300" C 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) 

V CC = +12 v * 10% . V EE = -12 V ± 10%, R L -3 k!l unless otherwise noted 



(COM'L) T A - C to + 75 C 
(MIL) T A = -55°C to + 125°C 



Typ. 



Parameters 


Description 


Test Conditions 


Min. 


(Note 1) 


Max. 


Units 


V H 




Output HIGH Voltage (Note 2) 


V| Nl =V,n 2 = V inhib , t =0.8V 


+5.0 


+6.0 


+7.0 


Volts 


Vol 




Output LOW Voltage (Note 2) 


V|N 1 =V|N 2 = V| NH , B | T -2.0V 




- 6 ° 


-5.0 


Volts 


V,h 




Input HIGH Level 


Guaranteed input logical HIGH voltage 








Volts 


V,L 




Input LOW Level 


Guaranteed input logical LOW voltage 






0.8 


Volts 


1 1 1_ 




Input LOW Current 


Vin, =V| N2 = 0.4VorV| NH | B , T =0.4V 




-1.2 


-1 .6 


mA 


I.H 




Input HIGH Current 


V,N, =V| N2 = 2.4 V or V INH |BIT= 2.4 V 






40 


MA 


'sc 




Output Short Circuit Current (Positive) 
(Note 3) 


R L = on 

V| N , °r V,N 2 = V| NH | B |T = 0.8V 


-10 


-17 


-30 


mA 


l S E 




Output Short Circuit Current (Negative) 
(Note 3) 


R L = on 

Vin-, °r V|n 2 = Vinhibit = 2.0 V 


+ 10 


+17 


+30 


mA 


'cc 




Total Positive Supply Current 


V !Nl =V| N2 = v inhibix = 0.8V 




19 


28 


mA 




V|N, = V lN 2 = V, NH IBIT = 2.0 V 




9.5 


17 




Iee 




Total Negative Supply Current 


Vin, = v lN2 = Vinhibit = 0.8 v 







-2 


mA 




V|N, =V,n 2 = V INH IBIT = 2.0V 




-20 


-30 





Notes: 1. Typical values are at V cc = 12 V, V EE - -12 V, T A = 25 C. 

2. Vqh and Vql are guaranteed to be equal within ±10 percent of each other for Ml L-1 88C operation. (i.e., Vqh = 6.0V then Vq[_ - 

3. The Isc and ls E minimum limits guarantee the output impedance to be less than 1 00 ohms. 



-6.0V +0.6V). 



Switching Characteristics (Ta = 25°C, Vcc = +12.0V, Vee = -12.0 V) 



Parameters 


Description 


Test Conditions 


Min. 


Typ. 


Max. 


Units 


«PLH 


Delay from Input LOW to Output HIGH 


C L = 15 pF, R L = 00 




320 


650 


ns 


'PHL 


Delay from Input HIGH to Output LOW 




320 




ns 


dV/dt l+) 


Positive Slew Rate 


OpF < C L < 2500 pF, R u > 3 kfi 


4.0 


15 


30 


V/us 


dV/dt(-) 


Negative Slew Rate 


-30 


-15 


-4.0 


V/„s 



4-79 



Am2616 



TYPICAL CHARACTERISTICS 



Transfer Characteristics 



Output Slew Rate 
versus Load Capacitance 



I I I 

V CC = +12V 
















E = 


-1 

















































































































































0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 
Vj n - INPUT VOLTAGE - VOLTS 




100 1000 10,000 

Cl - CAPACITANCE - pF 



>3k£l 



Short-Circuit Output Current 
versus Temperature 



: Maximum Operating Temperature 
! versus Power-Supply Voltage 































\ 




'■'in 
«L 


= OPEN 
= 3k£2 




















a 
















b 


z 




















a. HthMt i it, me 

b. FLAT PACK 100 FT/MIN. 
AIRFLOW 

c. FLAT PACK 

AND MOLDED DIP 
STILL AIR 















T A - AMBIENT TEMPERATURE - °C 



-55 -35-15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE -°C 



DEFINITION OF TERMS 



FUNCTIONAL TERMS 

RS-232C A specification of the Electronic Industries Association 
that defines the electrical characteristics of data signals trans- 
mitted between two pieces of digital equipment. 
R L Load resistance. The DC resistance between the driver output 
and ground. 



MIL-188C A Military specification that defines the electrical 
interface and characteristics of data signals transmitted between 
two pieces of digital equipment. 

CCITT V.24 A European specification similar to the MIL-188C 
and RS-232 specifications. 



4-80 



Am2616 



SWITCHING TEST CIRCUIT & VOLTAGE WAVEFORMS 



I I . INPUT 1 

-HI O- 



V INHIBIT 

-lit INHIBIT 

H -O 



Note: Omit V ]N2 for channels B, C and D. 



+3.0V - 
INPUT - 

ov - 







/ 


IPHL — 




\ 




tpLH — 











Pulse Generator Rise Time = 10 ± 5ns. 



Metallization and Pad Layout 




DIE SIZE 
0.069" X 0.103" 



4-81 



Am2617 

Quad RS-232C Line Receiver 



Distinctive 



• Full military temperature range 

• Compatible with EIA specification RS-232C 

• Input signal range ± 30 volts 



• Guaranteed input thresholds over full military tem- 
perature range 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 

• Includes response control input and built-in hysterisis 



FUNCTIONAL DESCRIPTION 

The Am2617 is a quad line receiver whose electrical characteristics 
conform to EIA specification RS-232C. Each receiver has a single 
data input that can accept signal swings of up to + 30V. The output 
of each receiver is TTL/DTL compatible, and includes a 2kn resistor 
pull-up to Vcc- An internal feedback resistor causes the input to 
exhibit hysterisis so that AC noise immunity is maintained at a high 
level even near the switching thresholds. For example, at 25°C when 
a receiver is in a LOW state on the output, the input may drop as 
LOW as 1.25 volts without affecting the output. The device is 
guaranteed to switch to the HIGH state when the input voltage is 
below 0.75V. Once the output has switched to the HIGH state, the 
input may rise to 1 ,75V without causing a change in the output. The 
Am2617 is guaranteed to switch to a LOW output when its input 
reaches 2.25V. Because of this hysterisis in switching thresholds, 
the device can receive signals with superimposed noise or with slow 
rise and fall times without generating oscillations on the output. The 
threshold levels may be offset by a constant voltage by applying a 
DC bias to the response control input. A capacitor added to the 
response control input will reduce the frequency response of the 
receiver for applications in the presence of high frequency noise 
spikes. The companion line driver is the Am2616. 



LOGIC SYMBOL 



IN A ■ 

R.C A ■ 

IN B 
R.C. B 

INC ■ 
R.C. C ■ 



9~ 



9~ 



9~ 



V cc = Pin 14 
GND = Pin 7 



CIRCUIT DIAGRAM 
(One Receiver) 



I NPUT O VvV- 



2kSJ 



— *- 



ORDERING INFORMATION 



Temperature 
Range 



Order 
Number 



Molded DIP 
Hermetic DIP 

Dice 
Hermetic DIP 

in. 

Dice 



C to +75 C 
0°C to +75° C 
0°C to +75°C 
-55°Cto+125°C 
-55°Cto+125°C 
-55°Cto +125°C 



AM2617PC 
AM2617DC 
AM2617XC 
AM2617DM 
AM2617FM 
AM2617XM 



CONNECTION DIAGRAM 
Top View 



A IN [ 1* 

A R.C. Q 2 

A OUT Q 3 

b in rj 4 

B B.C. \2 5 

B OUT Q 6 

GND Q 7 



!« □ VCC 
13 IN 

12 □ D R.C. 

11 ^ D OUT 

10 ^ C IN 

9 ^ C R.C. 

8 ^ C OUT 



Note: Pin 1 is marked for orientation. 



4-82 



Am2617 

MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65 Cto+175"C 



Temperature (Ambient) Under Bias 



-55 Cto +125 C 



Supply Voltage to Ground Potential (Pin 14 to Pin 7) Continuous 



-0.5 V to +10 V 



DC Voltage Applied to Outputs for High Output State 
Input Signal Range 



Output Current, Into Outputs 



-0.5 V to +Vcc max. 
-30 V to +30 V 
30 mA 



DC Input Current 



Defined by Input Voltage Limits 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) 



T A = 0°C to +75° C V CC =5.0V±5% 
T A - -55°C to +125° C V CC = 5.0V+10% 



J Response control pin open. 



Parameters 


Description 


Test Conditions 


Min. 


Typ. 

(Note 1) 


Max. 


Units 


V H 




Output HIGH Voltage 


'OH = — °-5 mA, V||\j = 0.4 V or open 


2.4 


4.0 




Volts 


vol 




Output LOW Voltage 


Iql " 10 rnA, V|N = 3.0 V 




0.2 


0.45 


Volts 


IlL 




Input LOW Current 


V| N = -3.0V 


-0.43 






mA 




V| N = -2SV 


-3.6 




-8.3 


•|H 




Input HIGH Current 


V| N = +3.0V 


0.43 






mA 




V, N =+25 V 






8.3 


isc 




Output Short Circuit Current 


V IN = 0.0 V, V O UT=0.0V 


_JJ 






mA 


ice 




Power Supply Current 


V C C " MAX. 




20 


26 


mA 



Note 1 . Typical Limits are at VqO = 5 -0 v . 25° C ambient and maximum loading. 



Threshold Characteristics (Note 2) 
Parameters 



Test Conditions 



Min. 



Typ. 

(Note 1) 



Max. 



Units 



v T + 




Positive-Going Threshold Voltage 


Vql = 0.45V, V C C = 5.0V 


-55° C 


2.3 




3.1 


Volts 


c 


1.9 




2.5 


25° C 


1.75 


2.0 


2.25 


75° C 


1.45 




1.90 


125°C 


1.20 




1.65 


v-r- 




Negative-Going Threshold Voltage 


V H ■ 2.5V, V C C * 5.0V 


-55 C 


0.85 




1.65 


Volts 


o°c 


0.75 




1.40 


25° C 


0.75 


0.95 


1.25 


75° C 


0.60 




1.10 


125°C 


0.50 




0.95 



Notes: 1. Typical Limits are at Vqq = 5.0V, 25°C ambient and maximum loading. 

2. The input threshold margin for the device is greater than the voltage computed as the V-p + — V T _ value. For the minimum value s 
threshold margin versus temperature graph. 



3 the input 



Switching Characteristics (Ta = 25°C, response control pin open, C|_ = 15 pF) 



Parameters 


Description 


Test Conditions 


Min. 


Typ. 


Max. 


Units 


»PLH 


Delay from Input LOW to Output HIGH 


R[_ = 3.9 kSTl 




25 


85 


ns 


<PHL 


Delay from Input HIGH to Output LOW 


R l = 390 n 




25 


50 


ns 


tr 


Output Rise Time (10% to 90%) 


R[_ = 3.9 kf! 




120 


175 


ns 


tf 


Output Fall Time (90% to 10%) 


R[_ = 390 a 




10 


20 


ns 



Am2617 



TYPICAL CHARACTERISTICS 



Input Current 



Input Threshold 
Voltage Adjustment 






10 




8.0 


< 




E 


6.0 


h 


4.0 


Z 




cc 


2.0 


(C 




=> 
o 







-2.0 








-4.0 


I 


-6.0 




-8.0 




-10 



T A = 25°C 





































































































































































































V CC " 5. 
T A = 25" 


IV 












c 
































R l 

-5k 
■ v t 
+5 






























H T 

IlkP. 

V,h 

-5V 




n 

h - 












V 




















































































































X 



-25 -15 -5.0 5.0 15 

- INPUT VOLTAGE — VOLTS 



-3.0-2.0-1.0 1.0 2.0 3.0 4.0 5.0 
V in - INPUT VOLTAGE - VOLTS 



Input Threshold Versus 
Power-Supply Voltage 



Input Threshold Voltage 
Versus Temperature 



Input Threshold Margin 
Versus Temperature 

















VT+ 














































V- 


■- 










— 


— 












































V CC - 5.0V 








































































to. 











































































4.0 8.0 12 

V CC - POWER SUPPLY VOLTAGE - VOLTS 



-55-35-15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - 'C 



-55 -35 -15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - °C 



DEFINITION OF TERMS 
FUNCTIONAL TERMS 

Response Control Pin A pin available on each receiver that allows 
the user to set the switching thresholds and frequency response of 
the receiver. 

Threshold Voltage The voltage level on the input that will cause 
the output to change state. Because the device exhibits hysterisis, 
the LOW level input threshold is different from the HIGH level 



input threshold. Both thresholds can be moved by applying a bias 
to the response control pin. 

RS-232C A specification of the Electronic Industries Association 
that defines the electrical characteristics of data signals trans- 
mitted between two pieces of digital equipment. 

Input Signal Range The permitted range of DC voltages that can 
be applied to the receiver input without damage to the device. 



4-84 



Am2617 



SWITCHING TIME TEST CIRCUIT & WAVEFORMS 




LIC-421 



LIC-422 



Metallization and Pad Layout 

A IN VCC D IN 




6 7 8 
8 OUT GNOC OUT 



DIE SIZE 0.047" X 0.059" 



4-85 



Am2905 



Quad Two-Input OC Bus Transceiver With Three-State Receiver 



Distinctive Characteristics 

• Quad high-speed LSI bus-transceiver 

• Open-collector bus driver 

• Two-port input to D-type register on driver 

• Bus driver output can sink 100 mA at 0.8V max. 



• Receiver has output latch for pipeline operation 

• Three-state receiver outputs sink 12 mA 

• Advanced low-power Schottky processing 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 



FUNCTIONAL DESCRIPTION 

The Am2905 is a high-performance, low-power Schottky 
bus transceiver intended for bipolar or WIOS microprocessor 
system applications. The device consists of four D-type 
edge-triggered flip-flops with a built-in two-input multi- 
plexer on each. The flip-flop outputs are connected to four 
open-collector bus drivers. Each bus driver is internally con- 
nected to one input of a differential amplifier in the receiver. 
The four receiver differential amplifier outputs drive four 
D-type latches that feature three-state outputs. 

This LSI bus transceiver is fabricated using advanced low- 
power Schottky processing. All inputs (except the BUS in- 
puts) are one LS unit load. The open-collector bus output 
can sink up to 100 mA at 0.8V maximum. The BUS input 
differential amplifier contains disconnect protection diodes 
such that the bus is fail-safe when power is not applied. The 
bus enable input (BE) is used to force the driver outputs to 
the high-impedance state. When BE is HIGH, the driver is 
disabled. The open-collector structure of the driver allows 
wired-OR operations to be performed on the bus. 
The input register consists of four D-type flip-flops with a 
buffered common clock and a two-input multiplexer at the 
input of each flip-flop. A common select input (S) controls 
the four multiplexers. When S is LOW, the Aj data is stored 
in the register and when S is HIGH, the Bj data is stored. 
The buffered common clock (DRCP) enters the data into 
this driver register on the LOW-to-HIGH transition. 

Data from the A or B inputs is inverted at the BUS output. 
Likewise, data at the BUS input is inverted at the receiver 
output. Thus, data is non-inverted from driver input to 
receiver output. The four receivers each feature a built-in 
D-type latch that is controlled from the buffered receiver 
latch enable (RLE) input. When the RLE input is LOW, the 
latch is open and the receiver outputs will follow the bus 
inputs (BUS data inverted and OE LOW). When the RLE 
input is HIGH, the latch will close and retain the present 
data regardless of the bus input. The four latches have three- 
state outputs and are controlled by a buffered common 
three-state control (OE) input. When OE is HIGH, the 
receiver outputs are in the high-impedance state. 



LOGIC SYMBOL 



A B Q A, B, A 2 B 2 A 3 B 3 



BUS BUS, BUS 2 BUS 3 



f f t t 



V cc = Pin 24 
GND, = Pin 6 
GND 2 = Pin 18 



CONNECTION DIAGRAM 
Top View 



RLE | 

"olZ 

BUS„ Q 
GND 1 
BUS, 
A l IZ 

»iIZ 



Zl v cc 

I ORCP 
Zl»3 
Zl B 3 

6Ds 3 

| GND 2 
| BUS 2 

ZI A 2 

ZI B 2 

LZi R 2 



Note: Pin 1 is marked for orientation. 



4-86 



Am2905 



LOGIC DIAGRAM 



A o o 




BUS BUS] BUSj BUS3 

9 9 9 9 



-£> — ° ° 



-O R 



-o»i 



^{Z—o»: 



-3- 



RECEIVER 

-O RLE LATCH 
ENABLE 



MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



rati 



-65 Cto +150 C 



Temperature (Ambient) Under Bias 



-55 Cto +125 C 



Supply Voltage to Ground Potential 



-0.5V to +7V 



DC Voltage Applied to Outputs for HIGH Output State 



-0.5V to +V CC max. 



DC Input Voltage 



-0.5V to +7V 



DC Output Current, Into 
DC Output Current, Into 



(E> 



30mA 



200 mA 



DC Input Current 



-30 mA to +5.0mA 



ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 



Am2905XC (COM'L) T A ■ 
Am2905XM (MIL) T A ■ 



C to +70 C 



V CC MIN. - 4.75V V CC MAX. = 5.25 V 
-55"C to +125" C V CC MIN. - 4.50 V V cc MAX. = 5.50 V 



BUS INPUT/OUTPUT CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

Parameters Description Test Conditions (Note 1) Min 



Typ. 

(Note 2) 



Max. 



Units 











'OL 40mA 




0.32 


0.5 




vol 


Bus Output LOW Voltage 


V CC - MIN. 


Iql = 70mA 




0.41 


0.7 


Volts 








Iql = 100 mA 




0.55 


0.8 










V = 0.4V 






-50 




'0 


Bus Leakage Current 


V CC « MAX. 


V = 4.5V 


MIL 






200 


MA 








COM'L 






100 




'OFF 


Bus Leakage Current 
(Power OFF) 


V - 4.5V 






100 


MA 


VjH 




Receiver Input HIGH 


Bus enobie - 2.4V 


MIL 


2.4 


2.0 




Volts 




Threshold 


COM'L 


2.3 


2.0 




VTL 




Receiver Input LOW 


Bus enable = 2.4V 


MIL 




2.0 


1.5 


Volts 




Threshold 


COM'L 




2.0 


1.6 



4-87 



The following 
Am2905XC I 
Am2905XM 



Ml 



Am2905 



ELECTRICAL CHARACTERISTICS 



conditions apply unless otherwise noted: 



COM'LI 
L) 



Ta- 
ta - 



C to +70 C 



= 4.75 V V CC MAX. - 5.25 V 



55 C to +125 C V CC MIN. = 4.50 V V cc MAX .- 5.50 V 

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Parameters 


Description 


Test Conditions (Note 1) 




Min. 


Typ. 

(Note 2) 


Max. 


Units 


V H 




Receiver Output 


V CC = V IN 


MIL, Iqh " -1.0mA 


2.4 


3.4 




Volts 




HIGH Voltage 


V, N =V| L orV| H 


COM'L, Iqh = 


-2.6 mA 


2.4 


3.4 








Receiver Output 


V cc = Ml N . 

V| N = V| L or V| H 


'OL 4mA 




0.27 


0.4 




vol 




Iql = 8mA 




0.32 


0.45 


Volts 






Iql = 12mA 




0.37 


0.5 




V|H 




Input HIGH Level 
(Except Bus) 


Guaranteed input logical HIGH 
for all inputs 


2.0 






Volts 


Vn 
I L 




Input LOW Level 


Guaranteed input logical LOW 


MIL 






0.7 


Volts 




(Except Bus) 


for all inputs 




COM'L 






0.8 


Vi 




Input Clamp Voltage 
(Except Bus) 


V CC = MIN., I IN =-18mA 






-1.5 


Volts 


1 1 1_ 




Input LOW Current 
(Except Bus) 


V cc = MAX., V| N = 0.4V 






-0.36 


mA 


"|H 




Input HIGH Current 
(Except Bus) 


V cc - MAX., V| N = 2.7V 






20 


K£ 


•l 




Input HIGH Current 
(Except Bus) 


V CC = MAX., V| N = 5.5V 






100 


M 


'0 




Receiver Off-State 


V CC = MAX. 


V - 2.4 V 






20 


mA 




Output Current 


V = 0.4 V 






-20 


'sc 




Receiver Output 
Short Circuit Current 


V CC = MAX. 


-12 




-65 


mA 


'cc 




Power Supply Current 


Vcc = MAX., All inputs = GND 




69 


105 


mA 



SWITCHING CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 











Am2905XM 


Am2905XC 




Parameters 




Description 


Test Conditions 


Min. 


Typ. 

(Note 2) 


Max. 


Min. 


Typ. 

(Note 2) 


Max. 


Units 


«PHL 




Driver Clock (DRCP) to Bus 






21 


40 




2 I 


36 


ns 


«PLH 




C L (BUS) = 50pF 




21 


40 




21 


36 


'PHL 




Bus Enable (BE) to Bus 


R L (BUS) = 500 




13 


26 




13 


23 


ns 


«PLH 








13 


26 




13 


23 


«s 




Data Inputs (A or B) 




25 






23 






ns 


«h 






8.0 






7.0 






«s 




Select input (S) 




33 






30 






ns 


<h 






8.0 






7.0 






t PW 




Driver Clock (DRCP) Pulse Width 
(HIGH) 




28 






25 






ns 


'PLH 




Bus to Receiver Output 






18 


37 




18 


34 


ns 


«PHL 




(Latch Enable) 


C L = 15pF 




18 


37 




18 


34 


«PLH 


Latch Enable to Receiver Output 


R[_ = 2.0kf2 




21 


37 




21 


34 


ns 


«PHL 






21 


37 




21 


34 


«s 


Bus to Latch Enable (RLE) 




21 






18 






ns 


th 




7.0 






5.0 






tZH 


Output Control to Receiver Output 






14 


28 




14 


25 


ns 


«ZL 






14 


28 




14 


25 


«HZ 




Output Control to Receiver Output 






14 


28 




14 


25 


ns 


«L2 








14 


28 




14 


25 



For conditions shown as MIN. or MAX., use the appropriate value specified under El 
Typical limits are at V^c = 5.0V, 25°C ambient and maximum loading. 
Not more than one output should be shorted at a time. Duration of the short circuit 



ectrical Characteristics for the applicable device type, 
test should not exceed one second. 



4-88 



Am2905 



INPUT/OUTPUT CURRENT 
INTERFACE CONDITIONS 



DRIVEN INPUT 



DRIVING OUTPUT 




Note: Actual current flow direction shown. 



TYPICAL PERFORMANCE CURVES 



Bus Output Low Voltage 
Versus Ambient Temperature 

1.0 



0.8 



V 


CC" 


1 

+5.0V 




































BUS 1 


]0m 


\ - 










l BUS -70mA 










-r- 












BUS 


-4 





























-55 -35 -15 5 25 45 65 85 105 125 
T. - AMBIENT TEMPERATURE - "C 



Receiver Threshold Variation 
Versus Ambient Temperature 



< 2.3 









































v C c" 5 - 5v 
















V cc - 5.25 V 






_ K 


< 




i I 

V CC = 4 - 75V 


cot 


It 




\ 
















v c 


; = 4 


5 V 

















































-55 -35 -15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - °C 



SWITCHING WAVEFORMS 



r 



MMM ^ 



1 



\ 



3.0 V 
1.3V 
0V 

V H 
2.0 V 



Note: Bus to Receiver output delay is measured by clocking data into the driver register 
and measuring the BUS to R combinatorial delay. 



4-89 



Am2905 

















INTERNAL 














INPUTS 






TO DEVICE 


BUS 


OUTPUT 


FUNCTION 


s 


A, 




DRCP 


BE 


RLE 


OE 


Dj 


Qi 


BUSj 


Ri 


X 


X 


> 


X 


H 




X 


X 


X 


Z 


X 


Driver output disable 


X 


X 


X 


X 


X 


X 


H 


X 


X 


X 


z 


Receiver output disable 


x 


X 


x 


x 


H 


L 


L 


X 


L 


L 


H 


Driver output disable and 


X 


X 


X 


X 


H 


L 


L 


X 


H 


H 


L 


receive data via Bus input 


X 


X 


X 


X 


X 


H 


X 


X 


NC 


X 


X 


Latch received data 


L 


L 


x 


t 


X 


X 


X 


L 


X 


X 


X 




L 


H 


X 


t 


X 


X 


X 


H 


X 


X 


X 


























Load driver register 


H 


X 


L 


T 


X 


X 


X 


L 


X 


X 


X 


H 


X 


H 


T 


X 


x 


X 


H 


X 


X 


X 




x 


X 


X 


L 


X 


X 


X 


NC 


X 


X 


X 


No driver clock restrictions 






















X 


X 


x 


H 


X 


X 


X 


NC 


X 


X 


X 




X 


X 


* 


X 


L 


X 


X 


L 


X 


H 


X 


























Drive Bus 


X 


» 


X 


X 


L 


X 


X 


H 


X 


L 


X 





FUNCTION TABLE 



H - 
L = 



HIGH 
LOW 



. HIGH 
NC - No 



^ Don't care i = 0, 1 , 2, 3 

• LOW to HIGH transition 



ORDERING INFORMATION 



Order the part number according to the table below to obtain the de- 
sired package, temperature range, and screening level. 



Screening 

Level 
(Note 3) 

C-1 
C-1 
B-1 
C-3 
B-3 
C-3 
B-3 

Visual inspection 
to MIL-STD-883 
Method 201 OB. 





Package 


Temperature 


Order 


Type 


Range 


Number 


(Note 1) 


(Note 2) 


AM2905PC 


P-24 


C 


AM2905DC 


D-24 


C 


AM2905DC-B 


D-24 


c 


AM2905DM 


D-24 


M 


AM2905DM-B 


D-24 


M 


AM2905FM 


F-24 


M 


AM2905FM-B 


F-24 


M 


AM2905XC 


Dice 




AM2905XM 


Dice 


M 



Notes 
1 



P = Molded DIP, D = Hermetic DIP, F = Flat Pak. Number follow- 
ing letter is number of leads. See Appendix B for detailed outline. 
Where Appendix B contains several dash numbers, any of the 
variations of the package may be used unless otherwise specified. 
C = 0°C to +70°C, M = -55°C to +125°C. 
See Appendix A for details of screening. Levels C-1 and C-3 con- 
form to MIL-STD-883, Class C. Level B-3 conforms to MIL-STD- 
883, Class B. 



DEFINITION OF FUNCTIONAL TERMS 

Ag, A^,A2, A3 The "A" word data input into the two 
input multiplexer of the driver register. 

Bg, B-|, B2, B3 The "B" word data input into the two 
input multiplexers of the driver register. 

Select. When the select input is LOW, the 
A data word is applied to the driver reg- 
ister. When the select input is HIGH, the 
B word is applied to the driver register. 

Driver Clock Pulse. Clock pulse for the 
driver register. 

Bus Enable. When the Bus Enable is HIGH, 
the four drivers are in the high impedance 
state. 



LOAD TEST CIRCUIT 



DRCP 
BE 

BOSq, BUSt 

bUs 2 , BUS3 
Ro> R1. R2. R3 

RLE 




OE 



The four driver outputs and receiver in- 
puts (data is inverted). 

The four receiver outputs. Data from the 
bus is inverted while data from the A or B 
inputs is non-inverted. 

Receiver Latch Enable. When RLE is 
LOW, data on the BUS inputs is passed 
through the receiver latches. When RLE 
is HIGH, the receiver latches are closed 
and will retain the data independent of 
all other inputs. 

Output Enable. When the OE input is 
HIGH, the four three state receiver out- 
puts are in the high-impedance state. 



Metallization and Pad Layout 




DIE SIZE 0.080" X 0.130" 



4-90 



Am2905 



APPLICATIONS 



ADDRESS 
AND 
DATA DISPLAY 



A CONTROL B 
ALU 
OUT 



CONTROL f" 
SCRATCHPAD 



B CONTROL 



B CONTROL 



B CONTROL 



The Am2905 is a universal Bus Transceiver useful for many system data, address, control and 
timing input/output interfaces. 



31 



_sz 




-7% 



Am2905 

~7V~ 



1Z 



Am26S10 



O 



TV 



SZ 



Am26S10 



1Z 



iz 



lZ 



iz 



Using the Am2905 and Am26S10 in a terminated Bus system for the Am9080 MOS Microprocessor. 



4-91 



Am2906 

Quad Two-Input OC Bus Transceiver With Parity 



Distinctive Characteristics 

• Quad high-speed LSI bus transceiver. 

• Open-co lector bus driver. 

• Two-port input to D-type register on driver. 

• Bus driver output can sink 100 mA at 0. 8V max. 

• Internal odd 4-bit parity checker/generator. 



• Receiver has output latch for pipeline operation. 

• Receiver outputs sink 12 mA. 

• Advanced low-power Schottky processing. 

• 100% reliability assurance testing in compliance with 
MIL-STD-883. 



FUNCT ONAL DESCRIPTION 



The 
bus 

system 
edge 
on each 
collector 
nected 
The 
D-type 
parity 



Am2906 is a high-performance, low-power Schottky 
transceiver intended for bipolar or MOS microprocessor 
applications. The device consists of four D-type 
triggered flip-flops with a built-in two-input multiplexer 
The flip-flop outputs are connected to four open- 
bus drivers. Each bus driver is internally con- 
one input of a differential amplifier in the receiver, 
receiver differential amplifier outputs drive four 
atches. The device also contains a four-bit odd 
checker/generator. 



to 
four 



This LSI bus transceiver is fabricated using advanced low- 
power Schottky processing. All inputs (except the BUS in- 
puts) are one LS unit load. The open-collector bus output 
can sink up to 100 mA at 0.8V maximum. The BUS input 
differential amplifier contains disconnect protection diodes 
such that the bus is fail-safe when power is not applied. The 
bus enable input (BE) is used to force the driver outputs to 
the high-impedance state. When BE is HIGH, the driver is 
disabled. The open-collector structure of the driver allows 
wired-OR operations to be performed on the bus. 

The input register consists of four D-type flip-flops with a 
buffered common clock and a two-input multiplexer at the 
input of each flip-flop. A common select input (S) controls 
the four multiplexers. When S is LOW, the A, data is stored 
in the register and when S is HIGH, the Bj data is stored. 
The buffered common clock (DRCP) enters the data into 
this driver register on the LOW-to-HIGH transition. 

Data from the A or B input is inverted at the BUS output. 
Likewise, data at the BUS input is inverted at the receiver 
output. Thus, data is non-inverted from driver input to 
receiver output. The four receivers each feature a built-in 
D-type latch that is controlled from the buffered receiver 
latch enable (RLE) input. When the RLE input is LOW, the 
latch is open and the receiver output s will follow the bus 
inputs (BUS data inverted). When the RLE input is HIGH, 
the latch will close and retain the present data regardless of 
the bus input. 

The Am2906 features a built-in four-bit odd parity checker/ 
generator. The bus enable input (BE) controls whether the 
parity output is in the generate or check mode. When the 
bus enable is LOW (driver enabled), odd parity is generated 
based on the A or B field data input to the driver register. 
When BE is HIGH, the parity output is determined by the 
four latch outputs of the receiver. Thus, if the driver is en- 
abled, parity is generated and if the driver is in the high- 
impedance state, the BUS parity is checked. 



LOGIC SYMBOL 



16 15 20 21 



*0 B A l B l A 2 B 2 A 3 



ODD 
"0 



RLE 

BUSq bus, bus? bus 3 



TTTT 



V cc = Pin 24 

GND, = Pin 6 
GND 2 « Pin 18 



CONNECTION DIAGRAM 
Top View 



RLE 1 


• 

1 


B oLZ 


2 


B |Z 


3 


AotZ 




BUS„ £2 


5 


GND, | 


6 


BUS, \2Z 




A,rz 


8 


B .LZ 


9 




10 


siq 


11 


ODD 


12 



24 


□ V CC 


23 


| DRCP 


22 


ZI R 3 


21 


Zl*3 


20 


Zl*3 


19 


— |bUs 3 


18 


| GND 2 


17 


□ bDs 2 


16 


□ *2 


15 




14 


□ "2 


13 


3? 



Note: Pin 1 is marked for orientation.- 



4-92 



Am2906 



LOGI 



C DIAGRAM 



, BUS, BUS 2 8US3 



A 2 O- 
BjO- 
A3 O- 



A 



A 



r 



t; 



t; 



rU 



I 1 Q i 

D Q — f-^O o«, 



- p0>O-°"2 





^<]-^ra °j! 



MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65 C to +150 C 



Temperature (Ambient) Under Bias 
Supply Voltage to Ground Potential 



-55 C to +125 C 



-0.5V to +7V 



DC Voltage Applied to Outputs for HIGH Output 



-0.5V to +V CC max. 



DC Input Voltage 



-0.5V to +5.5V 



DC Output Current, Into Outputs (Except Bus) 



30mA 



DC Output Current, Into Bus 



200 mA 



DC Input Current 



-30mA to +5.0mA 



ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 

Am2906XC (COM'L) T A = 0°C to +70° C V cc M I N. - 4.75V V cc MAX. - 5.25V 

Am2906XM (MIL) T A = -55° C to +1 25° C V cc Ml N. - 4.50V V cc MAX. = 5.50V 

BUS INPUT/OUTPUT CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Typ. 

Parameters Description Test Conditions (Note 1) Min. (Note 2) Max. Units. 



vol 


Bus Output LOW Voltage 




Iql = 40mA 




0.32 


0.5 


Volts 


lOL = 70mA 




0.41 


0.7 


Iql = 100mA 




0.55 


0.8 


to 


Bus Leakage Current 


V CC = MAX. 


V = 0.4V 






-50 


(lA 


V = 4.5V 


MIL 






200 


COM'L 






100 


'OFF 


Bus Leakage Current 
(Power OFF) 


V = 4.5V 






100 


MA 


V T H 


Receiver Input HIGH 
Threshold 


Bus enable = 2.4V 


MIL 


2.4 


2.0 




Volts 


COM'L 


2.3 


2.0 




V-TL 


Receiver Input LOW 
Threshold 


Bus enable = 2.4V 


MIL 




2.0 


1.5 


Volts 


COM'L 




2.0 


1 .6 



4-93 



Am2906 



ELECTRICAL CHARACTERISTICS 



The following conditions apply unless otherwise noted: 

Am2906XC ICOM'LI T A = 0° C to +70° C V cc M I N. - 4.75 V V cc MAX. = 5.25V 

Am2906XM (MIL) T A - -55° C to + 1 25° C V CC MIN.4.5V V cc MAX. = 5.5V 



DC CHARACTERISTICS 
Parameters 



OVER OPERATING TEMPERATURE RANGE 

Description Test Conditions (Note!) 



Min. 



Typ. 

(Note 2) 



Max. 



Units 



VOH 


1 


Receiver Output 
HIGH Voltage 


V CC = MIN. 
V| N -V| L or V| H 


MIL 


Iqh -— I«iA 


2.4 


3.4 




Volts 


COM'L 


l H = -2.6mA 




O.I 




1 

1 


'arity Output 
HIGH Voltage 


V CC - MIN., I H * -66G>A 
V|N = v IH° rV lL 


MIL 


2.5 


3.4 




COM'L 


2.7 


3.4 




Vol 


Output LOW Voltage 
(Except Bus) 


V C C = MIN. 

V| N = V| L or V| H 


'OL = 4mA 




0.27 


0.4 


Volts 


IfjL = 8m A 




32 


45 


Iql = 12mA 




0.37 


o.s 


V| H 


Input HIGH Level 
(Except Bus) 


Guaranteed input logical HIGH 
for all inputs 


2.0 






Volts 


V|L 


Input LOW Level 
(Except Bus) 


Guaranteed input logical LOW 
for all inputs 


MIL 






0.7 


Volts 


COM'L 






0.8 


V| 


Input Clamp Voltage 
(Except Bus) 


V cc = MIN., I| N = -18mA 






-1.2 


Volts 


l|L 




nput LOW Current 
Except Bus) 


V C C = MAX., V| N - 0.4V 






-0.36 


mA 


Urn 




nput HIGH Current 
Except Bus) 


V CC = MAX., V| N - 2.7V 






20 


MA 


k 




nput HIGH Current 
Except Bus) 


V CC = MAX., V, N =5.6V 








100 


uA 


isc 




Dutput Short Circuit Current 
Except Bus) 


V CC = MAX. 


-12 




-65 


mA 


ice 




Power Supply Current 


V CC = MAX., All inputs - GND 




72 


105 


mA 



SWITCHING CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Parameters 


Description Test Conditions 


Am2906XM 


Am2906XC 


Units 


Typ. 

Min. (Note 2) Max. 


Typ. 

Min. (Note 2) Max. 


tPHL 




Driver Clock (DRCP) to Bus 


C L (BUS) - 50pF 
R|_<BUS) = 500 




21 


40 




21 


36 


ns 


tPLH 




21 


40 




21 


36 


'PHL 




Bus Enable ('BE) to Bus 




13 


26 




13 


23 


ns 


tPLH 




13 


26 




13 


23 


»s 




Data Inputs (A or B) 


C L = 15pF 
R L = 2.0kS2 


25 






23 






ns 


«h 


8.0 






7.0 






«s 




Select Inputs (S) 


33 






30 






ns 


% 


8.0 






7.0 






tpw 




Clock Pulse Width (HIGH) 


28 






25 






ns 


'PLH 




Bus to Receiver Output 
(Latch Enabled) 




18 


37 




18 


34 


ns 


'PHL 




18 


37 




18 


34 


«PLH 








21 


37 




21 


34 


ns 


tPHL 


Ldlyll 1_1 laUIC IU MCLCIVCI l>JUt 




21 


37 




21 


34 


t S 


Bus to Latch Enable (RLE) 


21 






18 






ns 


th 


7.0 






5.0 






»PLH 


A or B Data to Odd Parity Output 
(Driver Enabled) 




21 


40 




21 


36 


ns 


'PHL 




21 


40 




21 


36 


tPLH 


Bus to Odd Parity Output 
(Driver Inhibited, Latch Enabled) 




21 


40 




21 


36 


ns 


»PHL 




21 


40 




21 


36 


tPLH 




Latch Enable (RLE) to 
Odd Parity Output 




21 


40 




21 


36 


ns 


«PHL 




21 


40 




21 


36 



Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type. 

2. Typical limits are at = 5.0V, 25°C ambient and maximum loading. 

3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 



4-94 



Am2906 



INPUT/OUTPUT CURRENT 
INTERFACE CONDITIONS 



DRIVEN INPUT 



DRIVING OUTPUT 




OR|. ODD 



Note: Actual current flow direction shown. 



TYPICAL PERFORMANCE CURVES 



Bus Output Low Voltage 
Versus Ambient Temperature 



l R llc = 100mA 



-55 - 35 -15 5 25 45 65 85 105 125 
T a - AMBIENT TEMPERATURE - °C 



Receiver Threshold Variation 
Versus Ambient Temperature 












































.5V 



















V cc = 5.25V 




. h 


< 




•■a 


1 1^ 

= 4.75 V 


COP 


ft ■ 






















v cc-" 


.5V 















































-55 -35-15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - °C 



RECEIVER 
OUTPUT 



SWITCHING WAVEFORMS 



3.0V 
1.3V 



"1 



h- 



3.0V 
1.3V 



\ 



2.0V 
U Ol 



1.3V 
Vol 



Note: Bus to Receiver output delay is measured by clocking data into the driver register 
and measuring the BUS to R combinatorial delay. 



4-95 



Am2906 



FUNCTION TABLE 



B, DRCP BE RLE OE 



H = 
L- 



HIGH 
LOW 



INTERNAL 
TO DEVICE 



Dj Q| 



BUSi 



Driver outpul disable 



Receiver output disable 



Driver output disable and 
receive data via Bus input 



Latch received data 



Load driver register 



r clock restrictions 



Z = HIGH Impedance 
NC - No change 



X- Don't care 1 = 0,1,2,3 

t - LOW to HIGH transition 



ORDERING INFORMATION 

Order the part number according to the table below to obtain the de- 
sired package, temperature range, and screening level. 



Order 
Number 



Package 

Type 
(Note 1) 



Temperature 
Range 
(Note 2) 



Screening 

Level 
(Note 3) 



AM2906PC 


P-24 


C 


C-1 


AM2906DC 


D-24 


C 


C-1 


AM2906DC-B 


D-24 


C 


B-1 


AM2906DM 


D-24 


M 


C-3 


AM2906DM-B 


D-24 


M 


B-3 


AM2906FM 


F-24 


M 


C-3 


AM2906FM-B 


F-24 


M 


B-3 


AM2906XC 
AM2906XM 


Dice 
Dice 


C 
M 


\ Visual inspection 
\ to MIL-STD-883 
) Method 201 OB. 



Notes 
1. 



P = Molded DIP, D = Hermetic DIP, F = Flat Pak. Number follow- 
ing letter is number of leads. See Appendix B for detailed outline. 
Where Appendix B contains several dash numbers, any of the 
variations of the package may be used unless otherwise specified. 
C = 0°C to +70°C, M = -55°C to +125°C. 
See Appendix A for details of screening. Levels C-1 and C-3 con- 
form to MIL-STD-883, Class C. Level B-3 conforms to MIL-STD- 
883, Class B. 



DEFINITION OF FUNCTIONAL TERMS 



LOAD TEST CIRCUIT 



Bo. B,, 



DRCP 
BE 



^2. A3 The "A" word data input into the two 
input multiplexer of the driver register. 

B 2. B 3 The "B" word data input into the two 
input multiplexers of the driver register. 

Select. When the select input is LOW, the 
A data word is applied to the driver reg- 
ister. When the select input is HIGH, the 
B word is applied to the driver register. 

Driver Clock Pulse. Clock pulse for the 
driver register. 

Bus Enable. When the Bus Enable is HIGH, 
the four drivers are in the high impedance 
state. 



O TEST 
POINT 



? u cc 



7 



>pF -|~ 



-M— 



50 Q 



BUS , bus 1 
BUS 2 , BUS3 

Ro. R1 



The four driver outputs and 
puts (data is inverted). 



r in- 



RLE 



OE 



R 2. R 3 The four receiver outputs. Data from the 
bus is inverted while data from the A or B 
inputs is non-inverted. 

Receiver Latch Enable. When RLE is 
LOW, data on the BUS inputs is p assed 
through the receiver latches. When RLE 
is HIGH, the receiver latches are closed 
and will retain the data independent of 
all other inputs. 

Output Enable. When the OE input is 
HIGH, the four three state receiver out- 
puts are in the high-impedance state. 



Metallization and Pad Layout 




DIE SIZE 0.080" X 0.130" 



4-96 



Am2906 



APPLICATIONS 




A 


B 


S 




DRCP 






Am2906 


BE 




RLE 




R 


ODD BUS 



1 



p l p 2 p 3 p 4 p 5 P 6 p 7 p 8 p 9 



DRCP 
-C BE 
RLE 



R ODD BUS 



3 



BUS PARITY 



ODD/EVEN 
" CONTROL 
L = EVEN 
H = ODD 



PARITY OUTPUT 



Generating or checking parity for 16 data bits. 



_sz 



O 



Am2906 



4\ 



iz 



Am2906 Am2906 Am26S10 



7T 



iz 



iz 



iz 



Z\Z 



3 



Using the Am2906 and Am26S10 in a terminated Bus system for the Am9080 MOS Microprocessor. 



Am2907»Am2908 

Quad Bus Transceivers with Interface Logic 



Distinctive Characteristics 

• Quad high-speed LSI bus-transceiver 

• Open-collector bus driver 

• D-type register on driver 

• Bus driver output can sink 1 00mA at 0.8V max. 

• Internal odd 4-bit parity checker/generator 



• Am2907 has 2.0V input receiver threshold; Am2908 is 
"DEC Q or LSI-II bus compatible" with 1.5V receiver 
threshold 

• Receiver has output latch for pipeline operation 

• Three-state receiver outputs sink 12mA 

• Advanced Low-power Schottky processing 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 



FUNCTIONAL DESCRIPTION 

The Am2907 and Am2908 are high-performance bus trans- 
ceivers intended for bipolar or MOS microprocessor system ap- 
plications. The Am2908 is Digital Equipment Corporation "Q or 
LSI-II bus compatible" while the Am2907 features a 2.0V receiver 
threshold. These devices consist of four D-type edge-triggered 
flip-flops. The flip-flop outputs are connected to four open-col- 
lector bus drivers. Each bus driver is internally connected to one 
input of a differential amplifier in the receiver. The four receiver 
differential amplifier outputs drive four D-type latches, that feature 
three-state outputs. The devices also contain a four-bit odd parity 
checker/generator. 

These LSI bus transceivers are fabricated using advanced 
low-power Schottky processing. All inputs (except the BUS in- 
puts) are one LS unit load. The open-collector bus output can 
sink up to 100mA at 0.8V maximum. The BUS input differential 
amplifier contains disconnect protection diodes such that the 
bus is fail-safe when power is not applied. The bus enable 
input (BE) is used to force the driver outputs to the high-impe- 
dance state. When BE is HIGH, the driver is disabled. The 
open-collector structure of the driver allows wired-OR opera- 
tions to be performed on the bus. 

The input register consists of four D-type flip-flops with a buf- 
fered common clock. The buffered common clock (DRCP) en- 
ters the Aj data into this driver register on the LOW-to-HIGH 
transition. 

Data from the A input is inverted at the BUS output. Likewise, 
data at the BUS input is inverted at ihe receiver output. Thus, 
data is non-inverted form driver input to receiver output. The 
four receivers each feature a built-in D-type latch that is con- 
trolled fro m th e buffered receiver latch enable (RLE) input. 
When the RLE input is LOW, the latch is open and the receiver 
outputs will follow the bus inputs (BUS data inverted and OE 
LOW). When the RLE input is HIGH, the latch will close and 
retain the present data regardless of the bus input. The four 
latches have three-state outputs and are controlled by a buf- 
fered common three-state control (OE) input. When OE is 
HIGH, the receiver outputs are in the high-impedance state. 

The Am2907 and Am2908 feature a built-jn_ four-bit odd parity 
checker/generator. The bus enable input (BE) controls whether 
the parity output is in the generate or check mode. When the 
bus enable is LOW (driver enabled), odd parity is generated 
based on the A field data input to the driver register. When BE 
is HIGH, the parity output is determined by the four latch out- 
puts of the receiver. Thus, if the driver is enabled, parity is 
generated and if the driver is in the high-impedance state, the 
BUS parity is checked. 

The Am2907 has receiver threshold typically of 2.0V while the 
Am2908 threshold is typically 1 .5V. 



LOGIC SYMBOL 



RLE 



Ao Al A2 A3 
DRCP ODD 

Ro 
R| 

"3 

BUSQ BUSi BUS2 8US3 



Am2907 
Am2908 



TTTT 



V CC = Pin 20 
GND-) = Pin 5 
GND 2 = Pin 15 



CONNECTION DIAGRAM 
Top View 



rle[~_ 

AoC 
BUSoQ 

BUS,[~_ 
AC 

»c 

beC 
oddQ 



Am2907 ' 
e Am2908 15 



7JVCC 
~ Jdrcp 

□ «3 

□ A3 
^]8US3 
^ GND2 
^ 8US2 

□ a 2 

□ 51 



Note: Pin 1 is marked for orientation. 



ORDERING INFORMATION 



Type 



Temperature 



Am2907 Am2908 
Order Order 
Number 



Molded DIP 0°Cto+70°C AM2907PC AM2908PC 

Hermetic DIP 0°C to +70°C AM2907DC AM2908DC 

Dice 0°C to +70°C AM2907XC AM2908XC 

Hermetic DIP -55°C to +125°C AM2907DM AM2908DM 

Hermetic Flat Pak -55°C to +125°C AM2907FM 

Dice -55°Cto +125°C AM2907XM 



Am2907/08 



LOGIC DIAGRAM 




MPR-085 



MAXIMUM RATINGS (Above which the useful life may be impaired) 


Storage Temperature 


-65°Cto+150°C 


Temperature (Ambient) Under Bias 


-55°Cto+125°C 


Supply Voltage to Ground Potential 


-0.5 V to +7 V 


DC Voltage Applied to Outputs for HIGH Output State 


-0.5 V to +V(X max. 


DC Input Voltage 


-0.5 V to +5.5 V 


DC Output Current, Into Outputs (Except BUS) 


30 mA 


DC Output Current, Into Bus 


200 mA 


DC Input Current 


-30 mA to +5.0 mA 



ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 

Am2907XC, Am2908XC (COM'L) T A = 0°C to +70°C V cc MIN. = 4.75V V cc MAX. = 5.25V 

Am2907XM, Am2908XM (MIL) T A = -55°C to +125°C V cc MIN. = 4.50V V cc MAX. = 5.50V 

BUS INPUT/OUTPUT CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

Typ. 



Parameters 


Description 


Test Conditions (Note 1) 


Min. 


(Note 2) 


Max. 


Units 










I l = 40mA 






0.32 


0.5 




Vol 




Bus Output LOW Voltage 


V CC = MIN- 


l 0L = 70mA 






0.41 


0.7 


Volts 










l 0L = 100mA 






0.55 


0.8 












V 4 0.4V 








-50 




b 




Bus Leakage Current 


v cc = MAX - 


V = 4.5V 


MIL 






200 


fj.A 










COM'L 






100 




'off 


Bus Leakage Current (Power Off) 


V = 4.5V 










100 


/xA 










Am2907 


MIL 


2.4 


2.0 






Vth 




Receiver Input HIGH Threshold 


Bus Enable = 2.4V 


COM'L 


2.3 


2.0 




Volts 




Am2908 


MIL 


1.9 


1.5 










COM'L 


1.7 


1.5 












Am2907 


MIL 




2.0 


1.5 




Vtl 




Receiver Input LOW Threshold 


Bus Enable = 2.4V 


COM'L 




2.0 


1.6 


Volts 




Am2908 


MIL 




1.5 


1.1 










COM'L 




1.5 


1.3 




V, 




Input Clamp Voltage 


V CC = MIN., I|N = " 


18mA 








-1.2 


Volts 



4-99 



Am2907/08 



ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 

Am2907XC, Am2908XC (COWL) T A = 0°C to +70°C V cc MIN. = 4.75V V cc MAX. = 

Am2907XM, Am2908XM (MIL) T A = -55°C to + 125°C V cc MIN. = 4.50V V cc MAX. = 

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Parameters 



Description 



Test ConditionslNote 1) 



5.25V 
5.50V 



Min. 



Typ. (Note 2) Max. 



Units 



v OH 




Receiver 

Output HIGH Voltage 


V CC = MIN. 

V|N = V|L or V| H 


MIL: Iqh " -1mA 


2.4 


3.4 




Volts 


COM'L: l H = -2.6mA 


2.4 


3.4 




VOH 




Parity 

Output HIGH Voltage 


V cc = MIN., I H - -660/JA 
V| N = V| H orV||_ 


MIL 


2.5 


3.4 




Volts 


COM'L 


2.7 


3.4 




vol 




Output LOW Voltage 
(Except Busl 


V CC = MIN. 

V| N = V| L or V| H 


'OL = 4mA 




0.27 


0.4 


Volts 


IOL~ 8mA 




0.32 


0.45 


Iql = 12mA 




0.37 


0.5 


V| H 




Input HIGH Level 
(Except Bus) 


Guaranteed input logical HIGH 
for all inputs 


2.0 






Volts 


V|L 




Input LOW Level 
(Except Bus) 


Guaranteed input logical LOW 
for all inputs 


MIL 






0.7 


Volts 


COM'L 






0.8 


V| 




Input Clamp Voltage 
(Except Bus) 


V CC = MIN., I| N - -18mA 






-1.2 


Volts 


>IL 




Input LOW Current 
(Except Bust 




V cc = MAX., V| N = 0.4 V 






-0.36 


rnA 


l|H 




Input HIGH Current 
(Except Bus) 


VCC " MAX., V IN = 2.7 V 






20 


MA 






Input HIGH Current 
(Except Bus) 


V CC = MAX., V, N = 5.5 V 






100 


MA 


!SC 




Output Short Circuit 
Current (Except Bus) 


VCC = MAX - 


-12 




-65 


mA 


•cc 




Power Supply Current 


Vcc = MAX., All Inputs = GND 




75 


110 


mA 


'o 




Off-State Output Current 
(Receiver Outputs) 


V C C = MAX- 


V Q - 2.4 V 






20 


MA 


Vq - 0.4 V 






-20 



Am2907 SWITCHING CHARACTERISTICS 
OVER OPERATING TEMPERATURE RANGE 

Description Test Conditions 



Am2907XM 



Min. 



Typ. 

(Note 2) 



Max. 



Am2907XC 



Typ. 

Min. (Note 2) 



Max. 



Units 



'PHL 



«PLH 



«PHL 



<PLH 



Driver Clock (DRCP) to Bus 



Bus Enable (BE) to Bus 



C L (BUS) =50pF 
R L (BUS) = 5012 



26 



13 



th 



Data Inputs 



t PW 



Clock Pulse Width (HIGH) 



rpLH 



•PHL 



Bus to Receiver Output 
(Latch Enabled) 



tPLH 



«PHL 



Latch Enable to Receiver Output 



«h 



Bus to Latch Enable (RLE) 



C L - 15pF 
R L " 2.0kfi 



21 



7.0 



<PLH 



tPHL 



Data to Odd Parity Out 
(Driver Enabled) 



tPLH 



tPHL 



Bus to Odd Parity Out 
(Driver Inhibit) 



»PLH 



»PHL 



Latch Enable (RLE) to Odd 
Parity Output 



»ZH 



«ZL 



Output Control to Output 



tHZ 



<LZ 



Output Control to Output 



' 2,0 kfi 



37 



37 



37 



18 



21 



40 



14 



28 



21 



14 



34 



36 



36 



36 



25 



Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics 

2. Typical limits are at VQC = 5.0V, 25°C ambient and maximum loading. 

3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed 



for the applicable devicB type, 
one second. 



4-100 



raram 


eiers Description Test Conditions 


Min. (Note 2) Max. 


■ TH- 

Min. (Note 2) Max. 


Units 


tpHL 




Driver Clock (DRCP) to Bus 


C L (BUS) = 50pF 
R U (BUS): 9into 

v C c 

2000 to GND 




21 


40 




21 


36 


ns 


tpLj. 






21 


40 




21 


36 


*PHL 




Bus Enable (BE) to Bus 




13 


26 




13 


23 


ns 


•piH 






13 


26 




13 


23 


tr 


Bus Output Rise Time 


5 


10 




7 


10 




ns 


tf 


Bus Output Fall Time 


3 


6 




4 


6 




ts 


Data Inputs 


18 






15 






ns 


th 


8.0 






7.0 






*PW 




Clock Pulse Width (HIGH) 


28 






25 






ns 


'PLH 




Bus to Receiver Output 
(Latch Enabled) 


C L = 50pF 
R L = 2.0kn 




18 


38 




18 


35 


ns 


>PHL 






18 


38 




18 


35 


*PLH 




Latch Enable to Receiver Output 




21 


38 




21 


35 


ns 


'PHL 






21 


38 




21 


35 


<s 




Bus to Latch Enable (RLE) 


21 






18 






ns 


th 




7.0 






5.0 






>PLH 




Data to Odd Parity Out 
(Driver Enabled) 


C L = 15pF 
R L = 2.0kfi 




21 


40 




21 


36 


ns 


'PHL 






21 


40 




21 


36 


'PLH 




Bus to Odd Parity Out 
(Driver Inhibit) 




21 


40 




21 


36 


ns 


<PHL 






21 


40 




21 


36 


*PLH 




Latch Enable (RLE) to Odd 
Parity Output 




21 


40 




21 


36 


ns 


'PHL 






21 


40 




21 


36 


'ZH 




Output Control to Output 




14 


28 




14 


25 


ns 


tZL 






14 


28 




14 


25 


«HZ 




Output Control to Output 


C L = 5.0pF 
R L = 2.0kfl 




14 


28 




14 


25 


ns 


tLZ 






14 


28 




14 


25 



Notes: 1 . For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics fo the applicable device type. 
2. Typical limits are at V cc = 5.0V, 25°C ambient and maximum loading. 



4-101 



Am2907/08 



INPUT/OUTPUT CURRENT 
INTERFACE CONDITIONS 



DRIVEN INPUT 



DRIVING OUTPUT 




Note: Actual current flow direction shown. 



Bus Output Low Voltage 
Versus Ambient Temperature 



PERFORMANCE CURVES 



Am2907 
Receiver Threshold Variation 
Versus Ambient Temperature 



Am2908 
Receiver Threshold Variation 
Versus Ambient Temperature 







































V CC -5.5V| 












y 






h 






! 




. 1 _ 








■a 


- 4.75V 












v 
















■c 


; = 4.5V 























































1 






c" 


5.5 V 




1 


'cc 


= 5.1 


5V 




— MIL 










v 
















;co 








































4.75V 







































55-35 -15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - 'C 



-55 -35-15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE - °C 



-55 -35-15 5 25 45 65 85 105 125 
T A - AMBIENT TEMPERATURE -°C 
MPR-508 



Am2907/08 SWITCHING WAVEFORMS 



r 



/ \ £ 



— I K- 



3.0V 
1.3V 



3.0V 
1.3V 



2.0 V 

vol 



1. INPUT SET-UP AND HOLD TIMES. 



4-102 



Am2907/08 



Am2907/08 SWITCHING WAVEFORMS 
AND LOAD TEST CIRCUITS 



'if 



901 
10«i 



-t PW - 



W' of- 

/l.5V 

lot / 



- ! PHL tPLH ~ 



UtpHL*j 



aw 



2. DRIVER CLOCK (DRCP) TO BUS 3. BUS ENABLE (BE) TO BUS 

DRIVER SWITCHING WAVEFORMS 



T 



Am2907 
DRIVER LOAD TEST CIRCUIT 







D O 
CP 




BUS n | 


— 
— 1> — 


% 




l 



Am2908 MPR-512 
DRIVER LOAD TEST CIRCUIT 



OE 
RLE 



BUS„ 



OE 



90' < 90% 



1.5V 

.10* 



— IPHL— J I— t PL „ 1 



.jF 



BUS„ l"sv\ ^ 

"«H— I 



X 

|- — 'pw — -j 



■ ov 

-3V 



IPHL 












\ 


^ 1.5V 



1 PLH " 



4. BUS TO RECEIVER OUTPUT 
(LATCH ENABLED) 



5. LATCH ENABLE TO OUTPUT mpr-sh 

RECEIVER SWITCHING WAVEFORMS 



BUS„ 



RLE - 

SI - 




C L ±: >5K(1 *ll diodes 

ARE 1N3064 



MPR-515 Am2907/08 RECEIVER LOAD TEST CIRCUIT. 



* Note: C L = 1 5pF for Am2907 
C L = 50pF for Am2908 



4-103 



Am2907/08 



A 0-3 



BE 



Am2907/08 SWITCHING WAVEFORMS 
AND LOAD TEST CIRCUITS (Cont.) 



OE 1.5V 



OUTPUT 
NORMALLY 
LOW 



OUTPUT 
NORMALLY 
HIGH 



£ 



-*ZL — — j 
PEN ^~ 



-<LZ— | .5V 



1 



T 



S1 AND S2 
V 0H CLOSED 



S1 AND S2 
CLOSED 



6. RECEIVER TRI-STATE WAVEFORMS 



¥ ^¥ — 

A A 



BUSq-3 1.5V 



-*PLH tpHL- 



■ ov 

R-51B 



7. A INPUT TO PARITY OUTPUT 8. BUS TO PARITY OUTPUT 

ODD PARITY OUTPUT WAVEFORMS 




DEVICE 






ODD 




Note 1 : C L = 15pF for t ZL , t ZH 
C L = 5pFfort LZ , t HZ 

MPR-519 

LOAD FOR RECEIVER TRI-STATE TEST 



LOAD FOR PARITY OUTPUT 



4-104 



Am2907/08 



TRUTH TABLE 



INPUTS 


INTERNAL 
TO DEVICE 


BUS 


OUTPUT 


FUNCTION 


Aj 


DRCP 


BE 


RLE 


OE 


m 


Qi 


B: 


Ri 


X 


X 


H 


X 


X 


X 


X 


H 


X 


Driver output disable 


X 


X 


X 


X 


H 


X 


X 


X 


z 


Receiver output disable 


X 


X 


H 


L 


L 


X 


L 


L 


H 


Driver output disable and receive data 


X 


X 


H 


L 


L 


X 


H 


H 


L 


via Bus input 


X 


X 


X 


H 


X 


X 


NC 


X 


X 


Latch received data 


L 
H 


t 
t 


X 
X 


X 
X 


X 
X 


L 
H 


X 
X 


X 
X 


X 
X 


Load driver register 


X 
X 


L 

H 


X 
X 


X 
X 


X 
X 


NC 
NC 


X 
X 


X 
X 


X 
X 


No driver clock restrictions 


X 
X 


X 
X 


L 
L 


X 
X 


X 
X 


L 
H 


X 
X 


H 
L 


X 
X 


Drive Bus 



H = HIGH Z = High Impedance X = Don't Care i = 0, 1,2, 3 

L=LOW NC= No Change t = LOW-to-HIGH Transition 



PARITY OUTPUT FUNCTION TABLE 



BE 


ODD PARITY OUTPUT 


L 
H 


ODD = Aq 9 Ai ffi A2 ® A3 
ODD = Qq ® Q1 ® Q2 ffi Q3 



DEFINITION OF FUNCTIONAL TEI 



DRCP Driver Clock Pulse. Clock pulse for the driver register. 

BE Bus Enable. When the Bus Enable is LOW, the four 
drivers are in the high impedance state. 

BUSo, BUS-|, BUS2, BUS3 The four driver outputs and 
receiver inputs (data is inverted). 

RO. Rl> "2> "3 Tne f° ur receiver outputs. Data from the 
bus is inverted while data from the A or B inputs is non- 
inverted. 

RLE Receiver Latch Enable. When RLE is LOW, data on the 
BUS inputs is passed through the receiver latches. When RLE 
is HIGH, the receiver latches are closed and will retain the 
data independent of all other inputs. 

ODD Odd parity output. Generates parity with the driver 
enabled, checks parity with the driver in the high-impedance 
state. 

OE Output Enable. When the OE input is HIGH, the four 
three-state receiver outputs are in the high-impedance state. 



Metallization and Pad Layout 




DIE SIZE 0.088" X 0.103" 



4-105 



Am2907/08 



APPLICATIONS 



SBUS 



Am 2907/8 

DATA BUS ■ 
REGISTER 



BUS Am2907/8 



Am29D9 
MICROPROGRAM 
SEQUENCER 



Am2901A 
BIPOLAR 
MICROPROCESSOR 



Am2918 
M1CHOWOHD 
REGISTER 



The Am2907 can be used as an I/O Bus Transceiver and Main Memory I/O Transceiver 
in high-speed Microprocessor Systems. 



u 

31 



_SZ 



t 

X 




o 



Am2907 



7\ 



1Z 



Am26S10 



a 



V 



Am2907 



Am2907 



1Z. 



Am26S10 



iz 



1Z 



1Z 



AZ 



CONTROL 





3 



Using the Am2907 and Am26S10 in a terminated Bus system for the Am9080 MOS Microprocessor. 



4-106 



Am2915A 

Quad Three-State Bus Transceiver With Interface Logic 



Distinctive Characteristics 

• Quad high-speed LSI bus-transceiver 

• Three-state bus driver 

• Two-port input to D-type register on driver 

• Bus driver output can sink 48mA at 0.5V max. 

• Receiver has output latch for pipeline operation 



• Three-state receiver outputs sink 12mA 

• Advanced low-power Schottky processing 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 

• 3.5V minimum output high voltage for direct inter- 
face to MOS microprocessors 





FUNCTIONAL DESCRIPTION 

The Am2915A is a high-performance, low-power Schottky bus 
transceiver intendedfor bipolar or MOS microprocessor system 
applications. The device consists of four D-type edge-triggered 
flip-flops with a built-in two-input multiplexer on each. The 
flip-flop outputs are connected to four three-state bus drivers. 
Each bus driver is internally connected to the input of a 
receiver. The four receiver outputs drive four D-type latches 
that feature three-state outputs. 

This LSI bus transceiver is fabricated using advanced low- 
power Schottky processing. All inputs (except the BUS inputs) 
are one LS unit load. The three-state bus output can sink up 
to 48mA at 0.5V maximum. The bus enable input (BE) is 
used to force the driver outputs to the high-impedance state. 
When BE is HIGH, the driver is disabled. The Vqh and Vql of 
the bus driver are selected for compatibility with standard and 
Low-Power Schottky inputs. 

The input register consists of four D-type flip-flops with a 
buffered common clock and a two-input multiplexer at the 
input of each flip-flop. A common select input (S) controls the 
four multiplexers. When S is LOW, the Aj data is stored in the 
register and when Sis HIGH, the Bj data is stored. The buffered 
common clock (DRCP) enters the data into this driver register 
on the LOW-to-HIGH transition. 

Data from the A or B inputs is inverted at the BUS output. 
Likewise, data at the BUS input is inverted at the receiver out- 
put. Thus, data is non-inverted from driver input to receiver 
output. The four receivers each feature a built-in D-type latch 
t hat is controlled from the buffered receiver latch enable 
(RLE) input. When the RLE input is LOW, the latch is open 
and the receiver outputs will follow the b us inputs (BUS data 
inverted and OE LOW). When the RLE input is HIGH, the 
latch will close and retain the present data regardless of the 
bus input. The four latches have three-state outputs and are 
controlled by a buffered common three-state control (OE) 
input. When OE is HIGH, the receiver outputs are in the high- 
impedance state. 



LOGIC SYMBOL 



16 15 20 21 



A Bq A, B, a 2 b 2 a 3 b 3 



BUS n BUS. BUS? 



rr 



V cc =Pin24 
GND, « Pin 6 



CONNECTION DIAGRAM 
Top View 



RLE | 


1 


24 


Zl v cc 


»oC 


2 


23 


| DRCP 


BoLZ 


3 


22 


Zl R 3 


A olZ 


4 


21 


Z1 B 3 




5 


20 


Z!*3 


GNOj 


6 

Am2915A 


19 


I]BUS 3 


BUS, 


7 


18 


| GND 2 




8 


17 




■id 


9 


16 


Zl*2 




10 


15 


Z1 B 2 


BTLZ 


11 


14 


Z R 2 


51C 


12 


13 


Zh 



Note: Pin 1 is marked for orientation. 



4-107 



Am2915A 



LOGIC DIAGRAM 



A o o- 



B oo 

ft l o 




Bl 




A 2 O- 



B 2 0- 



A30- 



B 3 
SELECT S 



DRIVER 
CLOCK 






bus bus, bus 2 bus 3 
9 9 9 



BUS ^ 

ENABLE BE O 



-o"o 



-OR, 



-0«2 



-O r 3 



RECEIVER 
- O RLE LATCH 
ENABLE 



MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65 C to +150 C 



Temperature (Ambient) Under Bias 



-55°C to +125°C 



Supply Voltage to Ground Potential 



-0.5V to +7V 



DC Voltage Applied to Outputs for HIGH Output State 



-0.5V to +V CC max. 



DC Input Voltage 



-0.5V to +7V 



DC Output Current, Into Outputs (Except Bus) 



30 mA 



DC Output Current, Into Bus 



100mA 



DC Input Current 



-30mA to +5.0mA 



ELECTRICAL CHARACTERISTICS 



The following 
Am2915AXC 



conditions apply unless otherwise noted: 



(COM'L) 



T A = OCto+70C V CC MIN. = 4.75V V cc MAX. = 5.25 V 

T A - -55°C to +125°C V CC MIN. - 4.50V V cc MAX. - 5.50 V 



Am2915AXM (MIL) 

BUS INPUT/OUTPUT CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Parameters 


Description 


Test Conditions (Note 1) 


Min. 


Typ. 


Max. 


Units 


vol 


Bus Output LOW Voltage 


V cc = MIN. 


Iql " 24mA 






0.4 


Volts 


Iql " 48mA 






0.5 


Voh 


Bus Output HIGH Voltage 


V cc = MIN. 


COM'L, Iqh = -20mA 


2.4 






Volts 


MIL, Iqh = -15mA 








Bus Leakage Current 
(High Impedance! 


Vcc = MAX. 
Bus enable = 2.4 V 


V = 0.4 V 






-200 




'0 


V = 2.4 V 






50 








V -4.5 V 






100 




'OFF 


Bus Leakage Current 
(Power OFF) 


V =4.5V 
V C C = ov 






100 


*A 


V| H 


Receiver Input HIGH Threshold 


Bus enable = 2.4V 


2.0 






Volts 


V| L 


Receiver Input LOW Threshold 


Rnc onahle - 9 4 \/ 


COM'L 






0.8 


Volts 






MIL 






0.7 


<SC 


Bus Output Short Circuit Current 


V CC = MAX. 
V = OV 


-50 


-120 


-225 


mA 



4-108 



-55 C to +125 C 



-MIN. - 4.50V 



DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

Parameters Description Test Conditions (Note D 



Min. 



Typ. 

(Note 2) 



Max. 



Units 



v 


OH 


Receiver 

Output HIGH Voltage 


V cc = MIN. 

V| N - V| L or V| H 


MIL: Iqh " -1.0mA 


2.4 


3.4 




Volts 


COM'L: Iq H = -2.6mA 


2.4 


3.4 




V C C = 5.0V, l H = -100 mA 


3.5 








Output LOW Voltage 
{Except Bus) 


V CC = M1N. 

V| N = V| L orV| H 


lOL = 4.0mA 




0,27 


0.4 


Volts 


V 


OL 


lOL = 8.0mA 




0.32 


0.45 


IqL = 12mA 




0.37 


0.5 


V| H 


Input HIGH Level 
(Except Bus) 


Guaranteed input logical HIGH 
for all inputs 


2.0 






Volts 


V 


L 


Input LOW Level 
( Except Bus) 


Guaranteed input logical LOW 
for all inputs 


MIL 






0.7 


Volts 


COM'L 






0.8 


V 


I 


Input Clamp Voltage (Except Bus) 


V CC = MIN., I| N » -18mA 






-1.2 


Volts 






Input LOW Current (Except Bus) 


V C C - MAX., V| N = 0.4V 


BE, RLE 






-0.72 


mA 




All other inputs 






-0.36 


' IH 


Input HIGH Current (Except Bus) 


VCC = MAX., V| N = 2.7 V 






20 


uA 




Input HIGH Current (Except Bus) 


V C C = MAX., V| N = 7.0V 






100 


ma 


'sc 


Output Short Circuit Current 
(Except Bus) 


V CC = MAX. 


-30 




-130 


mA 


•cc 


Power Supply Current 


V CC = MAX. 




63 


95 


mA 


'c 


) 


Off -State Output Current 
(Receiver Outputs) 


V C C = MAX. 


V = 2.4 V 






50 


uA 


V = 0.4 V 






-50 



SWITCHING CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Parame 


lers Description Test Conditions 


Am2915AXM 
Typ. 

Min. (Nota2) Max. 


Am2915AXC 
Typ. 

Min. (Note 2) Max. 


Units 


'PHL 




Driver Clock (DRCP) to Bus 


C L (BUS) = 50pF 
R|_(BUS) = 130n 




21 


36 




21 


32 


ns 


'PLH 






21 


36 




21 


32 


«ZH.«ZL 


Bus Enable (BE) to Bus 




13 


26 




13 


23 


ns 


'HZ.«LZ 




13 


21 




13 


18 


h 




Data Inputs (A or B) 


C L - 15pF 
R|_ = 2.0kt2 


15 






12 






ns 


«h 




8.0 






6.0 






«s 




Select Input (S) 


28 






25 






ns 


th 




8.0 






6.0 






t pw 




Driver Clock (DRCP) Pulse Width 
(HIGH) 


20 






17 






ns 


«PLH 




Bus to Receiver Output 
(Latch Enable) 




18 


33 




18 


30 


ns 


«PHL 




18 


30 




18 


27 


'PLH 


Latch Enable to Receiver Output 




21 


33 




21 


30 


ns 


tPHL 




21 


30 




21 


27 




Bus to Latch Enable (RLE) 


15 






13 






ns 


«h 


6.0 






4.0 






'ZH.'ZL 


Output Control to Receiver Output 




14 


26 




14 


23 


ns 


1HZ. t 


LZ 


C L = 5pF, R|_ = 2.0kS2 




14 


26 




14 


23 



Notes: 1. 
2. 
3. 



For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type. 
Typical limits are at V cc = 5.0V, 25°C ambient and maximum loading. 

Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 



4-109 



Am2915A 



INPUT/OUTPUT CURRENT 
INTERFACE CONDITIONS 



DRIVEN INPUT 



DRIVING OUTPUT 




Note: Actual current flow direction shown. 



SWITCHING TEST CIRCUIT 




5.0kn 



*C L = 15pF for tp LH , tpHL. 
C L = 5pFfor tHZ.^LZ 



SWITCHING WAVEFORMS 



/ \ £ 



r 



3.0 V 
1.3V 



BUS 
OUTPUT 



EIVER 
UTPUT 



X 



X 



V H 

1.3 V 



Note: Bus to Receiver output delay is measured by clocking data into the driver register 
and measuring the BUS to R combinatorial delay. 



4-110 



Am2915A 



INPUTS 


INTERNAL 
TO DEVICE 


BUS 


OUTPUT 


FUNCTION 


S 


A, 


Bi 


DRCP 


BE 


RLE 


OE 


Di 


Qi 


BUSj 


Ri 




X 


X 


X 


X 


H 


X 




X 


X 


z 


X 


Driver output disable 


X 


X 


X 


X 


X 


X 


H 


X 


X 


X 


Z 


Receiver output disable 


X 


X 


X 


X 


H 


L 


L 


X 


L 


L 


H 


Driver output disable and 


X 


X 


X 


X 


H 


L 


L 


X 


H 


H 


L 


receive data via Bus input 


X 


X 


X 


X 


X 


H 


X 


X 


NC 


X 


X 


Latch received data 


L 


L 


X 


t 


X 


X 


X 


!_ 


X 


X 


X 




L 
H 


H 
X 


X 
L 


t 

t 


X 
X 


X 
X 


X 
X 


H 
L 


X 
X 


X 
X 


X 
X 


Load driver register 


H 


■■ 


H 


' 


X 


X 


x 


H 


X 


X 


X 




X 
x 


X 
X 


X 
X 


L 

I H 


X 
X 


X 
X 


x 
X 


NC 
NC 


X 
X 


X 
X 


X 
X 


No driver clock restrictions 


X 
X 


X 

X 


X 
X 


I X 
X 


L 
L 


X 
X 


X 
X 


L 
H 


X 
X 


H 
L 


X 
X 


Drive Bus 



FUNCTIONAL TABLE 



H - 

L - 



HIGH Z - HIGH Impedance 
LOW NC = No change 



X - Don't care 
t = LOW to HIGH 



Metallization and Pad Layout 




DIE SIZE .074" X .130" 



DEFINITION OF FUNCTIONAL TERMS 

Aq.A 

B . "l 



A2, A3 The "A" word data input into the two 
input multiplexer of the driver register. 



B 2 , B 3 The "B" word data input into the two 
input multiplexers of the driver register. 

Select. When the select input is LOW, the 
A data word is applied to the driver reg- 
ister. When the select input is HIGH, the 
B word is applied to the driver register. 

Driver Clock Pulse. Clock pulse for the 
driver register. 

Bus Enable. When the Bus Enable is HIGH, 
the four drivers are in the high impedance 
state. 



BUS , BUS<| 
BUS 2 , BUS3 

Ro. Ri. R2. R3 

RLE 



OE 



The four driver outputs and receiver in- 
puts (data is inverted). 

The four receiver outputs. Data from the 
bus is inverted while data from the A or B 
inputs is non-inverted. 

Receiver Latch Enable. When RLE is 
LOW, data on the BUS inputs is p assed 
through the. receiver latches. When RLE 
is HIGH, the receiver latches are closed 
and will retain the data independent of 
all other inputs. 

Output Enable. When the OE input is 
HIGH, the four three state receiver out- 
puts are in the high-impedance state. 



ORDERING INFORMATION 

Order the part number according to the table below to obtain the desired package, temperature range, and screening I 





Package Type 


Temperature Range 


Screening Level 


Order Number 


(Note 1) 


(Note 2) 


(Note 3) 


AM2915APC 


P-24 


C 


C-1 


AM2915ADC 


D-24 


C 


C-1 


AM2915ADC-B 


D-24 


C 


B-1 


AM2915ADM 


D-24 


M 


C-3 


AM2915ADM-B 


D-24 


M 


B-3 


AM2915AFM 


F-24 


M 


C-3 


AM291 5AFM-B 


F-24 


M 


B-3 


AM2915AXC 


Dice 


C 


\ Visual inspection 


AM2915AXM 


Dice 


M 


} to MIL-STD-883 


J Method 2010B. 



Notes: 1. P = Molded DIP, D = Hermetic DIP, F = Flat Pak. Number following letter is number of leads. See Appendix B for detailed outline. 
Where Appendix B contains several dash numbers, any of the variations of the package may be used unless otherwise specified. 

2. C = 0°C to +70°C, M = -55°C to +125°C. 

3. See Appendix A for details of screening. I 
Class B. 



d C-3 conform to MIL-STD-883, Class C. Level B-3 conforms to MIL-STD-883, 



4-111 



Am2915A 



ADDRESS 
AND 
DATA DISPLAY 



APPLICATIONS 



A CONTROL B 







A B CONTROL 



DATA 
BUS 



CONTROL 
SCRATCHPAD 



A B CONTROL 



A B CONTROL 



The Am2915A is a universal Bus Transceiver useful for many system data, address, control and 
timing input/output interfaces. 



I/O DEVICES 



A- 



a 

H 




Am8T26 Am8T26 



Am822B Am8T26 



TV 



OLJO 



TV 



1Z 



7V 



Am2915A 



iz 



Am2915A 

~7V 



Am8T26 

~7V 



1 



iz 



iz 



iz 



If 



J>z_ 







3 



Using the Am2915A and Am8T26 in a terminated Bus system for the Am9080 MOS Microprocessor. 



4-112 



Am2916A 



Quad Three-State Bus Transceiver With Interface Logic 



Distinctive Characteristics 

• Quad high-speed LSI bus-transceiver 

• Three-state bus driver 

• Two-port input to D-type register on driver 

• Bus driver output can sink 48mA at 0.5V max. 

• Internal odd 4-bit parity checker/generator 

• Receiver has output latch for pipeline operation 



Receiver outputs sink 12mA 

Advanced low-power Schottky processing 

100% reliability assurance testing in compliance with 

MIL-STD-883 

3.5V minimum output high voltage for direct inter- 
face to MOS microprocessors 



FUNCTIONAL DESCRIPTION 

The Am2916A is a high-performance, low-power Schottky 
bus transceiver intended for bipolar or MOS microprocessor 
system applications. The device consists of four D-type edge- 
triggered flip-flops with a built-in two-input multiplexer on 
each. The flip-flop outputs are connected to four three-state 
bus drivers. Each bus driver is internally connected to the 
input of a receiver. The four receiver outputs drive four D-type 
latches. The device also contains a four-bit odd parity checker/ 
generator. 

The LSI bus transceiver is fabricated using advanced low-power 
Schottky processing. All inputs (except the BUS inputs) 
are one LS unit load. The three-state bus output can sink 
up to 48mA at 0.5V maximum. The bus enable input (BE) is 
used to force the driver outputs to the high-impedance state. 
When BE is HIGH, the driver is disabled. 

The input register consists of four D-type flip-flops with a 
buffered common clock and a two-input multiplexer at the 
input of each flip-flop. A common select input (S) controls 
the four multiplexers. When S is LOW, the Aj data is stored 
in the register and when S is HIGH, the Bj data is stored. The 
buffered common clock (DRCP) enters the data into this 
driver register on the LOW-to-HIGH transition. 

Data from the A or B input is inverted at the BUS output. 
Likewise, data at the BUS input is inverted at the receiver out- 
put. Thus, data in non-inverted from driver input to receiver 
output. The four receivers each feature a built-in D-type latch 
t hat is controlled from the buffered receiver latch enable 
(RLE) input. When the RLE input is LOW, the latch is open 
and the receiver outp uts w ill follow the bus inputs (BUS data 
inverted). When the RLE input is HIGH, the latch will close 
and retain the present data regardless of the bus input. 

The Am2916A features a built-in four-bit odd parity checker/ 
generator. The bus enable input (BE) controls whether the 
parity output is in the generate or check mode. When the bus 
enable is LOW (driver enabled), odd parity is generated based 
on the A or B field data input to the driver register. When BE 
is HIGH, the parity output is determined by the four latch 
outputs of the receiver. Thus, if the driver is enabled, parity is 
generated and if the driver is in the high-impedance state, the 
BUS parity is checked. 



LOGIC SYMBOL 



16 15 20 21 



a b a, b, a 2 b 2 a 3 b 3 

S ODD 



RLE 

BUS n BUS, BUS, BUS-, 



TTTT 



V CC = Pin 24 
GND, = Pin 6 
GND 2 - Pin 18 



CONNECTION DIAGRAM 
Top View 



RLE 

B oLZ 

BotZ 

aus Q 

GND, | 
BUS, 

BE 
ODD | 



Zl v cc 

| DRCP 
"3 

□ B 3 
ZI A 3 

8US 3 
GND 2 
^ BUSj 

□ *2 
Zl«2 

Rj 



Note: Pin 1 is marked for orientation. 



4-113 



Am2916A 



LOGIC DIAGRAM 

BUS BUS] BUS 2 BUS 3 




MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65 C to +150 C 



Temperature (Ambient) Under Bias 



-55 C to +125 C 



Supply Voltage to Ground Potential 



-0.5V to +7V 



DC Voltage Applied to Outputs for HIGH Output State 



-0.5V to +V CC max 



DC Input Voltage 



-0.5V to +7V 



DC Output Current, Into Outputs (Except Bus) 



30mA 



DC Output Current, Into Bus 



DC Input Current 



100mA 



-30mA to +5.0mA 



ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 

Am2916AXC (COM'L) T A - 0°C to + 70°C V cc Ml N. = 4.75 V V cc MAX. - 5.25 V 

Am2916AXM (MIL) T A = -55°C to +1 25°C V cc Ml N. = 4.50 V V cc MAX. - 5.50 V 

BUS INPUT/OUTPUT CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Parameters 


Description 


Test Conditions (Note i) 


Min. 


Typ. 


Max. 


Units 


vol 




Bus Output LOW Voltage 


V CC = MIN. 


'OL = 2 4m A 






0.4 


Volts 




IqL " 48mA 






0.5 


V H 




Bus Output HIGH Voltage 


V CC = MIN. 


COM'L, l H ■ -20mA 


2.4 






Volts 




MIL, l H = -15mA 










Bus Leakage Current 
(High Impedance) 


Vcc " MAX. 
Bus enable m 2.4 V 


Vq = 0.4 V 






-200 




"0 




V - 2.4 V 






50 


HA 






V =4.5V 






100 




'OFF 




Bus Leakage Current 
(Power OFF) 


V =4.5V 

v cc =ov 






100 


M A 


V| H 


Receiver Input HIGH Threshold 


Bus enable = 2.4V 


2.0 






Volts 






Receiver Input LOW Threshold 


Rus *>n»Hfp - ?iV 


COM'L 






0.8 


Volts 








MIL 






0.7 


"sc 




Bus Output Short Circuit Current 


Vcc * MAX. 
V - OV 


-50 


-120 


-225 


mA 



4-114 



Am2916A 

ELECTRICAL CHARACTERISTICS 



The following conditions apply unless otherwise noted: 

Am2916AXC (COM'L) T A - 0°C to + 70° C V cc M I N. - 4.75 V V CC MAX. - 5.25 V 

Am2916AXM (MIL) T A - -55°C to +1 25°C V cc Ml N. = 4.50 V V cc MAX. = 5.50 V 

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 



Parameters Description Test Conditions (Note i) Min. (Note 2) Max. Units 



V H 




Receiver 

Output HIGH Voltage 


V C C = MIN - 

V| N = V| L orV| H 


MIL: Iq H = -1.0mA 


2.4 


3.4 




Volts 


COM'L: l 0H = -2.6mA 


2.4 


3.4 




V CC = 5.0V, l H = -100 mA 


3.5 






V H 




Output HIGH Voltage 


V cc = MIN., Iq H f -660 mA 
V|N = V| H orV| L 


MIL 


2.5 


3.4 




Volts 


COM'L 


2.7 


3.4 




V 0L 




Output LOW Voltage 
(Except Bus) 


V cc = MIN. 

V|N = V IL or V IH 


'OL = 4.0mA 




0.27 


0.4 


Volts 


lOL = 8.0mA 




0.32 


0.45 


IqL - 12 mA 




0.37 


0.5 


V| H 




Input HIGH Level 
(Except Bus) 


Guaranteed input logical HIGH 
for all inputs 


2.0 






Volts 


V IL 




Input LOW Level 
(Except Bus) 


Guaranteed input logical LOW 
for all inputs 


MIL 






0.7 


Volts 


COM'L 






0.8 


V| 




Input Clamp Voltage (Except Bus) 


V C C " MIN., I| N = -18mA 






-1.2 


Volts 


l|L 




Input LOW Current (Except Bus) 


Vcc = MAX., V|N = 0.4 V 


BE, RLE 






-0.72 


mA 


All other inputs 






-0.36 


l|H 




Input HIGH Current (Except Bus) 


Vcc * MAX., V|N = 2.7 V 






20 


»A 


l| 




Input HIGH Current (Except Bus) 


V CC = MAX., V| N = 7.0V 








M A 


'SC 




Output Short Circuit Current 
(Except Bus) 


V CC " MAX. 


RECEIVER 


-30 




-130 


mA 


PARITY 


-20 




-100 


!CC 




Power Supply Current 


V CC = MAX., All Inputs = GND 




75 


no 


mA 



SWITCHING CHARACTERISTICS OVER 
OPERATING TEMPERATURE RANGE 



Parameters 


Description Test Conditions 


Am2916AXM 

Typ. 

Min. (Note 2) Max. 


Am2916AXC 
Typ. 

Min. (Note 2) Max. 


Units 


tPHL 




C L (BUS) = 50pF 
R L (BUS) = 130J2 




21 


36 




21 


32 


ns 


t PLH 


Driver Clock (DRCP) to Bus 




21 


36 




21 


32 


<ZH.*ZL 


Bus Enable ("BE) to Bus 




13 


26 




13 


23 


ns 


«HZ. «LZ 






13 


21 




13 


18 


«s 






15 






12 






ns 


«h 


Data Inputs (A or B) 


8.0 






6.0 






«s 




28 






25 






ns 


th 


Select Inputs (S) 


8.0 






6.0 






*PW 


Clock Pulse Width (HIGH) 


20 






17 






ns 


f PLH 


Bus to Receiver Output 


C L = 15pF 
R L = 2.0k!7 




18 


33 




18 


30 


ns 


*PHL 


(Latch Enabled) 




18 


30 




18 


27 


«PLH 






21 


33 




21 


30 


ns 


tpHL 


Latch Enable to Receiver Output 




21 


30 




21 


27 


ts 




15 






13 






ns 


th 


Bus to Latch Enable (RLE) 


6.0 






4.0 






«PLH 


A or B Data to Odd Parity Output 




32 


46 




32 


42 


ns 


»PHL 


(Driver Enabled) 




26 


40 




26 


36 


tPLH 


Bus to Odd Parity Output 




21 


36 




21 


32 


ns 


«PHL 


(Driver Inhibited, Latch Enabled) 




21 


36 




21 


32 


tPLH 


Latch Enable (RLE) to 




21 


36 




21 


32 


ns 


tPHL 


Odd Parity Output 




21 


36 




21 


32 



Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type. 

2. Typical limits are at V cc = 5.0V, 25°C ambient and maximum loading. 

3. Not more than one output should be shorted at a time. Duration of the short circuit test shoul not exceed one second. 



4-115 



INPUT/OUTPUT CURRENT 
INTERFACE CONDITIONS 



Am2916A 



DRIVEN INPUT 



DRIVING OUTPUT 




OUTPUT, ODD 



Note: Actual current flow direction shown. 



SWITCHING TEST CIRCUIT 



TEST 
POINT 
O 



5-0kS! 



Y 

H<HH 



mm 



l.OkS! 

-VS*- 



*C L = 15pF for tp|_H, tpHL. 
tZL.tZH 
C L = 5pFfor t H z. tLZ 



SWITCHING WAVEFORMS 



/ \ £ 



i— 



\ 



3.0 V 

1.3 V 



WMM ^ 




V H 

1.3V 



Note: Bus to Receiver output delay is measured by clocking data into the driver register 
and measuring the BUS to R combinatorial delay. 



4-116 



Am2916A 



FUNCTION TABLE 



DRCP BE RLE 0~E 



INTERNAL 
TO DEVICE 



Driver output disable 



Receiver output disable 



Driver output disable and 
receive data via Bus input 



Latch received data 



No driver clock restrictions 



Drive Bus 



HIGH 
LOW 



NC = No change 



X - Don't care 
t - LOW to HIGH 



1 = 0,1,2,3 



Metallization and Pad Layout 



A 4 
BUSo 5 



GNDi 6 



mm 



MP® T 



22 R 3 
21 B 3 

20 A 3 
19 BUS3 

18 GND 2 



15 B2 
14 R 2 



DIE SIZE .074" X .130" 



DEFINITION OF FUNCTIONAL TE 



Bo. 



1- A 2. A 3 Tne " A " word data input into the two 
input multiplexer of the driver register. 



1, B 2 , B 3 



The "B" word data input into the two 
input multiplexers of the driver register. 

Select. When the select input is LOW, the 
A data word is applied to the driver reg- 
ister. When the select input is HIGH, the 
B word is applied to the driver register. 



DRCP 
BE 



Clock pulse for the 



Driver Clock Pulse, 
driver register. 

Bus Enable. When the Bus Enable is HIGH, 
the four drivers are in the high impedance 
state. 



BUS , BUSt 
BUS 2 , BUS 3 

Ro. "1. "2. R3 
RLE 



OE 



The four driver outputs and receiver in- 
puts (data is inverted). 

The four receiver outputs. Data from the 
bus is inverted while data from the A or B 
inputs is non-inverted. 

Receiver Latch Enable. When RLE is 
LOW, data on the BUS inputs is p assed 
through the receiver latches. When RLE 
is HIGH, the receiver latches are closed 
and will retain the data independent of 
all other inputs. 

Output Enable. When the OE input is 
HIGH, the four three state receiver out- 
puts are in the high-impedance state. 



ORDERING INFORMATION 

Order the part number according to the table below to obtain the desired package, temperature range, and screening level. 





Package Type 


Temperature Range 


Screening Level 


Order Number 


(Note 1) 


(Note 2) 


(Note 3) 


AM2916APC 


P-24 


C 


C-1 


AM2916ADC 


D-24 


c 


C-1 


AM291 6ADC-B 


D-24 


c 


B-1 


AM2916ADM 


D-24 


M 


C-3 


AM291 6ADM-B 


D-24 


M 


B-3 


AM2916AFM 


F-24 


M 


C-3 


AM291 6AFM-B 


F-24 


M 


B-3 


AM2916AXC 
AM2916AXM 


Dice 
Dice 


C 
M 


| Visual inspection 
1 to MIL-STD-883 


) Method 201 OB. 



Notes: 1 . P = Molded DIP, D = Hermetic DIP, F = Flat Pak. Number following letter is number of leads. See Appendix B for detailed outline. 
Where Appendix B contains several dash numbers, any of the variations of the package may be used unless otherwise specified. 
2. C = OX to +70°C, M = -55°C to + 125°C. 

See Appendix A for details of screening. Levels C-1 and C-3 conform to MIL-STD-883, Class C. Level B-3 conforms to MIL-STD-883, 

Class B. 



4-117 



Am2916A 



ENABLE 

LATCH 

ENABLE 



APPLICATIONS 



A 

s 


B 


DROP 






Am2916A 


BE 




RLE 




R 


ODD BUS 



R ODD BUS 



BITS 
12-15 



1 



p l P 2 P 3 P 4 p 5 P 6 P 7 P 8 P 9 



R ODD BUS 



ODD/EVEN 
" CONTROL 
L = EVEN 
H = ODD 



Generating or checking parity for 16 data bits. 



31 



Am2916A 



Am2916A 



7T 



OTTT1 



Am2916A 



1Z 



A- 



Am2916A 



Am8T26 

~7^~ 



3 



Using the Am2916A and Am8T26 in a terminated Bus system for the Am9080 MOS Microprocessor. 



4-118 



Am2917A 

Quad Three-State Bus Transceiver With Interface Logic 



Distinctive Characteristics 

• Quad high-speed LSI bus-transceiver 

• Three-state bus driver 

• D-type register on driver 

• Bus driver output can sink 48mA at 0.5V max. 

• Internal odd 4-bit parity checker/generator 

• Receiver has output latch for pipeline operation 



• Three-state receiver outputs sink 12mA 

• Advanced low-power Schottky processing 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 

• 3.5V minimum output high voltage for direct inter- 
face to MOS microprocessors 



FUNCTIONAL DESCRIPTION 

The Am2917A is a high-performance, low-power Schottky bus 
transceiver intended for bipolar or MOS microprocessor system 
applications. The device consists of four D-type edge-triggered 
flip-flops. The flip-flop outputs are connected to four three- 
state bus drivers. Each bus driver is internally connected to the 
input of a receiver. The four receiver outputs drive four D-type 
latches, that feature three-state outputs. The device also con- 
tains a four-bit odd parity checker/generator. 

The LSI bus transceiver is fabricated using advanced low- 
power Schottky processing. All inputs (except the BUS inputs) 
are one LS unit load. The three-state bus output can sink up to 
48mA at 0.5V maximum. The bus enable input (BE) is used to 
force the driver outputs to the high-impedance state. When BE 
is HIGH, the driver is disabled. 

The input register consists of four D-type flip-flops with a 
buffered common clock. The buffered common clock (DRCP) 
enters the Aj data into this driver register on the LOW-to- 
HIGH transition. 

Data from the A input is inverted at the BUS output. Like- 
wise, data at the BUS input is inverted at the receiver output. 
Thus, data is non-inverted from driver input to receiver output. 
The four receivers each feature a built-in D-type latch t hat i s 
controlled from the buffered receiver latch enable (RLE) 
input. When the RLE input is LOW, the latch is open and the 
receiver outputs will follow the bus inputs (BUS data inverted 
and OE LOW). When the RLE input is HIGH, the latch will 
close and retain the present data regardless of the bus input. 
The four latches have three-state outputs and are controlled 
by a buffered common three-state control (OE) input. When 
OE is HIGH, the receiver outputs are in the high-impedance 
state. 

The Am2917A features a built-in four-bit odd parity checker/ 
generator. The bus enable input (BE) controls whether the 
parity output is in the generate or check mode. When the bus 
enable is LOW (driver enabled), odd parity is generated based 
on the A field data input to the driver register. When BE is 
HIGH, the parity output is determined by the four latch out- 
puts of the receiver. Thus, if the driver is enabled, parity is 
generated and if the driver is in the high-impedance state, the 
BUS parity is checked. 



LOGIC SYMBOL 



3 7 13 17 



Ao Ai A2 
DRCP 



BUSo BUSi BUS2 BUS3 



TTTT 

4 6 14 16 



V CC = P ' n 20 
GND 1 = Pin 5 
GN Do = Pin 15 



ODD 


10 


Ro 




R1 


8 


"2 


12 


R3 


IB 



CONNECTION DIAGRAM 
Top View 



Rod 

BUSoQ 
BUS,[^ 

»c 

oodQ 



□ vcc 
I] 0BCP 

>> 

□ A3 

□ bus 3 

^ GND2 
™] BUS2 

□ A 2 

□ "2 

□ 51 



Note: Pin 1 is marked for orientation. 



4-119 




MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 



-65 C to +150 C 



Temperature (Ambient) Under Bias 



-55 C to +125 C 



Supply Voltage to Ground Potential 



-0.5 V to +7 V 



DC Voltage Applied to Outputs for HIGH Output State 



-0.5 V to +Vqc max. 



DC Input Voltage 



-0.5 V to +7 V 



DC Output Current, Into Outputs (Except BUS) 


30 mA 


DC Output Ci 


rrent. Into Bus 


100 mA 


DC Input Current 


-30 mA to +5.0 mA 







ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 

Am2917AXC (COM'LI T A = 0°C to +70°C V cc Ml N. = 4. 75 V V cc MAX. - 5.25 V 

Am291 7AXM (Ml LI T A = -55°C to + 1 25° C V cc Ml N. = 4.50 V V cc MAX. = 5.50 V 

BUS INPUT/OUTPUT CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

Parameters Description Test Conditions (Note 1) Min. Typ. 



Max. 



Units 



vol 


Bus Output LOW Voltage 


V CC = MIN. 


Iql = 24 mA 






0.4 


Volts 


Iql = 48mA 






0.5 


v 0H 


Bus Output HIGH Voltage 


V CC = MIN. 


COM'L, l H - -20mA 


2.4 






Volts 


MIL, Iqh = -15mA 


•o 


Bus Leakage Current 
(High Impedance) 


V CC * MAX. 
Bus enable = 2.4 V 


V = 0.4 V 






-200 




V = 2.4V 






50 


V =4.SV 






100 


"OFF 


Bus Leakage Current 
(Power OFF) 


V =4.5V 

v cc =ov 






100 


ma 


V| H 


Receiver Input HIGH Threshold 


Bus enable = 2.4 V 


2.0 






Volts 


V|L 




Receiver Input LOW Threshold 


Bus enable = 2.4 V 


COM'L 






0.8 


Volts 


MIL 






0.7 


'sc 




Bus Output Short Circuit Current 


V CC " MAX. 
V =0V 


-SO 


-120 


-225 


mA 



4-120 



Am2917A 

ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 
Am2917AXC (COM'L) T A = 0°C to + 70°C 
Am2917AXM (MIL) T A = -55°C to +1 25°C 

DC CHARACTERISTICS OVER 

Parameters Description 



'cc 



Ml N. 



V CC MIN. 



4.75 V 
4.50 V 



■ 5.25 V 

■ 5.50V 



G TEMPERATURE RANGE 

Test Conditions (Note D 



Min. 



Typ. 

(Note 2) 



Max. 



Units 



VOH 




Receiver 

Output HIGH Voltage 


V CC = MIN. 
V|N = V IL ° r V IH 


MIL: l H = -1-OmA 


2.4 


3.4 




Volts 


COM'L: l 0H - -2.6mA 


2.4 


3.4 




V CC = 5.0 V, l H = -100mA 


3.5 






Vqh 




Parity 

Output HIGH Voltage 


V CC = MIN., I 0H = -660 (iA 
V|N = V IH or V| L 


MIL 


2.5 


3.4 




Volts 


COM'L 


2.7 


3.4 




vol 




Output LOW Voltage 
(Except Bus) 


V cc - MIN. 

V| N = V| L or V m 


'OL 4.0mA 




0.27 


0.4 


Volts 


lOL = 8.0mA 




0.32 


0.45 


l 0L = 12mA 




0.37 


0.5 


V|H 




Input HIGH Level 
(Except Bus) 


Guaranteed input logical HIGH 
for all inputs 


2 






Volts 


V IL 




Input LOW Level 
(Except Bus) 


Guaranteed input logical LOW 
for all inputs 


MIL 






0.7 


Volts 


COM'L 






0.8 


V| 




Input Clamp Voltage (Except Bus) 


Vcc * MIN., I|M = -18mA 






-1.2 


Volts 


Ml 




Input LOW Current (Except Bus) 


Vcc - MAX., V|M = 0.4 V 


BE, RLE 






-0.72 


mA 


All other inputs 






-0.36 


■ih 




Input HIGH Current (Except Bus) 


V CC = MAX., V| N = 2.7 V 






20 


mA 


•l 




Input HIGH Current (Except Bus) 


Vcc = MAX., V| N = 7.0V 






100 


mA 


!SC 




Output Short Circuit Current 
(Except Bus) 


V CC " MAX. 


RECEIVER 


-30 




-130 


mA 


PARITY 


-20 




-100 


'cc 




Power Supply Current 


Vcc ' MAX. 




63 


95 


mA 


"0 




Off -State Output Current 
(Receiver Outputs) 


V C C = MAX. 


V = 2.4 V 






50 


M A 


V = 0.4 V 






-50 



SWITCHING CHARACTERISTICS OVER 
OPERATING TEMPERATURE RANGE 



Parameters 



Description 



Test Conditions 



Am2917AXM 
Typ. 

Min. (Note 2) Max. 



Am2917AXC 
Typ. 

Min. (Note 2) Max. 



Units 



«PHL 



<PLH 



«ZH.«ZL 



'HZ.'LZ 



Driver Clock (DRCP) to Bus 



Bus Enable (BE) to Bus 



C L (BUS) = 50pF 
R L BUS) = 130S2 



21 



36 



21 



32 



tpw 



«PLH 



<PHL 



*PLH 



«PHL 



'PLH 



«PHL 



«PLH 



<PHL 



•PLH 



*PHL 



'ZH.«ZL 



'HZ. ILZ 



A Data Inputs 



8.0 



Clock Pulse Width (HIGH) 



Bus to Receiver Output 
(Latch Enabled) 



20 



18 



18 



Latch Enable to Receiver Output 



33 



21 



30 



Bus to Latch Enable (RLE) 



A Data to Odd Parity Out 
(Driver Enabled) 



C L = 15pF 
R|_ = 2.0kSJ 



46 



32 



Bus to Odd Parity Out 
(Driver Inhibit) 



21 



21 



Latch Enable (RLE) to Odd 
Parity Output 



Output Control to Output 



C L =5pF, R L = 2.0kn 



14 



26 



14 



27 



32 



32 



Notes: 1 . For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable devit 

2. Typical limits are at V cc = 5.0 V, 25"c ambient and maximum loading. 

3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 

4-121 



INPUT/OUTPUT CURRENT 
INTERFACE CONDITIONS 



Am2917A 



DRIVEN INPUT 



DRIVING OUTPUT 




Note: Actual current flow direction shown. 



SWITCHING TEST CIRCUIT 




C L = 15pF fort PLH ,tpHL. 

( ZL. tZH 
C L = 5pF for t HZ , t|_Z 



SWITCHING WAVEFORMS 



7 


I \ 7 


f 




\ }/////////// 


w 



3.0V 
1.3V 



3.0V 
T.3V 



■ v 0H 

■ 1.3V 



Note: Bus to Receiver output delay is measured by clocking data into the driver register 
and measuring the BUS to R combinatorial delay. 



4-1 22 



Am2917A 



FUNCTION TABLE 



H = HGH 
L - LOW 



INTERNAL 
TO DEVICE 



BUS OUTPUT 



BUS; 



Driver output disable 



Receiver output disable 



Driver output disable and 
receive data via Bus input 



Latch received data 



Load driver register 



No driver clock restrictions 



Z - HIGH 
NC- 



Impedance X - Don't car 
t - LOW to h 



■0.1.2.3 



Metallization and Pad Layout 



31- 



R 2 



A 3 
BUSq * 



BUS] 6 
At 7 



R 1 8 



mm 



mmm 



BE 9 



1? A 3 
16 BUS 3 



15 GND 2 



14 aus 2 

13 A 2 



DIE SIZE .074" X .130" 



ORDERING INFORMATION 



Order the part number according to the table below to obtain the de- 
sired package, temperature range, and screening level. 




Type 
(Note 1) 



Temperature 
Range 
(Note 2) 



Screening 

Level 
(Note 3) 



AM2917APC 

AM2917ADC 

AM2917ADC-B 

AM2917ADM 

AM2917ADM-B 

AM2917AFM 

AM2917AFM-B 

AM2917AXC 
AM2917AXM 



P-20 
D-20 
D-20 
D-20 
D-20 
F-20 
F-20 

Dice 
Dice 



C 
C 

c 

M 
M 
M 
M 

C 
M 



C-1 
C-1 
B-1 
C-3 
B-3 
C-3 
B-3 

Visual inspection 
to MIL-STD-883 
Method 201 OB. 



Notes: 

1. P = Molded DIP, D = Hermetic DIP, F = Flat Pak. Number follow- 
ing letter is number of leads. See Appendix B for detailed outline. 
Where Appendix B contains several dash numbers, any of the var- 
iations of the package may be used unless otherwise specified. 

2. C = 0°C to +70°C, M = -55°C to +125°C. 

3. See Appendix A for details of screening. Levels C-1 and C-3 con- 
form to MIL-STD-883, Class C. Level B-3 conforms to MIL-STD- 
883, Class B. 



DEFINITION OF FUNCTIONAL TERMS 

DRCP Driver Clock Pulse. Clock pulse for the driver register. 

BE Bus Enable. When the Bus Enable is LOW, the four 
drivers are in the high impedance state. 

BUSo, BUSi, BUS2, BUS3 The four driver outputs and 
receiver inputs (data is inverted). 

R0. R 1. R 2. R 3 Tne four receiver outputs. Data from the 
bus is inverted while data from the A or B inputs is non- 
inverted. 

RLE Receiver Latch Enable. When RLE is LOW, data on the 
BUS inputs is passed through the receiver latches. When RLE 
is HIGH, the receiver latches are closed and will retain the 
data independent of all other inputs. 

ODD Odd parity output. Generates parity with the driver 
enabled, checks parity with the driver in the high-impedance 
state. 

OE Output Enable. When the OE input is HIGH, the four 
three-state receiver outputs are in the high-impedance state. 



PARITY OUTPUT FUNCTION TABLE 



BE 


ODD PARITY OUTPUT 


L 
H 


ODD = Ao ® A1 ® A2 ® A3 

ODD = Qq ffl Q1 ® Q2 <B Q3 



4-123 



Am2917A 



APPLICATIONS 



SBUS 



I/O 
BUS 



Am2917A 

DATA BUS 
REGISTER 



BUS Am2917A 



Am2917A 
ADDRESS REGISTER 



MAIN 
MEMORY 



Am2909 
MICROPROGRAM 
SEQUENCER 



Am2918 
STATUS REGISTER 



I Am2901 
BIPOLAR 
MICROPROCESSOR 



R BUS 




The Am2917A can be used as an I/O Bus Transceiver and Main Memory I/O Transceiver 
in high-speed Microprocessor Systems. 



iz 



Am291?A 



1Z 



Am2917A 

~7V~ 



Am8T26 



1LJLJL D 



Am2917A 



iz 



Am2917A 



Am8T26 



1Z 



lz 



iz 



_sz_ 



Using the Am2917A and Am8T26 in a terminated Bus system for the Am9080 MOS Microprocessor. 



4-124 



Am3212*Am8212 

Eight-Bit Input/Output Port 



Distinctive Characteristics 

• Fully parallel, 8-bit data register and buffer replacing 
latches, multiplexers and buffers needed in micro- 
processor systems. 

• 4.0V output high voltage for direct interface to MOS 
microprocessors, such as the Am9080A family. 

• Input load current 250/uA max. 

• Reduces system package count 



• Available for operation over both commercial and 
military temperature ranges. 

• Advanced Schottky processing with 100% reliability 
assurance testing in compliance with Ml L-STD-883. 

• Service request flip-flop for interrupt generation 

• Three-state outputs sink 15mA 

• Asynchronous register clear with clock over-ride 



FUNCTIONAL DESCRIPTION 

All of the principal peripheral and input/output functions 
of a Microcomputer System can be implemented with the 
Am3212 • Am8212. The Am3212 • Am8212 input/output 
port consists of an 8-latch with 3-state output buffers along 
with control and device selection logic, which can be used to 
implement latches, gated buffers or multiplexers. 



DEVICE 
SELECTION 



LOGIC DIAGRAM 

SERVICE 
PV, REQUEST FF 




DATA LATCHES - 



Dl, ■ 



-c£>o- 



ACTIVE L( 



=6>- 



CONNECTION DIAGRAM 
Top View 







* 




24 


Zl v cc 




MP | 


2 




23 


| iNT 






3 




22 


Z] D '8 




°°l[Z 


4 




21 






D'2|Z 


5 




20 






D ° 2 [Z 


6 


Am3212 
Am8212 


19 
18 


Zlo'e 






8 




17 


ZI D °6 




°u|Z 







16 


□ ois 




DQ 4 | 


10 




15 


Z] D °5 




STB | 






14 


|CLR 




gndI 


12 




13 


Z]DS 2 




Note: P 


n 1 


is marked for 


orientation. 


PIN DEFINITION 


Dh- 


Dl 8 


DATA IN 


DO-| 


-DOg 


DATA OUT 


DlTj- 


-DS 2 


DEVICE SELECT 


MD 


MODE 


STB 


STROBE 


iNT 


INTERRUPT (ACTIVE LOW) 


CLR 


CLEAR (ACTIVE LOW) 



ORDERING INFORMATION 

Package Temperature Order 

Type Range Number 



Hermetic DIP 
Hermetic DIP 

Molded DIP 

Dice 
Hermetic DIP 
Hermetic DIP 

Molded DIP 



-55 C to +125 C 
0°C to +70°C 
0°C to +70°C 
0°C to +70°C 
0°C to +70°C 

-55°C to +125°C 
0°C to +70° C 



AM8212DM 
D8212 
P8212 

AM8212XC 
D3212 
MD3212 
P3212 



4-125 



Am3212/Am8212 



FUNCTIONAL DESCRIPTION (Cont'd) 



Data Latch 

The 8 flip-flops that make up the data latch are of a "D" type 
design. The output (Q) of the flip-flop will follow the data 
input (D) while the clock input (C) is high. Latching will occur 
when the clock (C) returns low. 

The d ata latch is cleared by an async hrono us reset input 
(CLR). (Note: Clock (C) Overrides Reset (CLR)). 



Output Buffer 



The outputs of the data latch (Q) are connected to 3-state, 
non-inverting output buffers. These buffers have a common 
control line (EN); this control line either enables the buffer 
to transmit the data from the outputs of the data latch (Q) 
or disables the buffer, forcing the output into a high im- 
pedance state. (3-state). This high-impedance state allows the 
Am3212 • Am8212 to be connected directly onto the micro- 
processor bi-directional data bus. 

Control Logic 

The Am3212 • Am8212 has control inputs DS-), DS2, MD 
And STB. These inputs are used to control device selection, 
data latching, output buffer state and service request flip-flop. 

DS-,, DS 2 (Device Select) 

These 2 inputs are used for device selection. When DSi is low 
and DS2 is high (DS-| ■ DS2) the device is selected. In the 
selected state the output buffer is enabled and the service 
request flip flop (SR) is asynchronously set. 



MD (Mode) 

This input is used to control the state of the output buffer and 
to determine the source of the clock input (C) to the data 
latch. 

When MD is high (output mode) the output buffers are en- 
abled and the source of clock (C) to the data latch is from the 
device selection logic (DS-) • DS2). 

When MD is low (input mode) the output buffer state is 
determined by the device selection logic (DSi • DS2) and the 
source of clock (C) to the data latch is the STB (Strobe) input. 

STB (Strobe) 

This input is used as the clock (C) to the data latch for the 
input mode MD = 0) and to synchronously reset the service 
request flip-flop (SR). 

Note that the SR flip-flop is negative edge triggered. 
Service Request Flip-Flop 

The SR flip-flop is used to generate and control interrupts 
in microcomputer systems. It is asynchronously set by the 
CLR input (active low). When the (SR) flip-flop is set it is in 
the non-interrupting state. 

The output of the (SR) flip-flop (Q) is connected to an in- 
verting input of a "NOR" gate. The other input to the "NOR" 
gate is non-inverting and is connected to the device selection 
logic (DSi • DS 2 ). The output of the "NOR" gate (INT) is 
active low (interrupting state) for connection to active low 
input priority generating circuits. 



TRUTH TABLE 



STB 


MD 


DS, - DS 2 


Data Out Equals 











Three-State 


1 








Three-State 





1 





Data Latch 


1 


1 





Data Latch 








1 


Data Latch 


1 





1 







1 


1 


Data In 


1 


1 


1 


Data In 



CLR 


DS-, -DS 2 


STB 


SR* 


INT 











1 


1 





1 





1 





1 


1 


A. 








1 


1 





1 





1 








1 


1 


1 


1 




1 


























:LR — Resets Data Latch 

- Sets SR Flip-Flop (no affect on Output Buffer) 
Internal SR Flip-Flop 



4-126 



Am3212/Am8212 

MAXIMUIVI RATINGS (Above which the useful life may be impaired) 



Storage Temperature 






-65°C to +150°C 


Tpmnprati irp /Amhipnt^ llnrtpr Ria^ 






— 55°C to +125°C 


Supply Voltage 






-0.5V to +7.0V 


Output Voltage 






-0.5V to +7.0V 


Input Voltages 






-1.0V to +5.5V 


Output Current (Each Output) 







125 mA 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (Unless Otherwise Noted) 

P8212, D8212, P3212, D3212 (COM'L) T A = 0°C to +70°C Vcc = 5.0V ± 5% 

Am8212DM, MD3212 (MIL) T A = -55°C to +1 25°C V C C=5.0V±10% 

DC CHARACTERISTICS 

Typ. 

Parameters Description Test Conditions Min. (Note 11 Max. Units 



'F 




Input Load Current 

ACK, DS 2 , CR, Dl i - Dig Inputs 


V F = 0.45V 






-0.25 


mA 






Input Load Current MD Input 


V F = 0.45V 






-0.75 


mA 


if 




Input Load Current DS^ Input 


V F - 0.45V 






-1.0 


mA 


IR 




Input Leakage Current 

ACK, DS, CR, Dl i - Dig Inputs 


V R = 5.25V 






10 


MA 


'R 




Input Leakage Current MO Input 


V R = 5.25V 






30 


m a 


"R 




Input Leakage Current DSi Input 


Vr - 5.25V 






4 


fA 


v c 




Input Forward Voltage Clamp 


IC = -5.0mA 


COM'L 






-1.0 


Volts 


MIL 






-1.2 






Input LOW Voltage 




COM'L 






0.85 


Volts 


MIL 






0.80 


V| H 




Input HIGH Voltage 




2.0 






Volts 


vol 




Output LOW Voltage 


IqL = 1 5mA 






0.45 


Volts 


V H 




Output HIGH Voltage 


'OH = —1.0mA 


COM'L 


3.65 


4.0 




Volts 


MIL 


3.3 


4.0 




IQH = —0.5mA 


MIL 


3.4 


4.0 




'sc 




Short Circuit Output Current 


V = OV 


-15 




-75 


mA 


liol 




Output Leakage Current 
High Impedance 


V = 0.45V/5.25V 






20 


MA 


'cc 




Power Supply Current 


Note 2 




90 


130 


mA 



AC CHARACTERISTICS (Note 3) 



Parameters 


Description 


Min. 


(Note 1) 


Max. 


Units 


tpw 




Pulse Width 


30 


8 




ns 


tpd 




Data to Output Delay 




12 


30 


ns 


*we 




Write Enable to Output Delay 




18 


40 


ns 


'set 




Data Set-up Time 


15 






ns 


*h 




Data Hold Time 


20 






ns 


*r 




Reset to Output Delay 




18 


40 


ns 


*s 




Set to Output Delay 




15 


30 


ns 


*e 


Output Enable/Disable Time 




14 


45 


ns 


*c 


Clear to Output Delay 




25 


55 


ns 



CAPACITANCE (Note 4) 

F = 1.0MHz, V B | AS - 2.5 V, V cc = +5.0V, T A - 25° C 



TEST LOAD (15mA and 30pF) 



Parameters 


Description 


Typ. 


Max. 


Units 


C|N 


DSi MD Input Capacitance 


9.0 


12 


pF 


C|N 


DS 2 , CK, ACK, Dl! -Dig 
Input Capacitance 


5.0 


9.0 


pF 


COUT 


DO^ — DOg Output Capacitance 


8.0 


12 


pF 



NoT.es: 1. 
2. 
3. 



Typical limits are at Vcc 
CLR = STB = HIGH; DSi 



Conditions of Test: 



■ 5 0V, 25 C ambient an 

■ DS, 



naximum loading. 
: MD = LOW; all data inputs are gound, all data outputs are open. 



T 



a) Input pulse amplitude = 2.5V 

b) Input rise and fall times 5.0ns 

c) Between 1 .OV and 2.0V measurements made at 1.5V with 1 5mA and 30pF Test Load. 
4. This parameter is sampled and not 100% tested. 



'Including Jig and Probe 
Capacitance. 



4-127 



Am3212/Am8212 




4-128 



Am3212/Am8212 




Input Current Versus 
Input Voltage 



TYPICAL CHARACTERISTICS 

Output Current Versus 
Output LOW Voltage 



Output Current Versus 
Output HIGH Voltage 



-3-2-10 1 2 
INPUT VOLTAGE - VOLTS 



v cc- 


5.0V 
















T A ■ 75-C 












T A = 0°C 









-30 
-35 



v cc 


5.0V 


















_ T A" 


75 D C 














»5°C — 








HT A" 
= 0°C— 






— T A 

















OUTPUT LOW VOLTAGE - VOLTS 



1.0 2.0 30 4.0 5.0 
OUTPUT HIGH VOLTAGE — VOLTS 



Data to Output Delay 
Versus Load Capacitance 





5.0V 
25"C 


































r 

























50 100 150 200 250 300 
LOAD CAPACITANCE - pF 



Data to Output Delay 
Versus Temperature 



25 50 75 100 
TEMPERATURE - °C 



Write Enable to Output Delay 
Versus Temperature 




TEMPERATURE - 



LOGIC SYMBOLS 



INPUT DEVICE 



OUTPUT DEVICE 



STB 






Dl 


DO 








6 






8 






10 


Am3212 




15 


Am8212 




17 






19 






21 


CLR 


INT 


23 


DS, MD DS 2 







LIC-429 



TU7 



Detailed 



Am3212 
Am8212 



TT 



Symbolic 



Am3212 
Am8212 



Am3212 
Am8212 



TT 



TT 



4-129 



Am3212/Am8212 



TYPICAL APPLICATIONS OF THE Am8212 



GATED BUFFER (3-STATE) 

By tying the mode signal low and the strobe input high, the 
data latch is acting as a straight through gate. The output 
buffers are then enabled from the device selection logic DSi 
and DS 2 . 

When the device selection logic is false, the outputs are 3-state. 

When the device selection logic is true, the input data from the 
system is directly transferred to the output. 



INPUT | 
DATA ' 
(250/iAl < 



A ) 

I > [/ 





STB 




Am3212 




Am8212 


CLR 





XI 



OUTPUT 
DATA 
115mA) 
13.65V MIN.) 



Bi-Directional Bus Driver 



Two Am3212 • Am8212's wired back-to back can be used as 
a symmetrical drive, bi-directional bus driver. The devices are 
controlled by the data bus input control which is connected 
to DSi on the first Am3212 • Am8212 and to DS2 on the 
second. While one device is active, and acting as a straight 
through buffer the other is in its 3-state mode. 



DATA ( 
BUS 



DATA BUS 
CONTROL 





STB 












Am3212 




Am8212 


CLR 





IT 
1 



Am3212 
Am8212 



V 



Interrupting Input Port 

The Am3212 • Am8212 accepts a strobe from the system 
input source, which in turn clears the service request flip-flop 
and interrupts the processor. The processor then goes through 
a service routine, identifies the port, and causes the device 
selection logic to go true - enabling the system input data 
onto the data bus. 



SYSTEM f N, 

INPUT \ / 



PORT A— 
SELECTION \ 
(DS 1 -DS 2 > J— 



Am3212 
Am8212 



JT 



4-130 



Am3212/Am8212 



TYPICAL APPLICATIONS OF THE Am8212 (Cont'd) 



Interrupt Instruction Port 

The Am3212 • Am8212 can be used to gate the interrupt 
instruction, normally RESTART instructions, onto the data 
bus. The device is enabled from the interrupt acknowledge 
signal from the microprocessor and from a port selection sig- 
nal. This signal is normally tied to ground. (DSi could be 
used to multiplex a variety of interrupt instruction ports onto 
a common bus). 



RESTART 
INSTRUCTION 
(RSTO- RST7) . 





STB 




Am3212 




Am8212 


CLR 





Output Port (With Hand-Shaking) 

The Am3212 • Am8212 is used to transmit data from the 
data bus to a system output. The output strobe could be a 
hand-shaking signal such as "reception of data" from the de- 
vice that the system is outputting to. It in turn, can interrupt 
the system signifying the reception of date. The selection of 
the port comes from the device selection logic. (DSi ■ DS2). 



- OUTPUT STROBE 



STB 




Am3212 




Am8212 




INT 


CLR 



SYSTEM OUTPUT 



■ SYSTEM RESET 



PORT SELECTION 
I LATCH CONTROL) 
(DS,-DS 2 > 

LIC-437 



Am9080A Status Latch 



The input to the Am3212 • Am8212 latch comes directly 
from the Am9080A data bus. Timing shows that when 
the SYNC signal is true (DS1 input), and $1 is true. 



An,9080A D 5 
°6 

SYNC 
DBIN 



(DS1 input) then the status data will be latched into the 
Am3212 • Am8212. The mode signal is tied high so that 
the output on the latch is active and evabled all the time. 



STATUS LATCH 



Am3212 
Afn8212 



CLR 

DS 2 



- iNTA 

- WO 

■ STACK 

- HLTA 

■ OUT 

- Ml 



>LT\ 

* ; /~r\ 



— BASIC , 
CONTROL ' 
BUS 



"V" 



V CC 



4-131 



Am3216 • Am3226 • Am8216 • 

Four-Bit Parallel Bidirectional Bus Driver 



Distinctive Characteristics 

• Data bus buffer driver for 8080 type CPU's 

• Low input load current — 0.25mA maximum 

• High output drive capability for driving system data 
bus - 50mA at 0.5V 

• 100% rel ability assurance testing in compliance with 
MIL-STD-883 



Am3216 



and Am8216 have non-inverting outputs • Am3226 and Am8226 have inverting outputs 



• Output high voltage compatible with direct interface 
to MOS 

• Three-state outputs 

• Advanced Schottky processing 

• Available in military and commercial temperature 
range 



FUNCTIONAL DESCRIPTION 

The Am3216, Am3226, Am8216 and Arr>8226 are four-bit, 
bi-directional bus drivers for use in bus oriented applications. 
The non- nverting Am3216 and Am8216, and inverting 
Am3226 and Am8226 drivers are provided for flexibility in 
system design. 

Each buffered line of the four bit driver consists of two 
separate buffers that are three-state to achieve direct bus inter- 
face and bi-directional capability. On one side of the driver the 
output of one buffer and the input of another are tied together 
(DB), this side is used to interface to the system side com- 
ponents such as memories, I/O, etc., because its interface is 
TTL compatible and it has high drive (50mA). On the other 
side of the driver the inputs and outputs are separated to 
provide maximum flexibility. Of course, they can be tied 



together so that the driver can be used to buffer a true bi-direc- 
tional bus. The DO outputs on this side of the driver have a 
special high voltage output drive capability so that direct inter- 
face to the 8080 type CPUs is achieved with an adequate 
amount of noise immunity. 

The CS input is a device enable. When it is "high" the output 
drivers are all forced to their high-impedance state. When it is 
a "LOW" the device is e nabled and the direction of the data 
flow is determined by the DIEN input. 



The DIEN input controls the direction of data flow which is 
accomplished by forcing one of the pair of buffers into its high 
impedance state and allowing the other to transmit its data. A 
simple two gate circuit is used for this function. 



Am3216 • Am8216 



LOGIC DIAGRAMS 



Am3226 • Am8226 




DO, o- 




ORDERING INFORMATION 



Package 
Type 



Temperature 
Range 



Am3216 
Am8216 
Order 
Number 



Am3226 
Am8226 
Order 
Number 



Hermetic DIP 
Hermetic DIP 

Molded DIP 
Hermetic DIP 
Hermetic DIP 

Molded D F 
Dice 



-55 C to +125 C 
0°C to +70°C 
0°C to +70°C 

-55°C to +125°C 
0°C to +70°C 
0°C to +70°C 



MD3216 
D3216 
P3216 

MD8216 
D8216 
P8216 



0Cto+70°C AM8216XC 



MD3226 

D3226 

P3226 
MD8226 

D8226 

P8226 
AM8226XC 



CONNECTION DIAGRAM 
Top View 



CHIP SELECT CS LZ 
DATA OUTPUT DO Q Q 
DATA BUS _ 
BI-DIRECTIONAL °l — 

DATA INPUT DI Q Q 
DATA OUTPUT DO, 

DATA BUS _ 
BI-DIRECTIONAL UH l| 

DATA INPUT Dl, 

slote: Pin 1 is marked gnd I 
for orientation. 



16 □ v cc 



Am3216 
Am3226 
Am8216 
Am8226 



DATA IN ENABLE 
(DIRECTION CONTROL) 
D0 3 DATA OUTPUT 



1 Dl 3 DATA INPUT 



10 

9 



, DATA OUTPUT 



DATA BUS 
2 BI-DIRECTIONAL 



DATA INPUT 



4-132 



Am32 1 6/3226/821 6/8226 

MAXIMUM RATINGS (Above which the useful life may be impaired) 



Temperature (Ambient) Under Bias —55 C to +125 C 

Storage Temperature —65 C to +1 50 C 



AW Output and Supply Voltages -0.5 V to +7.0 V 



All Input Voltages -1.0Vto+5.5V 



Output 



Currents 125 mA 



Am3216, Am3226, Am8216 AND Am8226 MILITARY 

ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (-55°Cto +125°C) 
The following conditions apply unless otherwise specified: 

MD3216, MD8216, MD3226, MD8226 (MIL) T A = -55°C to +1 25° C V cc - 5.0V ± 1 0% 

DC CHARACTERISTICS 



Typ. 

Parameters Description Test Conditions Min. (Note i) Max. Units 



•fi 


Input Load Current Dl EN, CS 


V F - 0.45 




-0.15 


-0.5 


mA 


«F2 


Input Load Current Alt Other Inputs 


V F = 0.45 




-0.08 


-0.25 


mA 


"R1 


Input Leakage Current DIEN, CS 


V R - 5.5V 






80 


M A 


IR2 


input Leakage Current Dl Inputs 


V R = 5.5V 






40 


MA 


v c 


Input Forward Voltage Clamp 


IC = -5.0mA 






-1.2 


Volts 


V| L 


Input LOW Voltage 


Am3216. 
Am8216 








0.95 


Volts 


Am3226. 
Am8226 








0.9 


V| H 


Input HIGH Voltage 




2.0 






Volts 


'O 


Output Leakage Current 
(Three-State) 


DO 


V = 0.45V/5.5V 






20 


MA 


DB 






100 


ice 


Power Supply Current 


Am3216, 
Am8216 






95 


130 


mA 


Am3226, 
Am8226 







85 


120 


VOL1 


Output LOW Voltage 


DO Outputs Iql = 15mA 
DB Outputs Iql = 25mA 




0.3 


0.45 


Volts 


VOL2 


Output LOW Voltage 


DB Outputs Iql = 45mA 




0.5 


0.6 


Volts 


v OH1 


Output HIGH Voltage 


DO Outputs 


lOH = -0.5mA 


3.4 


4.0 




Volts 


'OH " -2.0mA 


2.4 






VOH2 


Output HIGH Voltage 


DB Outputs Iqh = -5.0mA 


2.4 


3.0 




Volts 


'OS 


Output Short Circuit Current 


DO Outputs = 0V, V cc = 5.0V 


-15 


-35 


-65 


mA 


DB Outputs = 0V, Vcc = 50v 


-30 


-75 


-120 



AC CHARACTERISTICS 



Parameters Description Test Conditions Min. (Note i) Max. Units 



»PD1 


Input to Output Delay DO Outputs 


C L = 30pF. R-| = 300n, R 2 = 600« 




15 


25 


ns 




Input to Output Delay DB Outputs 


Am3216, Am8216 


C L =300pF, R-| =90n,R 2 = 18012 




20 


33 


ns 






Am3226, Am8226 




16 


25 






Am3216 


Note 3 




45 


75 




«E 


Output Enable Time 


Am8216 


Note 2 




45 


75 


ns 






Am3226, Am8226 


Note 3 




35 


62 




«D 


Output Disable Time 


Am3216, Am8216 


Note 4 




20 


40 




Am3226, Am8226 




16 


38 


ns 



4-133 



Am321 6/3226/821 6/8226 



Am3216, Am3226, Am8216 AND Am8226 COMMERCIAL 

ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (0°C to +70°C) 
The following conditions apply unless otherwise specified: 

D3216, D8216, D3226, D8226, P3216, P8216, P3226, P3226 (COM'L) T A - 0° C to + 70° C V cc - 5.0V ± 5% 

DC CHARACTERISTICS 



Parameters 


Description 




Test Conditions 


Min. 


Typ. 

(Note 1 ) 


Max. 


Units 


>F1 


I 


nput Load Current Dl EN, CS 


V F - 0.45 




-0.15 


-0.5 


mA 


'F2 


I 


nput Load Current All Other Inputs 


Vp = 0.45 




—0.08 


—0.25 


mA 


IR1 


I 


nput Leakage Current DIEN, CS 


Vp = 5.25V 






20 


uA 


'R2 


I 


nput Leakage Current Dl Inputs 


Vp; = 5.25V 






10 


uA 


v c 


I 


nput Forward Voltage Clamp 


Ifj - —5.0mA 






-1.0 


Volts 


V| L 


I 


nput LOW Voltage 








0.95 


Volts 


Vm 
In 


I 


nput HIGH Voltage 




2.0 






Volts 


I'ol 


Output Leakge Current 


DO 


V = 0.45V/5.5V 






20 


MA 


( 


Three-State} 


DB 








100 


'cc 


Power Supply Current 


Am3216, Am8216 






95 


130 


mA 


Am3226, Am8226 






85 


120 


VOL1 


C 


lutput LOW Voltage 


DB Outputs Iql = 15mA 
DB Outputs IOL = 25mA 




0.3 


0.45 


Volts 


v OL2 


c 


lutput LOW Voltage 


Am3216, Am8216 


DB Outputs Iql " 55mA 




0.5 


0.6 


Volts 




Am3226, Am8226 


DB Outputs Iql = 50mA 




0.5 


0.6 


v OH1 


c 


lutput HIGH Voltage 


DO Outputs Iqh = -1 -OmA COM'L 


3.65 


4.0 




Volts 


v OH2 


c 


lutput HIGH Voltage 


DB Outputs Ioh = -10mA 


2.4 


3.0 




Volts 


'OS 


c 


lutput Short Circuit Current 


DO Outputs a 0V 


-15 


-35 


-65 


mA 




DB Outputs Vcc = 50v 


-30 


-75 


-120 



AC CHARACTERISTICS 

Parameters 



Description 



Test Conditions 



Min. 



Typ. 

(Note 1) 



Max. Units 



«PD1 


I 


nput to Output Delay DO Outputs 


Cl = 30pF, Rt =3000, R 2 - 600JJ 




15 


25 


ns 


tpD2 


I 


nput to Output Delay DB Outputs 


Am3216, Am8216 


C L = 300pF,R 1 = 90f!, R 2 = 180S2 




20 


30 


ns 


Am3226, Am8226 




16 


25 


'E 


C 


lutput Enable Time 


Am3216 


Note 3 




45 


65 


ns 


Am8216 


Note 2 




45 


65 


Am3226, Am8226 


Note 3 




35 


54 


«D 


c 


lutput Disable Time 


Note 4 




20 


35 


ns 



TEST CONDITIONS 



TEST LOAD CIRCUIT 



Input pulse amplitude of 2.5V. 

Input rise and fall times of 5.0ns between 1 .0 and 2.0 volts. 
Output loading is 5.0mA and 10pF. 
Speed measurements are made at 1 .5V levels. 



OUT O- 



4-134 



Am321 6/3226/821 6/8226 



CAPACITANCE (Note 5) 
Parameters Description 


Test Conditions 


Min. 


Typ. 

(Note 1) 


Max. 


Units 


C|N 


Input Capacitance 


VBIAS • 2.5V, V CC = 5.0V 
T A - 25°C, f " 1.0MHz 




4.0 


8.0 


pF 


COUT1 


Output Capacitance 




6.0 


10 


pF 


COUT2 


Output Capacitance 




13 


18 


pF 



1 . Typical values are for T A = 25 C, Vqc = 5 v - 

2. DO outputs, C L - 30pF, R-, « 300/10kfi, R 2 - 180/1 .OkO; DB outputs, C L = 300pF, R, = 90/10k£l, R 2 - 180/1.0kS2. 

3. DO outputs, C L « 30pF, = 300/10kfi, R 2 » 600/I.Okfi; DB outputs, C L = 300pF, R-, - 90/10kIi, R 2 = 180/1 .Okfi. 

4. DO outputs, C L = 5.0 pF, R-, = 300/1 0kS2, R 2 = 600/1 .OkO; DB outputs, C L = 5.0 pF, fl^ = 90/1 0kS2, R 2 = 180/1.0kfi. 

5. This parameter is periodically sampled and not 1 00% tested. 



SWITCHING WAVEFORMS 



— 'PD^j 



OUTPUT 
ENABLE 



r*:1 




FUNCTION TABLE 



DIEN 


cs 




8216 


8226 


DB 


DO 


DB 


DO 


L 


L 


□ 1 =• DB 


Dl 


z 


Di 


z 


H 


L 


DB = DO 


Z 


DB 


Z 


DB 


L 


H 




Z 


Z 


Z 


z 


H 


H 




Z 


z 


z 


z 



' HIGH 
■ LOW 



TYPICAL APPLICATION 



l-DIRECTIONAL DATA BUS II 



MEMORY AND I/O INTERFACE TO A BI-DIRECTIONAL BUS 



4-135 



Am321 6/3226/821 6/8226 




4-136 



Am3448A 

IEEE-488 Quad Bidirectional Transceiver 



DISTINCTIVE CHARACTERISTICS 

• Four independent driver/receiver pairs 

• Three-state outputs 

• High impedance inputs 

• Receiver hysteresis - 600mV (Typ.) 
Fast Propagation Times - 50-20ns (Typ.) 

L compatible receiver outputs 
ngle +5 volt supply 

pen collector driver output option with internal passive 
pull up 

iwer up/power down protection (No invalid information 
transmitted to bus) 

No bus loading when power is removed from device 
ired termination characteristics provided 
'anced Schottky processing 
100% product assurance screening to MIL-STD-883 
iUirements 



GENERAL DESCRIPTION 

The Am3448A is a quad bidirectional transceiver meeting the 
requirement of IEEE-488 standard digital interface for pro- 
grammable instrumentation for the driver, receiver, and com- 
posite device load. One pull-up enable input is provided for 
each pair of transceivers which controls the operating mode of 
the driver outputs as either an open collector or active pull-up 
configuration. 

The receivers feature input hysteresis for improved noise im- 
munity in system applications. The device bus (receiver input) 
changes from standard bus loading to a high impedance load 
when power is removed. In addition no spurious noise is gen- 
erated on the bus during power-up or power-down. 




LOGIC DIAGRAM 




BUS 

C 



Package 
Type 



ORDERING INFORMATION 



Temperature 
Range 



Order 
Number 



Hermetic DIP 
Molded DIP 
Dice 



0°C to +70°C 
0°C to +70°C 
0°C to +70°C 



MC3448AL 
MC3448AP 
AM3448AX 



CONNECTION DIAGRAM 
Top View 



SEND/REC. 
INPUT A 

DATA A 
BUS A 



c 
c 
c 
c 

BUS B {Z. 
DATA B 
SEND/REC. r- 
INPUT B I— 

GND □ 



PULL-UP ENABLE 
INPUT A-B 



SEND/REC. 
INPUT D 



□ v cc 

□ 

□ DATA D 

□ BUSD 

— I PULL-UP ENABLE 
—I INPUT C-D 

□ BUSC 

□ DATA C 

□ ! 



Note: Pin 1 is marked for orientation. 



4-137 



Am3448A 

ABSOLUTE MAXIMUM RATINGS above which the useful life may be impaired 



Storage Temperature 


-65°C to +150°C 


Supply Voltagi 


3 7.0V 


Input Voltage 


5.5V 


Driver Output 


Current 


150mA 



ELECTRICAL CHARACTERISTICS 

The following conditions apply unless otherwise noted: 

Am3448A T A = 0°C to 70°C V cc MIN. = 4.75V V cc MAX. = 5.25V 

DC ELECTRICAL CHARACTERISTICS over operating temperature range 



Typ. 

Parameters Description Test Conditions Min. (Notei) Max. Units 



Bus Characteristics 


V (BUS) 




Bus Pin Open, V| (s / R) = 0.8V 


2.75 




3.7 


Volts 


V IC(BUS) 




Lia vuuaye 


'(BUS) - -12mA 






-1.5 


'(BUS) 


B 


js Current 


5.0V s V ( buS)« 5.5V 


0.7 




2.5 


mA 


V(BUS) = 0.5V 


-1.3 




-3.2 


V cc = 0V, OVs V, BUS) s 2.75V 






0.04 


Driver Char 


acteristics 


V IC(D) 


D 


river Input Clamp Voltage 


V|(S/R) = 2.0V, l ICID) = -18mA 






-1.5 


Volts 


V OH(D) 


Driver Output Voltage - High Logic State 


V|(S/R) = 2.0V, V| H(D ) = 2.0V, 
V IH (E) = 2 0V, l 0H = -5.2mA 


2.5 






Volts 


v OL(D) 


Driver Output Voltage - Low Logic State 


V| (S/R) = 2.0V, l 0L (D) = 48mA 






0.5 


Volts 


'OS(D) 





utput Short Circuit Current 


V I(S/R) = 2.0V, V IH ,D) = 2 0V 
V|H(E) = 2.0V 


-30 




-120 


mA 


V IH(D) 


D 


river Input Voltage - High Logic State 


V I(S/R) = 2.0V 


2.0 






Volts 


V IL(D) 


D 


river Input Voltage - Low Logic State 


V I(S/R) = 2.0V 






0.8 


Volts 


'i(D) 


D 


river Input Current - Data Pins 


V|(S/R) = V I(E ) = 2-OV 


0.5 s V|, DI « 2.7V 


-200 




40 


mA 


'lB(D) 


V|(D) = 5.5V 






200 


Receiver Characteristics 


V HYS(R) 


Receiver Input Hysteresis 


V|(S/R) = 8V 


400 


600 




mV 


V ILH(R) 


Receiver Input Threshold 


V I(S/R) = 8V . Low t0 Hi 3 h 




1.6 


1.8 


Volts 


V IHL(R) 


V I(S/R) = °- 8V . Hi 9 h ,0 Low 


0.8 


1.0 




V OH(R) 


Receiver Output Voltage - High Logic State 


V|(S/R) = 0.8V, l 0H(R) = -800mA, 
V(BUS)=2.0V 


2.7 






Volts 


V OL(R) 


Receiver Output Voltage - Low Logic State 


V| (S /R) = 0.8V, l 0L(R) = 16mA, V (BUS) = 0.8V 






0.5 


Volts 


'OSIR) 


Receiver Output Short Circuit Current 


V| (S /R) = 0.8V, V, BUS) = 2.0V 


-15 




-75 


mA 


Enable, Send/Receive Characteristics 


'l(S/R) 




0-5 « V I(S/R) s 2.7V 


-100 




20 


mA 


'|B(S/R) 


Input Current - Send/Receive 


V|(S/R) = 5.5V 






100 


'l(E) 




0.5 s V|,e) « 2.7V 


-200 




20 


mA 


'lB(E) 


Input Current - Enable 


V|(E) = 5.5V 






100 


Power Supply Current 


'CCL 


Power Supply Current 


Listening Mode - All Receivers On 




63 


85 


mA 


'CCH 


Talking Mode - All Drivers On 




106 


125 



Note 1. Typical limits are at V cc = 5.0V, 25°C ambient and maximum loading. 



4-138 



Am3448A 

SWITCHING CHARACTERISTICS (V cc = 5.0V, T A = 25°C unless otherwise noted) 

Parameters Description Test Conditions Min. Typ. Max. Units 



'PLH(D) 


Propagation Delay of Driver (Fig. 2) 


Output Low to High 


- 




15 


ns 


*PHL(D) 


Output High to Low 






17 


•PL 


1IR) 


Propagation Delay of Receiver (Fig. 1) 


Output Low to High 


- 




25 


ns 


VhL{R) 


Output High to Low 


- 




23 


tpHZ(R) 


Propagation Delay Time - Send/Receiver to Data 

(Rg. 4) 


Logic High to Third State 


_ 




30 


ns 


*PZH(R) 


Third State to Logic High 


_ 




30 


'PLZ(R) 


Logic Low to Third State 


- 




30 


'PZL(R) 


Third State to Logic Low 






30 


'PHZ(D) 


Propagation Delay Time - Send/Receiver to Bus 

(Rg. 3) 


Logic High to Third State 






30 


ns 


'PZH(D) 


Third State to Logic High 






30 


'PLZ(D) 


Logic Low to Third State 






30 


'PZL(D) 


Third State to Logic Low 






30 


'POFF(E) 


Turn-On Time - Enable to Bus (Fig. 5) 


Pull-Up Enable to Open Collector 






30 


ns 


*PO 


M(E) 


Open Collector to Pull-Up Enable 






20 



TRUTH TABLE 



Send/Rec. 


Enable 


Into Flow 


Comments 





X 


Bus —> Data 




1 


1 


Data ->Bus 


Active Pull-Up 


1 





Data -> Bus 


Open Collector 



X = Don't Care 



PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS 



TO SCOPE 

(OUTPUT) +5.0V 




lic 449 Figure 1. Bus Input to Data Output (Receiver). uc-450 



TO SCOPE 
3.0V (OUPUT) 2.3V 
O 



PULSE 
GENERATOR 




DRIVER INPUT 



tPLHID) — ~-| j— 

OUTPUT Jf 2 -°' 



C L ^ 30pF 

PULL-UP ENABLE 

•Includes Jig and Probe Capacitance. 

Figure 2. Data Input to Bus Output (Driver). 



tpMUQ] 



' Vol 



f = 1.0MHz 

'TLH = *THL s 5 0ns (10-909?) 
Duty Cycle = 509? 



4-139 



Am3448A 



PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS (Cont.) 



. Z L TO SCOPE 
(OUTPUT) 



1 



ZL SEND/ 
REC. 



TO SCOPE 
(INPUT) " 



PULL-UP 
ENABLE 



PULSE 
GENERATOR 



JT 



C L = 15pF (Includes Jig and Probe Capacitance) 



rr 



OUTPUT HIGH 
TO OPEN 



LOW OUTPUT 
TO OPEN 



2.0V 



3.0V 
0V 

V OH 

ov 



j^10 



•PLZID) — 



V z 1.1V 

'j 

n Vol 



V 



l PZL(D> 



1.1V 



f = 1.0MHz 

tTLH = <THL < 5.0ns (10-90%) 
Duty Cycle = 50% 



Figure 3. Send/Receive Input to Bus Output (Driver). 





TO SCOPE 
(OUTPUT) 5.0V 



-^ZL 



ZL SEND/ 
REC. 



TO SCOPE 
(INPUT) 



PULSE 
GENERATOR 




OUTPUT HIGH 
TO OPEN 



OUTPUT LOW 
TO OPEN 



tpZH(R) 



— — l PHZ(R) 



t_ 



V H 

OV 

5.0V 

Vol 



tpZLIR) 



C L = 15pF (Includes Jig and Probe Capacitance) 

Figure 4. Send/Receive Input to Data Output (Receiver). 



f = 1.0MHz 

*TLH - *THL 55 5.0ns (10-90%) 
Duty Cycle = 50% 



3.0V 




TO SCOPE 
(INPUT) 



PULSE 
GENERATOR 



SEND/ 
REC. 



TO SCOPE 
(OUTPUT) 



PULL-UP 
ENABLE 



JT I 51 




INPUT 
ENABLE 



tpON(E) 



3 



— H p tpOFFIEl 

V H 



^ 2.0V 9olT"^|^~~ 



Voc 



C L = 15pF (Includes Jig and Probe Capacitance) 

Figure 5. Enable Input to Bus Output (Driver). 



f = 1.0MHz 

'tlh = *thl 55 5.0ns (10-90%) 
Duty Cycle = 50% 



4-140 



Am3448A 



TYPICAL RECEIVER HYSTERESIS 
CHARACTERISTICS 



TYPICAL BUS LOAD LINE 



V c c - 5.0V 
t. - tK^r- 


















- 






• 
















































































































































- 
















V,. INPUT VOLTAGE - VOLTS 



V B US. s 



TYPICAL APPLICATION 



INSTRUMENT 
A 

(WITH GP-IB) 



INSTRUMENT 
B 

(WITH GP-IB) 



PROGRAMMABLE 
CALCULATOR 
(WITH GP-IB) 



16 LINES TOTAL 
(FOUR Am3448A S FOR EACH BUS INTERFACE) 



TYPICAL MEASUREMENT SYSTEM APPLICATION 



4-141 



Am54S/74S240 -Am54S/74S241 



Octal I 



Am54S/74S244 

.ine Receivers With Three-State Outputs 



DISTINCT VE CHARACTERISTICS 

• Three-state outputs drive bus lines directly 

• Advanced Schottky processing 

• Hysteresis at inputs improve noise margin 

• PNP inputs reduce D.C. loading on bus lines 

• V 0L of 0.55V at 64mA for Am74S; 48mA for Am54S 

• Data-to-output propagation delay times: 

Inverting - 7.0ns MAX 
Non-inverting - 9.0ns MAX 

• Enable-to-output - 15.0ns MAX 

• 100% reliability assurance testing in compliance with 
MIL-STD-883 

• 20 pin hermetic and molded DIP packages for Am54S/ 
74S240 Am54S/74S241, and Am54S/74S244 



FUNCTIONAL DESCRIPTION 

These buffers/line drivers, used as memory-address drivers, 
clock drivers, and bus oriented transmitters/receivers, pro- 
vide improved PC board density. The outputs of the com- 
mercial temperature range versions have 64mA sink and 
15mA source capability, which can be used to drive termi- 
nated lines down to 133H. The outputs of the military tem- 
perature range versions have 48mA sink and 12mA source 
current capability. 

Featuring 0.2V minimum guaranteed hysteresis at each 
low-current PNP data input, they provide improved noise 
rejection and high-fan-out outputs to restore Schottky TTL 
levels completely. 

The Am54S/74S240, Am54S/74S241 and Am54S/74S244 
have four buffers which are enabled from one common line, 
and the other four buffers are enabled from another common 
line. The Am54S/74S240 is inverting, while the Am54S/ 
74S241 and Am54S/74S244 present true data at the outputs. 

The Am54S/74S242 and Am54S/74S243 have the two 4-line 
data paths connected input-to-output on both sides to form 
an asynchronous transceiver/buffer with complementing 
enable inputs. The Am54S/74S242 is inverting, while the 
Am54S/74S243 presents non-inverting data at the outputs. 



Am54S/74S240 



Am54S/74S241 



CONNECTION DIAGRAMS 
Top Views 

Am54S/74S242 



Am54S/74S243 



Am54S/74S244 





7^ 


~^ 20 


□ V CC 


ran 


r* w 


20 


□ V CC 


sir 


,* 


14 


□ ^cc 




• 


14 


□ V CC 


tgL 


1» ^ 


20 


3 v cc 


1A1 Q 




19 


Zl 25 


1A1 |Z 


2 


19 


Z] 2G 


NC [Z 


2 


13 


Zl 2G 


NC |Z 


2 


13 


Zl 2G 


1A1 


2 


19 


Zl ^ 


2Y4 \2 


3 


18 


im 


2Y4 |Z 


3 


18 


□ ,y, 


TAT? Q 


3 


12 


Z] NC 


1A/Y |Z 


3 


12 


Z] NC 


2Y4 




18 


3,Y, 


1A2 Q 


4 




Z| 2A4 


1A2 [Z 


4 


17 


Z] 2A4 


2a7y [Z 


4 




Z] 8a7y 


2A/Y Q 


4 




Z] 8A/Y 


1A2 


4 


17 


Z] 2A4 


2Y3 \Z 




16 


Z] 1Y2 


2Y3 |Z 


5 


IS 


Z| 1Y2 


5a7y [Z 


5 


10 


Z] wy 


3A/Y Q 


5 


10 


Z] WY 


2Y3 fj 


5 


16 


□ ,Y2 


1A3 |Z 


6 


15 


Zl 2A3 


1A3 |Z 


6 


15 


Zl 2A3 


4A7y ^ 


6 


9 


□ 6A7Y 


4A/Y [Z 


6 


9 


Z| 6A/Y 


1A3 E 


6 


15 


Zl 2A3 


2Y2 Q 




14 


Z| 1Y3 


2Y2 Q 




14 


3 1Y3 


gnd[Z 




8 


Z] ^aTy 


GND Z 




8 


^5A/Y 


2Y2 Q 


7 


14 


Z| 1Y3 


1A4 [Z 


8 


13 


Z| 2A2 


1A4 Q 


8 


13 


Z| 2A2 








MPR-358 






1A4 Q 


a 


13 


Z| 2A2 


2Y1 |Z 


9 


12 


Z| 1Y4 


2Y1 [Z 


9 


12 


Z| 1Y4 


















2Y1 


9 


12 


Z| 1Y4 


GND 


10 


11 


Zl 2A1 


GND □ 


10 


11 


Z] 2A1 




Note: 


Pin 1 is marked for orientation. 






GND 


10 


11 


□ 2A, 



ORDERING INFORMATION 



Package 
Type 



Temperature 
Range 



Order Number 

Am54S/74S240 Am54S/74S241 Am54S/74S242 Am54S/74S243 Am54S/74S244 



Hermetic 

Dice 
Hermetic 
Molded 

Dice 



-55 C to + 125 C 
-55°C to +125°C 
0°C to +70° C 
0°C to +70°C 
0°C to +70°C 



SN54S240J 

AM54S240X 

SN74S240J 

SN74S240N 

AM74S240X 



SN54S241J 

AM54S241X 

SN74S241J 

SN74S241N 

AM74S241X 



SN54S242J 

AM54S242X 

SN74S242J 

AM74S242X 



SN54S243J 

AM54S243X 

SN74S243J 

AM74S243X 



SN54S244J 

AM54S244X 

SN74S244J 

SN74S244N 

AM74S244X 



4-142 



Am54S/74S240/241 /242/243/244 



Am54S/74S240 



LOGIC DIAGRAMS 



Am54S/74S24T 



Am54S/74S244 



i — 1^^° — ,y2 



G— 0^^> 



1A2 1Y2 2A2 



- 2Y1 1A1- 



-2Y3 1A3- 



■ 2V4 1A4 - 



-2Y2 1A2- 



■ — 1V2 2A2 



- 2Y4 1A4 - 



tg -o^^> 



LIC-461 



Am54S/74S242 



LIC-462 LIC-463 

Am54S/74S243 



, 





LIC-464 

Note: All gates have input hysteresis. 




MAXIMUM RATINGS above which the useful life may be impaired 



Storage Temperature 


-65°Cto +150°C 


Temperature (Ambient) Under Bias 


-55°Cto +125°C 


Supply Voltage to Ground Potential 


-0.5V to +7.0V 


DC Voltage Applied to Outputs for HIGH Output State 


-0.5V to +V CC max. 


DC Input Voltage 


-0.5V to +7.0V 


DC Output Current 


150mA 


DC Input Current 


-30mA to +5.0mA 



4-143 



Am54S/74S240/241/242/243/244 



ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Noted: 



Am54S240/S241 /S242/S243/S244 (MIL) T A - -55 C to +125 C V CC (M I N.) = 4.50 V 

Am74S240/S241/S242/S243/S244 (COM'L) T fl = 0° C to +70° C V cc ( M I N. ) = 4.75 V V cc 

ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

Parameters Description Test Conditions (Note 1) 



V CC (MAX.) ■ 
MAX.) • 



Min. 



5.50V 
5.25V 

Typ. 

(Note 2) 



Max. Units 



V|H 




High-Level Input Voltage 




2.0 






Volts 


VlL 




Low-Level Input Voltage 








0.8 


Volts 


V|K 




Input Clamp Voltage 


V C c = MIN., I| = -18mA 






-1.2 


Volts 






Hysteresis (Vj + - V~r-) 


V cc = MIN. 


0.2 


0.4 




Volts 


V H 




High-Level Output Voltage 


V C c = MIN - 
V| [_ = 8V 


COM'L, l H =-1mA 


2.7 






Volts 


lOH =-3mA 


2.4 


3.4 




V CC = MIN. 
V| L =0.5V 


MIL, Iqh = -12mA 


2.0 






COM'L, l OH = -15mA 


2.0 






vol 




Low-Level Output Voltage 


V cc = MIN. 
V| L = 0.8V 


MIL, Iql =48mA 






0.55 


Volts 


COM'L, Iql =64mA 






0.55 


'OZH 




Off-State Output Current, 
High-Level Voltage Applied 


V CC - MAX. 
V m =2.0V 
V| L -0.8V 


V • 2.4V 


'S240, 
'S241, 
'S244 






50 


MA 


'S242, 
'S243 






1 00 


"OZL 




Off -State Output Current, 
Low-Level Voltage Applied 


V =0.5V 


'S240, 
'S241, 
'S244 








'S242, 
'S243 






—500 


l| 




Input Current at Maximum 
Input Voltage 


V cc = MAX., V| = 5.5V 






1.0 


mA 


l|H 




High-Level Input Current, Any Input 


V cc = MAX., V m = 2.7V 






50 


„A 


'IL 




Low- Level Input Current 


Any A 


Vcc = MAX., V| L = 0.5V 






-400 


MA 


Any G 






-2.0 


mA 


!0S 




Short-Circuit Output Current (Note 3) 


V cc = MAX. 


-50 




-225 


mA 


'cc 




Supply Current 


Am54S/74S240 
Am54S/74S242 


All Outputs 
HIGH 


V CC = MAX. 
Outputs open 


MIL 




80 


123 


mA 


COM'L 




80 


135 


All Outputs 
LOW 


MIL 




1 00 


145 


COM'L 




1 00 


1 50 


Outputs at Hi-Z 


MIL 




100 


145 


COM'L 




100 


150 


Am54S/74S241 
Am54S/74S243 
Am54S/74S244 


All Outputs 
HIGH 


V cc = MAX. 
Outputs open 


MIL 




95 


147 


mA 


COM'L 




95 


160 


All Outputs 
LOW 


MIL 




120 


170 


COM'L 




120 


180 


Outputs at Hi-Z 


MIL 




120 


170 


COM'L 




120 


180 



Notes: 1 . For conditions shown as MIN. or MAX., use the appropriate value specified under recommended operating conditions. 

2. All typical values are Vcc = 5.0V, T*a = 25° C. 

3. Not more than one output should be shorted at a time, and duration of the short-circuit should not exceed one second. 



SWITCHING CHARACTERISTICS (V cc = 5V, T A = 25°C) 



Am54S/74S240/242 Am54S/74S241 /243/244 



'arameter 


Description 


Test Conditions 


Min. 


Typ. 


Max. 


Min. 


Typ. 


Max. 


Units 


<PLH 


Propagation Delay Time, 
Low-to-High-Level Output 






4.5 


7.0 




6.0 


9.0 


ns 


«PHL 


Propagation Delay Time, 
High-to-Low-Level Output 


C L a 50pF, R L » 900 (Note 3) 




4.5 


7.0 




6.0 


9.0 


ns 


tZL 


Output Enable Time to Low Level 






10 


15 




10 


15 


ns 


tZH 


Output Enable Time to High Level 






6.5 


10 




8.0 


12 


ns 


«LZ 


Output Disable Time from Low Level 


C L - 5.0pF, R L = 9052 (Note 3) 




10 


15 




10 


15 


ns 


'HZ 


Output Disable Time from High Level 




6.0 


9.0 




6.0 


9.0 


ns 



4-144 



Am54S/74S240/241/242/243/244 



LOAD CIRCUIT FOR 
THREE-STATE OUTPUTS 



VOLTAGE WAVEFORMS 
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS 




OUTPUT 
CONTROL 
(LOW LEVEL 
ENABLING) 



WAVEFORM 1- 



WAVEFORM 2- 



'EN Y\3V 
OSED / 



closedL 



ST&S2 ^ 
CLOSED 



| 0.5V 



Notes: 1. 



Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 

2. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 

3. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. PR Ft < 1 .OMHz, Zq UT « 50SI 
and t r < 2.5ns, tf < 2.5ns. 



FUNCTION TABLES 



Am54S/74S242 



Am54S/74S240 



Am54S/74S241 
Am54S/74S243 



INPUTS 


OUTPUTS 


1G 


2G 


A 


Y 


H 


L 


X 


Z 


L 


H 


L 


H 


L 


H 


H 


L 



INPUTS 


OUTPUT 




INPUTS 


OUTPUTS 


G 


A 


Y 




1G 


2G 


A 


Y 


H 


X 


z 




H 


L 


X 


z 


L 


H 


L 




L 


H 


H 


H 


L 


L 


H 




L 


H 


L 


L 



Am54S/74S244 



INPUTS 


OUTPUT 


G 


A 




H 


X 


z 


L 


H 


H 


L 


L 


L 



APPLICATIONS 

Am54S/74S241'S USED AS REPEATER/LEVEL RESTORER 



KtPfcATfcH HtffcA I bH Htl'bA I tH 

-.1/8 'S241 . 1/8'S241 1/8'S241 



INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT 



'S240 USED AS SYSTEM AND/OR MEMORY BUS DRIVER - 
4-BIT ORGANIZATION CAN BE APPLIED TO HANDLE BINARY OR BCD 



Am54S/74S240 

I 

T rK> 



CONTROL OR MICROPROGRAM ROM/PROM 
OR 

MEMORY ADDRESS REGISTER 



.j 



SYSTEM AND/OR MEMORY-ADDRESS BUS 



4-145 



Am54S/74S240/241 /242/243/244 



APPLICATIONS (Cont.) 



INDEPENDENT 4-BIT BUS 
DRIVERS/RECEIVERS 
IN A SINGLE PACKAGE 

Am54S.'74 S24Q 

i 



FROM 
DATA 
BUS 




PARTY-LINE BUS SYSTEM 
WITH MULTIPLE INPUTS, OUTPUTS, AND RECEIVERS 




NONE NONE 



Am54S/74S240 
Am54S/74S241 
Am54S/74S244 



Metallization and Pad Layouts 



Am54S/74S242 
Am54S/74S243 





DIE SIZE 0.077" X 0.124" 



DIE SIZE 0.077" X 0.124" 



4-146 



Am55/75107B • Am55/75108B 

Dual Line Receivers 



Distinctive Characteristics 



• Input sensitivity 3mV typical 

• Common mode range of ±3V 

• Common mode range of more than ±15V using ex- 
ternal attenuator 

• TTL compatible output 



High common mode rejection ratio 

Blocking diodes provide high input impedance 

Strobe and gate inputs for flexibility 

100% reliability assurance testing in compliance with 

MIL-STD-883 



FUNCTIONAL DESCRIPTION 



The Am55/75107B and Am55/75108B are high speed dual 
line receivers designed for use as data receivers in balanced, 
unbalanced or party-line transmission systems. The two line 
receivers in each package share the common voltage and ground 
busses. The Am55/75107B has a standard active pull-up totem- 
pole output while the Am55/75108B has an open collector 
output for bus organized systems. 

Each receiver has a high impedance differential input for 
minimum transmission line loading. The differential inputs of 
the Am55/75107B and Am55/75108B are designed to detect 
input signals of 25mV or greater and provide TTL compatible 
outputs. 



All devices contain blocking diodes in the input differential 
transistor pair collectors to provide high input impedance in 
the power-off condition. The SN55/75107A and SN55/75108A 
are identical devices except for these input protection diodes. 

Each receiver has a separate gate input, G. When the gate is 
LOW, the output is HIGH regardless of the other inputs. The 
device also has a common strobe, S, which can be used to gate 
both receivers simultaneously. When the strobe is LOW, the 
output is HIGH regardless of the other inputs. 

Note: Output HIGH on the Am55/75108B is high impedance condition. 



SCHEMATIC DIAGRAM 
(One Receiver Shown) 



^ 12012 



[_ "J" _J n OUTPUT 




^ STROBE 



V CC-C- 



Notes: 1. Components shown with dashed lines are applicable to the A m55/751 07B 

2. Rl = 1kO for Am55/75107B and 750fi for Am55/75108B 

3. D1 and D2 are the input protection diodes. 



LOGIC SYMBOL 



2 5 6 8 11 12 

1B 1G S 2G 2b| |2A 





Vcc— " p 'h 13 
V cc+ = Pin 14 
GND - Pin 7 



ORDERING INFORMATION 



Package 
Type 

-d DIP 
; c DIP 

-IP 



Temperature 
Range 

0°C to +70° C 
0°Cto+70°C 
0°Cto +70°C 
-55°Cto-H25°C 
:o+125°C 



Am55/ 
75107B 
Order 
Number 

SN75107BN 
SN75107BJ 



Am55/ 
751 08B 
Order 
Number 

SN75108BN 
SN75108BJ 



AM75107BX AM75108BX 
SN55107BJ SN55108BJ 
AM55107BX 



CONNECTION DIAGRAM 
Top View 




Note: Pin 1 is marked for orientation. 
NC = No connection. 



4-147 



Am55/75107B/108B 



MAXIMUM RATINGS (Above which the useful life may be impaired). 



Storage Temperature 



-65 C to+150°C 



Temperature (Ambient) Under Bias 



-55°Cto+125 C 



Positive Supply Voltage Vcc+ to Ground Potential Continuous 



+7.0V 



Negative Supply Voltage V cc _ to Ground Potential Continuous 



-7.0V 



DC Voltage Applied to Outputs for HIGH Output State 



-0.5V to +V CC+ max. 



DC Input Voltage - Strobe 



-0.5V to +5.5V 



Differential Input Voltage 



±6.0V 



Common Mode Input Voltage (with Respect to GND Terminal) 



+5.0V 



Any Differential Input to Ground 



-5.0V to +3.0V 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

The Following Conditions Apply Unless Otherwise Noted: 

Am75107B, Am75108B (COM'L) T A = 0°Cto70°C V cc+ - 5.0 V ± 5% V cc _ = -5.0 V ± 5% (COM'L) 

Am55107B, Am55108B (MIL) T A = -55°C to +1 25°C V cc+ - 5.0 V ± 1 0% V cc _ = -5.0 V * 5% (M I L) 



Parameters 




Description 


Test Conditions 

(Notes 1, 4, & 5) 




Min. 


Typ. 

(Note 2) 


Max. 


Units 


V H 




Output HIGH Voltage 
(Am55/75107B Only) 


V CC+ = MIN., V CC _-MIN. 
Iqh * -40G>A. V| C = -3V to 3V 


2.4 






Volts 


vol 




Output LOW Voltage 


V CC+ = MIN., V CC _ = MIN. 
I L = 16mA, V IC = -3V to 3V 






0.4 


Volts 


V|H 




Strobe or gate input 
HIGH Voltage 


See Test Table 


2.0 






Volts 


V|L 




Strobe or Gate Input 
LOW Voltage 


See Test Table 






0.8 


Volts 


V|DH 




Differential Input Voltage 
for Output HIGH 


See Test Table 


0.025 




5.0 


Volts 


VlDL 




Differential Input Voltage 
for Output LOW 


See Test Table 


-5.0 




-0.025 


Volts 


•|H 




Input HIGH Current 
into 1 A or 2A 


V CC+ = MAX., V C C- " M AX. 
V|q = 0.5V, V| C - -3V to 3V 




30 


75 


"A 


•l l_ 




Input LOW Current 
into 1 A or 2 A 


V C C+ ■ MAX., V cc _ = MAX. 
V| D = -2V, V| C = -3V to 3V 






-10 


uA 


>IH 




Input HIGH Current 


V C c+ = MAX., V C C- * MAX. 


S 






80 


"A 




V iH = 2.4V 


G 






40 


'I 




Input HIGH Current 


V C C+ = MAX., V CC _ = MAX. 


S 






2 


mA 






V| H =V CC +MAX. 


G 






1 


■ 1 1_ 




Input LOW Current 


V CC+ = MAX., Vcc- " MAX. 


S 






-3.2 


mA 




V| L -0.4V 


G 






-1.6 


'OH 




HIGH Level Output 
Leakage (Am55/75108B 
Onlyl 


V C C+ = MIN., V C C- - MIN. 
VOH = VCC+ MAX. 






250 


"A 


■sc 


Output Short Circuit 
Current (Note 3) 
(Am55/75107B 
Only) 


V CC + - MAX., V CC - " MAX. 


-18 




-70 


mA 


"CCH+ 


Positive Power Supply 
Current 


Vcc+ = MAX., V CC - - MAX. 
Vj D = 25mV, T A »25°C 




18 


30 


mA 


'CCH- 


Negative Power 
Supply Current 


VCC+ = MAX., V C C- " MAX. 
V| D = 25mV, T A = 25°C 




-8.4 


-15 


mA 


V| 


Input Clamp Voltage, 
S or G 


V C C+ = MIN., V C C- = MIN - 
I in = -12mA. Ta = 25°C 




-1 


-1.5 


Volts 



Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type. 

2. Typical limits are at VqC+ = 5 -0 v r V CC— = — 5 -0V, T A = 25°C ambient and maximum loading. 

3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 

4. Vjc = common mode voltage with respect to G NO terminal. 
V lD = differential voltage (V A - V B ). 



4-148 



Am55/75107B/108B 

SWITCHING CHARACTERISTICS <T A = +25°C, V cc + = 5V. V cc 
Parameters Description Test Conditions 



- = -5V) 



Typ. 



Units 



AmS5/75107B Only 



'PLH 




A and B to Output 


R |_ = 390 n 
C L = 50 pF 




17 


25 


ns 


«PHL 




A and B to Output 




17 


25 


ns 


*PLH 




G or S to Output 




10 


15 


ns 


tPHL 




G or S to Output 




8 


15 


ns 


Am55 


751 08B Only 


tPLH 




A and B to Output 


B L = 390« 
C L = 15pF 




19 


25 


ns 


«PHL 




A and B to Output 




19 


25 


ns 


«PLH 




G or S to Output 




13 


20 


ns 


tPHL 




G or S to Output 




13 


20 


ns 



DIFFERENTIAL Q 
INPUT 



PULSE 
GENERATOR 
ISee Note 1) 



AC PARAMETER MEASUREMENT INFORMATION 

TEST CIRCUIT 

<j>vcc- 





1G S |2G 

|\ |\ |j 



OUTPUT p 
Am55107B 
Am75107B 
Am75207 



390 il 



IN916 

C L 14 places) 

: 50 pF J^. 

(See Note 3) 



-KJ-KH4- 



PULSE 
GENERATOR 
(See Note 1] 



1 



I 



OUTPUT 
. Am55108B 
' Am75108B 

Am75207 



15 pF 

(See Note 3) 



VOLTAGE WAVEFORMS 



-»P2- 



STROBE 
INPUT - 
GorS 



£ 



'PHL— j- 



-if- 



v OL 



Notes: 1. The pulse generators have the following characteristics: Z out = 50 SI , t r = tf = 1 ± 5 ns, tp-j = 500 ns, PRR = 1 MHz, 
t p2 = 1 ms, PRR = 500 kHz. 

2. Strobe input pulse is applied to Strobe 1 G when inputs 1 A - 1 B are being tested, to Strobe S when inputs 1 A - 1 B or 
2A - 2B are being tested, and to Strobe 2G when inputs 2A - 2B are being tested. 

3. C)_ includes probe and jig capacitance. 



4-149 



Am55/75107B/108B 



PERFORMANCE CURVES 



High-Level Input Current 
Into 1A or 2A 
Versus 
Ambient Temperature 




75 -50 -25 25 50 75 100 125 
T A - AMBIENT TEMPERATURE - "C 



Recommended Combinations 
of Input Voltage for 
Line Receivers 




5 -4-3-2-10 1 2 3 
INPUT - B TO GROUND VOLTAGE - V 



High-Logic-Level Supply Current 
Versus 
Ambient Temperature 



-75 -50 -25 25 50 75 100 125 
T a - AMBIENT TEMPERATURE - "C 



Am55108B, Am75108B 
Propagation Delay Time 
Low-to-High Level 
Differential Inputs 
Versus 
Ambient Temperature 



V C C* ■ 5 V 
V CC .--5V 














15 pF 




390 


39, 




































R, -*» 

























-75 -50 -25 25 50 75 100 125 
T. - AMBIENT TEMPERATURE - °C 



Am55107B, Am75107B 
Propagation Delay Time 
Differential Inputs 
Versus 
Ambient Temperature 




-75 -50 -25 25 50 75 100 125 
T A - AMBIENT TEMPERATURE - "C 



Am55108B, Am75108B 
Propagation Delay Time 
High-to-Low Level 
Differential Inputs 
Versus 
Ambient Temperature 



v C c+- 
- v cc-" 

C L " 15 


5V 
5V 












pF 






















f* L - 


390 


1 
















— i 


r 




T 










■ 39C 


o n 


R 




950 


1 _ 



















-75 -50 -25 25 50 75 100 125 
T. - AMBIENT TEMPERATURE - °C 



Am55107B, Am75107B 
Propagation Delay Time 
Strobe Inputs 
Versus 
Ambient Temperature 



Am55108B, Am75108B 
Propagation Delay Time 
Strobe Inputs 
Versus 
Ambient Temperature 




'c 

R L 


; + -5v 
= -5 V 
i390S! 






















■ 15 


jF 













































I 
















































T 





-75 -50 -25 25 50 75 100 125 
J. - AMBIENT TEMPE RATURE - "C 



-75 -50 -25 25 50 75 100 125 
T A - AMBIENT TEMPERATURE - °C 



Note: Use 0°C to +70°C temperature range only for commercial {Am75 Series) devices. 



4-150 



Am55/75107B/108B 



FUNCTION TABLE 





Differential 
V|D = V A - V B 


Inputs 


Output 
Y 


Gate 


Strobe 


G 


s 




V|q > +25mV 


X 


X 


H 




-25mV < V|o < +25mV 


H 


H 


? 




V| D < -25m V 


H 


H 


L 




X 


L 


X 


H 




X 


X 


L 


H 


H 


= HIGH 








L 


= LOW 








X 


' Don't Care 








? 


- Don't Know 









DEFINITION OF FUNCTIONAL TERMS 

IA, 2A The non-inverting input of the line receivers. 

IB, 2B The inverting input of the line receivers. 
1Y, 2Y The output of each line receiver. 

1G, 2G The gate input of each line receiver. A LOW on the 
gate input force- the output HIGH. 

S The strobe input that is common to both line re- 

ceivers. A LOW on the strobe forces both (1Y 
and 2Y) outputs HIGH. 

V|c Input Common Mode voltage with respect to 
ground terminal. 

V|D Differential Input voltage (Va — Vfj). 




DEFINITION OF SWITCHING TERMS 

(All switching times are measured at the 1.5V logic level 
unless otherwise noted.) 

*PLH The propagation delay time from an input change to 

an output LOW-to-HIGH transition. 
*PHL ^he Propagation delay time from an input change to 

an output HIGH-to-LOW transition. 
t r Rise time. The time required for a signal to change 

from 10% to 90% of its measured values, 
tf Fall time. The time required for a signal to change 

from 90% to 10% of its measured values. 



^aram 


. 

DC TEST TABLE 
Vic V| D 

„ A OA 1B (Common (Differen- 1Y 
Bter 1A 2A 2 B Model tiall 2Y 1G 2G s Note 


V IDH 






-3V to 3V 


Test 


-400uA 
(Note 2) 


+5V 


+5V 




VlDL 






-3V to 3V 


Test 


16mA 


+5V 


+5V 




l|H <9> A 






-3V to 3V 


+0.5V 


Open 


Open 


Open 




@ A 






-3V to 3V 


-2V 


Open 


Open 


Open 




vql® 1 Y 






-3V to 3V 


-25mV 


16mA 


V|H 


V|H 




V H ®-V 






-3V to 3V 


+25mV 


-400(uA 


V|H 


VlH 


1 & 2 


V H@ Y 






-3V to 3V 


-25mV 


-400/jA 


V|L 


V|H 


1 & 2 


V 0H @Y 






-3V to 3V 


-25mV 


-400>A 


V|H 


V|L 


1 & 2 


Iqh® Y 






-3V to 3V 


+25mV 


Vcc + MAX. 


V| H 


VlH 


1 & 3 


■ OH® Y 






-3V to 3V 


-25mV 


v cc+ max. 


V|L 


VlH 


1 & 3 


"OH® Y 






-3V to 3V 


-25mV 


Vcc+MAX. 


V| H 


VlL 


1 & 3 


l|H @ 1G 


+25mV 


GND 


GND 






Open 




GND 


GND 




1 1 h ® 2G 


GND 


+25mV 


GND - - Open 






GND 




l|H@S 


+25mV 


+25mV 


GND 






Open 


GND 


GND 


V|H 




l| L @ 1G 


-25mV 


GND 


GND 






Open 


V|L 


GND 


4.5V 




l| L @2G 


GND 


-25mV 


GND 






Open 


GND 


VlL 


4.5V 




l| L @>S 


-25mV 


-25mV 


GND 






Open 


4.5V 


4.5V 


VlL 






@ Y 


+25mV 


GND 






GND 


GND 


GND 






+25mV 


GND 






Open 


+5V 


+5V 






+25mV 


GND 






Open 


+5V 


+5V 





•in testing one channel, the inputs of the other channels are grounded. 
S/75107B only. 
751088 only. 



4-151 



Ani55/75107B/108B 



APPLICATIONS 



BUS-ORGANIZED SYSTEM 




Am55/75108B 



Si IG 

Am55/75107B 




rt 




=D- 



B 



Am55/75110 



Metallization and Pad Layouts 



Am55/75107B 



Am55/75108B 



1Y 4 

IG 5 — 



film 



— 13 V CC- 

— 12 2A 

— 11 2B 

— 9 2Y 



J I L 

7 

GND 



-8 2G 



1A 1 

IB 2 

1Y 4 

IG 5 



13 »CC- 



— 12 2A 

— 11 2B 



DIE SIZE: 0.049" X 0.056" 



S 6 1 I 1 a 2G 

GND 

DIE SIZE: 0.049" X 0.056" 



4-152 



Am55/75109 • Am55/75110 

Dual Line Drivers 



Distinctive Characteristics 

• Input is TTL compatible. 

• High common-mode output range of — 3V to +10V. 

• Separate and common output inhibits. 



• Open-collector differential outputs for bus-organized 
systems. 

• 100% reliability assurance testing in compliance with 
MIL-STD-883. 



FUNCTIONAL 

The Am55/75109 and Am55/75110 are dual line drivers 
characterized for applications in balanced, unbalanced, and 
party-line systems. The drivers provide a constant current 
output that is switched to either of the two differential 
output terminals under the control of the A and B inputs. 
When A and B are HIGH, the Y output is HIGH and Z 
output is LOW 

These drivers feature a separate inhibit input, C, that is 
used to switch off the constant current output. This leaves 
the driver differential output in the high impedance state 
for use in bus organized systems. A LOW on the C input 



DESCRIPTION 

forces the driver to the OFF state by switching off the 
current source of the differential output transistor pair. 
Likewise, the two drivers have a common inhibit input, D, 
that forces both drivers to the OFF state. A LOW on the D 
inputs turns off the output current sources of both drivers 
such that both differential outputs are in the high 
impedance state. 

The driver outputs have a common mode voltage range 
of -3V to +10V. The Am55/75109 output current is 
typically 6mA while the Am55/75110 output current is 
typically 12mA. 



SCHEMATIC DIAGRAM 
(One Driver Shown) 




TO OTHER LINE DRIVER 



Notes: 1. Component values shown are nominal. 
2. Resistance values are in ohms. 



ORDERING INFORMATION 



Package 
Type 



Temperature 
Range 



Am 55/75109 
Order 
Number 



Am55/75110 
Order 
Number 



Molded DIP 
Hermetic DIP 
Dice 
-metic DIP 
^ice 



0°C to +70° C 
0° C to +70° C 
0°Cto +70° C 
-55°Cto+125°C 
-55°Cto+125°C 



SN75109N 

SN75109J 

AM75109X 

SN55109J 

AM55109X 



SN75110N 
SN75110J 
AM75110X 
SN55110J 
AM55110X 



CONNECTION DIAGRAM 





Top View 








□ v CCt 


■ B[- 


2 13 


□ * 


kC 


3 12 




«c 


Am55/75109 
4 An>55/751 10 ^ ' 


□ v cc- 




5 10 


□° 




6 9 


□** 


gndQ 


V 8 


^2Y 



LIC-480 

Note: 

Pin 1 is marked for orientation. 



LOGIC SYMBOL 




V cc+ -Pin14_ 

12 V CC- = Pin 11 

GND =- Pin 7 



4-153 



Am55/75109/110 



MAXIMUM RATINGS (Above which the use 


Storage Temperature 



life may be impaired) 



-65 C to +150 C 



Temperature (Ambient) Under Bias 



-55°Cto+125"C 



Vqq + Supply Voltage to Ground Potential 



+7V 



Vqq_ Supply Voltage to Ground Potential 



-7V 



Common Mode DC Voltage Applied to Outputs 



-5V to+12V 



DC Input Vol 



age 



-0.5V to +V cc+ max. 



DC Input Current 



-30mA to +5. 0mA 



ELECTRICAL CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE 

The Following Conditions Apply Unless Otherwise Noted: 



Am75109, Am751 1 
Am55109, Am55110 



Parameters 



V cc + MIN. = 4.75V 
V cc+ MIN. ' 4.5V 



Description 



V cc+ MAX. = 5.25V, 
V CC+ MAX. » 5.5V, 



V cc _ MIN. = -4.75V 
V CC _ MIN. » -4.5V 



Test Conditions (Note 1) 



v C c- MAX - 



fvlin. 



= -5.25V. 
- -5.5V. 

Typ. 

(Note 2) 



: C to +70 C 

■ -55°C to +125°C 



Max. 



Units 



V IH 


Input HIGH Level 


Guaranteed input logical HIGH 
voltage for all inputs 


2.0 


1 

5.5 Volts 


V| L 


Input LOW Level 


Guaranteed input logical LOW 
voltage for all inputs 







0.8 


Volts 


hL 

(Note 3) 


Input Low Current 
Am55/75109 


V CC+ = MAX., V| N = 0.4 V 
V C C- " MAX. 


A, B 






-3 


mA 


C 






-1.6 


D 






-3 


(Note 3) 


Input LOW Current 
Am55/75110 


V CC+ = MAX., V| N = 0.4 V 
V CC _ = MAX. 


A, B, C 






-3 


mA 


D 






-6 


■|H 

(Note 3) 


Input HIGH Current 


V CC+ = MAX., V|N = 2.4 V 
V CC _ = MAX. 


A, B, C 






40 


»iA 


D 






80 




Input HIGH Current 


V cc+ = MAX., V in = MAX. 
V cc _ = MAX. 


A, B, C 






1 


mA 


D 






2 


lolonl 


Output Current On-State 


V CC + = MAX. 
V C C- = MAX. 


109 






7 


mA 


110 






15 


lo(on) 


Output Current On-State 


V C C+ = MIN. 
V CC _ - MAX. 


109 


3.5 






mA 


110 


6.5 






l (off) 


Output Current Off -State 


V cc+ = MIN. 
V cc _ = MIN. 








100 


MA 


l cc+ (on) 


Positive Supply Current; 
Driver Enabled 


A and B = 0.4V 
C and D = 2.0V 


109 




18 


30 


mA 


110 




23 


35 


'cc-lo") 


Negative Supply Current; 
Driver Enabled 


A and B = 0.4V 
Cand D = 2.0V 


109 




-18 


-30 


mA 


110 




-34 


-50 


i C c+(°ffl 


Positive Supply Current; 
Driver Disabled 


All Inputs = 0.4V 


109 




18 




mA 


110 




21 




icc-loW 


Negative Supply Current; 
Driver Disabled 


All Inputs = 0.4V 


109 




-10 




mA 


110 




-17 





Notes: 1. For conditions shown as MIN. or MAX., use the appropriate value specified under Electrical Characteristics for the applicable device type. 

2. Typical limits are at Vqq+ = 5.0V, V^C— = —5.0V, = 25° C ambient and maximum loading. 

3. Actual input currents = Unit Load Current X Input Load Factor (See Loading Rules). 



Switching Characteristics (T A = +25°C) 



Parameters 


Description 


Test Conditions 


Min. 


Typ. 


Max. 


Units 


tPLH 


A or B to Y or Z 






9 


15 


ns 


«PHL 


A or B to Y or Z 


V CC+ = 5.0 V, V C C- ■ -5.0 V, 




9 


15 


ns 


«PLH 


C or D to Y or Z 


R L = 50n, C L = 40pF 




16 


25 


ns 


tPHL 


C or D to Y or Z 






13 


25 


ns 



4-154 



Am55/J51 09/110 



OFF 

OFF 

ON 

ON 

OFF 



OFF 
OFF 
OFF 
OFF 
ON 



H = HIGH 
L = LOW 

ON = lo(°n) Current 
OFF = l (off) Current 
X = Don't Care 









Am55/ 


Output Output 


Input/Output 


Pin No.'s 


75109 


75110 


HIGH LOW 


1 A 


1 


1-7/8 


1-7/8 




IB 


2 


1-7/8 


1 -7/8 




1C 


3 


1 


1 -7/8 




2C 


4 


1 


1-7/8 




2A 


5 


1-7/8 


1-7/8 




2B 


6 


1-7/8 


1-7/8 




GND 


7 








2Y 


8 






/ Diff \ 


*Y7 

mm 


g 






\output / 


D 


10 


1 -7/8 


3-3/4 




Vcc- 


1 1 








1Z 


12 






( ) 


1Y 


13 






Voutput/ 


V CC+ 


14 








A TTL Unit Load is defined 


as 40 mA measured at 2.4 V HIGH and 


-1 .6mA measured at 0.4 V LOW. 







Am55109, Am 75109 
Output Current 
Versus 
Logic Input Voltage 



V CC+ = 5 V 
v 












■ ia*— 
»|-V,H 














: - 


























I I 
OUTPUT 






! 

OUTPUT 




Z 




I 

























1.2 1.3 1.4 

- LOGIC INPUT VOLTAGE - 











1 

'cc- 














































c- - 
















































V|L 


= 0.4 


V 












V IH- 2V 

v cc +- 5v 

V CC _--5V 













PERFORMANCE CURVES 
(Typical) 

Am55110, Am75110 
Output Current 
Versus 
Logic Input Voltage 



Am55110, Am75110 
Supply Current With Driver Enabled 
Versus - 
Ambient Temperature 






































TP! 

Z 


T 




1 


OUT 


PUT 







































Vrr 


1 

.'SV 












v cc-"- sv 
v, - v,„ 

T A ■ 26"C 













1 1.2 1.3 1.4 

V, - LOGIC INPUT VOLTAGE - V 

Propagation Delay Time 
Logic Inputs 
Versus 
Ambient Temperature 



V CC+ - 5 V 
V CC _--5V 













"L 

c L ■ 


40 p 


F 






























tp, H PHL 







































-75 - 50 -25 25 50 75 100 125 
T A - AMBIENT TEMPERATURE - 'C 



Note: For Am75 Series use 0°C to +70°C temperature range only. 



-75 - 50 -25 25 50 75 100 125 
BIENT TEMPERATURE -°C 



Am55109, Am75109 
Supply Current With Driver Enabled 
Versus 
Ambient Temperature 



V| L = 0.4V 
V IH .2V 

v C c+" 5v 






















v cc 




5 V 












I 














































cc - 















































-75 - 50 -25 25 50 75 100 125 
T A - AMBIENT TEMPERATURE - "C 

Propagation Delay Time 
Inhibit Inputs 
Versus 
Ambient Temperature 



v C c+ ■ 5 v 

V CC _--5V 
R L «50!J 
























40p 


F 























































































-75 - 50 - 25 25 50 75 1 00 125 
T A - AMBIENT TEMPERATURE - "C 



4-155 



Am55/75109/110 

DC TEST TABLE 



Parameter 


INPUTS 

A B C D 


OUTPUTS 
Y Z 


V|H 




Test 


Open 


V|H 


VlH 


OFF ON 


V|H 




Open 


Test 


V|H 


VlH 


OFF 


ON 


V IL 




Test 


V CC+ 


V|H 


V|H 


ON 


OFF 


V|L 




V CC+ 


Test 


VlH 


V IH 


ON 


OFF 


l|H 




Test 


GND 


V|H 


V|H 


GND 


GND 


'IH 




GND 


Test 


V|H 


V|H 


GND 


GND 


"IL 




Test 


4.5 V 


V|H 


V|H 


GND 


GND 


'IL 




4.5 V 


Test 


V|H 


V|H 


GND 


GND 


V| H 




V|H 


V|H 


Test 


Open 


OFF 


ON 


V| H 




V|H 


VlH 


Open 


Test 


OFF 


ON 


V|H 




VlL 


VlL 


Test 


Open 


ON 


OFF 


V|H 




VlL 


VlL 


Open 


Test 


ON 


OFF 


V|L 




VlH 


V|H 


Test 


Open 


OFF 


OFF 


VlL 




V|H 


V|H 


Open 


Test 


OFF 


OFF 


V|L 




VlL 


VlL 


Test 


V CC+ 


OFF 


OFF 


VlL 




VlL 


VlL 


V CC+ 


Test 


OFF 


OFF 


'IH 




GND 


GND 


Test 


GND 


GND 


GND 


'IH 




GND 


GND 


GND 


Test 


GND 


GND 


■ 1 1_ 




GND 


GND 


Test 


4.5 V 


GND 


GND 


!|L 




GND 


GND 


4.5 V 


Test 


GND 


GND 


'Olonl 




VlL 


VlL 


V|H 


VlH 


Test 


Note 1 


'Olonl 




VlL 


VlH 


V|H 


VlH 


Test 


Note 1 


'O(on) 




VlH 


VlL 


VlH 


VlH 


Test 


Note 1 


'Olon) 




V|H 


VlH 


V| H 


VlH 


Note 1 


Test 


lO(off) 




VlH 


VlH 


VlH 


VlH 


Test 


Note 1 


'Oloffl 




VlL 


VlL 


VlH 


V|H 


Note 1 


Test 


'Oloff) 




VlL 


VlH 


VlH 


VlH 


Note 1 


Test 


'Oloffl 




VlH 


V|L 


VlH 


VlH 


Note 1 


Test 


'O(off) 




X 


X 


V|L 


V|L 


Test 


Test 


^(off) 




X 


X 


V|U 


V|H 


Test 


Test 


'O(off) 




X 


X 


V|H 


VlL 


Test 


Test 


•cc+lon) 




VlL 


VlL 


VlH 


VlH 


GND 


GND 


'CC-lon 




V|L 


VlL 


VlH 


VlH 


GND 


GND 


'CC+loff) 


VlL 


VlL 


VlL 


VlL 


GND 


GND 


'CC-(off) 


VlL 


V|L 


VlL 


VlL 


GND 


GND 



X = Don't Care; Note 1 : Output not under test must have a low impedance (<50S2) termination to GND. 



AC PARAMETER MEASUREMENT INFORMATION 
TEST CIRCUIT 




LIC-483 



4-156 



Am55/75109/110 



AC VOLTAGE WAVEFORMS 



LOGIC 
INPUT ■ 
A OR B 



INHIBITOR 
INPUT 
COR 



£ 



I- 



ov 

. 3V 
1.5 V 
OV 

OFF 
■ 60% 
• ON 

. OFF 
50% 



otes: 1. The pulse generators have the following characteristics: Z out = 50fi, t r ■ tf = 1.0 ±5ns; t pw i = 500ns, PRR = 1 MHz; 
t pw2 = 1 /is, PRR = 500kHz. 

2. C L includes probe and jig capacitance. 

3. For simplicity, only one channel and the inhibitor connections are shown. 



UNIT LOAD DEFINITIONS 

HIGH 



LOW 



SERIES 


Current 


Measure 
Voltage 


Current 


Measure 
Voltage 


Am25/26/2700 


40> A 


2.4 V 


-1.6 mA 


0.4 V 


Am25S/26S/27S 


50 M A 


2.7 V 


-2.0mA 


0.5 V 


Am25L/26L/27L 


20 u A 


2.4 V 


—0.4 mA 


0.3 V 


Am25LS/26LS/27LS 


20 M A 


2.7 V 


-0.36 mA 


0.4 V 


Am54/74 


40 u A 


2.4 V 


-1.6mA 


0.4 V 


54H/74H 


50 u A 


2.4 V 


-2.0mA 


0.4 V 


Am54S/74S 


50uA 


2.7 V 


-2.0mA 


0.5 V 


54L/74L 
(Note 1) 


20uA 


2.4 V 


-0.8 mA 


0.4 V 


54L/74L 
(Note 11 


10mA 


2.4 V 


-0.18mA 


0.3 V 


Am54LS/74LS 


20 u A 


2.7 V 


—0.36 m A 


0.4 V 


Am9300 


40 u A 


2.4 V 


-1.6mA 


0.4 V 


Am93L00 


20 u A 


2.4 V 


-0.4 mA 


0.3V 


Am93S00 


50 M A 


2.7V 


-2.0 mA 


0.5 V 


Am75/85 


40 uA 


2.4 V 


-1.6mA 


0.4 V 


Am8200 


40uA 


4.5V 


-1 .6 mA 


0.4 V 



Note: 1 . 54L/74L has two different types of standard inputs. 



DEFINITION OF FUNCTIONAL TERMS 

1A, 2A, IB, 2B The TTL data inputs to each driver. 

1C, 2C The TTL inhibit inputs to each driver. A LOW input 

forces both outputs to the off -state. 



D The common TTL inhibit input to both drivers. A 
LOW input forces all four outputs to the off -state. 
1 Y, 2Y, 1Z, 2Z The differential output of each driver. 




4-157 



Am55/75109/110 



APPLICATIONS 




1 



Am55/75109 or Am55/751 10 in a unbalanced or single-ended connection. 



o- 





'OUT - 2'otON, 



Two line drivers connected in parallel for higher current. 




Metallization and Pad Layouts 

09 Am55/75110 

v cc* 




Am71/81LS95 • Am71/81 LS96 
Am71/81LS97 • Am71/81 LS98 



Three-State Octal Buffers 



DISTINCTIVE CHARACTERISTICS 

• Three-state outputs drive bus line directly 

• Typical propagation delay 
Am71/81LS95, Am71/81LS97 
Am71/81LS96, Am71/81LS98 

• Typical power dissipation 
Am71/81LS95, Am71/81LS97 
Am71/81LS96, Am71/81LS98 

• PNP inputs reduce DC loading on bus lines 

• Am71/81LS96 and Am71/81LS98 are inverting; 
Am71/81LS95 and Am71/81LS97 are non-inverting 

• 20-pin hermetic and molded DIP packages 

• 100% product assurance testing to MIL-STD-883 
requirements 



13ns 
10ns 

80mW 
65mW 



GENERAL DESCRIPTION 

The Am71/81LS95, Am71/81LS96, Am71/81LS97 and Am71/ 
81LS98 are octal buffers fabricated using Advanced Low- 
Power Schottky technology. The 20-pin package provides im- 
proved printed circuit board density for use in memory ad- 
dress and clock driver applications. 

The Am71/81LS95 and Am71/81LS97 present true data at the 
outputs, while the Am71/81LS96 and Am71/81LS98 are invert- 
ing. The Am71/81LS95 and Am71/81LS96 have a common 
enable for all eight buffers with access through a 2-input NOR 
gate. The Am71/81LS97 and Am71/81LS98 octal buffers have 
four buffers enabled from one common line, and the other four 
buffers enabled from another common line. In all cases the 
outputs are placed in the three-state condition by applying a 
high logic level to the enable pins. All parts feature low current 
PNP inputs. 



Am71/81LS95 



"1 



*8 — 



Am71/81LS96 



LOGIC DIAGRAMS 

Am71/81LS97 



«3— ^> Vj *i 

5, — ^>cJ Sj 



•LS95 



LS96 



INPUTS 


OUTPUT 
Y 




INPUTS 


OUTPUT 
Y 


G i 


G 2 


A 


G, I G2 


A 


H 


X 


X 


2 




H [ X 


X 


Z 


X 


H 


X 


Z 




X H 


X 


z 


L 


L 


H 


H 




L L 


H 


L 


L 


L 


L 


L 




L | L 


L 


H 



Am71/81LS98 



->:- 

'LS97 



A 8 

5,- 
LIC-490 



->:- 



LS98 



Am71/81LS95 



r 



□ w cc 

35. 
3*. 

3»' 

3*. 

3»» 



CONNECTION DIAGRAMS - Top Views 



Am71/81LS96 




Am71/81LS97 




Am71/81LS98 




4-159 



Am71 LS/81 LS/95/96/97/98 



MAXIMUM RATINGS above which the i 
Storage Temperature 



paired 



-65°C to +150°C 



Temperatun 



Dient) Under Bias 



-55°C to +125°C 



Supply Voltage to Ground Potential 



-0.5V to +7.0V 



DC Voltage Applied to Outputs for HIGH Output State 



-0.5V to +V CC max. 



DC Input Voltage 



-0.5V to +7.0V 



DC Output Current 



150mA 



DC Input Current 







-30mA to +5.0mA 



ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Specified: 
COM'L T A = 0°C to +70°C V cc = 5.0V ± 5% (MIN. 
MIL T A = -55°C to +125°C V cc = 5.0V ±10% (MIN. 



■ 4.75V MAX. 

■ 4.50V MAX. 



■ 5.25V) 
■■ 5.50V) 



DC CHARACTERISTICS OVER OPERATING RANGE 



Parameters 



Description 



Test Conditions 



Min 



Am71/81LS95 
Am71/81LS96 
Am71/81LS97 
Am71/81LS98 

Typ. 
(Note 1) Max. 



Units 



VlH 


High Level Input Voltage 




2 






Volts 


V|L 


Low Level Input Voltage 








0.8 


Volts 


v. 


Input Clamp Voltage 


Vcc = Min., h = -18mA 






-1.5 


Volts 


! OH 


Hig 


h Level Output Current 


MIL 






-1.0 


mA 


COM'L 






-2.6 


V H 


Hig 


h Level Output Voltage 


V C c = Min - V| H = 2 0V 
V, L = 0.8V 


COM'L 


Iqh = -5.0mA 


2.4 






Volts 


Iqh = -2.6mA 


2.7 






MIL, l OH = -1.0mA 


2.5 






l0L 


Low Level Output Current 


COM'L 






16 


mA 


MIL 






8 


Vol 


Low Level Output Voltage 


V cc = Min., V| H = 2.0V 
V| L = 0.8V 


COM'L, l 0L = 16mA 






0.5 


V 


MIL, l 0L = 8.0mA 






0.4 


'O(OFF) 


Off 
Sta 


State (High-Impedance 
te) Output Current 


V cc = Max., V| H =2.0V 
V, L = 0.8V 


V = 0.4V 






-20 


/aA 


V = 2.4V 






20 


j 


Inp 
Inp 


ut Current at Maximum 
Lit Voltage 


V cc = Max., V, = 7.0V 






0.1 


mA 


|h 


Hig 


h Level Input Current 


V cc = Max- V| = 2.7V 






20 


/jA 


L 


Lov 
Inp 


v Level 
ut Current 


A Input 


Vcc = Max - 


Both G Inputs at 2.0V 
Both G Inputs at 0.4V 


V, = 0.5V 






-50 


/i.A 


V, = 0.4V 






-0.36 


mA 


G Input 




V, = 0.4V 






-0.36 


'os 


Sh( 


>rt Circuit Output Current 


V cc = Max. (Note 2) 


-30 


-60 


-130 


mA 


ice 


Su| 


>ply Current 


V cc = Max. 


Am71/81LS95, Am71/81LS97 




16 


26 


mA 


Am71/81LS96, Am71/81LS98 




13 


21 



Notes: 1. All 
2. Not 



typical 
more 



values are at V C c = 5.0V, T A = 25°C. 

than output should be shorted at a time, and duration of the short circuit should not exceed one second. 



SWITCHING CHARACTERISTICS V cc = 5.0V, T A = 25°C 



Am71/81 LS95 
Am71/81LS97 



Am71/81LS96 
Am71/81LS98 



Parameters 



Description 



Test Conditions 



Min. Typ. Max. Min. Typ. Max. 



>PLH 


Propagation Delay Time, 
Low-to-High Level Output 


C L = 15pF, R[_ = 2kn 




11 


16 




6 


10 


ns 


*PHL 


Propagation Delay Time, 
High-to-Low Level Output 




15 


22 




13 


17 


ns 


tZH 


Output Enable Time to High Level 




16 


25 




17 


27 


ns 


•ZL 


Output Enable Time to Low Level 




13 


20 




16 


25 


ns 


'HZ 


Outp 


Jt Disable Time from HIGH Level 


C L = 5pF, R L = 2k£l 




13 


20 




13 


20 


ns 


kz 


Outp 


jt Disable Time from Low Level 




19 


27 




18 


27 



4-160 



Am71 LS/81 LS/95/96/97/98 



SWITCHING CHARACTERISTICS TEST CONDITIONS 



LOAD CIRCUIT FOR 
THREE-STATE OUTPUTS 



VOLTAGE WAVEFORMS 
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS 



FROM OUTPUT 
UNDER TEST 



C-495 




OUTPUT 
CONTROL 
(LOW-LEVEL 
(ENABLING) 



\" ' Z 



-H- 



WAVEFORM 2- 



S-, CLOSED 
SjOPEN 



S, OPEN 
S2 CLOSED 



s 1 & s 2 

CLOSED 



0.5 V \ 
\ 0.5 V 



s,&s 2 

CLOSED 



Notes: 1 . Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. 

2. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 

3. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. 

4. Pulse generator characteristics: PRR < 1MHz, ZrjUT ^ 50ft, t r < 15ns, tf < 6ns. 

5. When measuring tp LH and tp H L. switches S-| and S 2 are closed. 



Am7 



APPLICATIONS 

AS SYSTEM AND/OR MEMORY BUS DRIVER 



CONTROL OR MICROPROGRAM ROM/PROM 



MEMORY ADDRESS REGISTER 



r 



=T> 



SYSTEM AND/OR MEMORY ADDRESS B 



INDEF 



' 4-BfT BUS DRIVERS/RECEIVERS IN A SINGLE PACKAGE 

Am71/8ILS98 



OUTPUT 
PORTS 



FROM 
DATA 
BUS 




L 



4-161 



Am71 LS/81 LS/95/96/97/98 



OROE 



DERING INFORMATION 



Molded DIP 
Hermetic DIP 
Hermetic DIP 
Dice 



Package 
Type 



Temperature 
Range 



Order Number 

Am71/81LS95 Am71/81LS96 Am71/81LS97 Am71/81LS98 



0°C to +70°C 



DM81LS95N 



DM81LS96N DM81LS97N DM81LS98N 



DM81LS95J 
DM71LS95J 



0°C to +70°C 
-55°C to + 125°C 
0°C to +70°C 



DM81LS96J 
DM71LS96J 
AM81LS96X 



DM81LS97J 
DM71LS97J 
AM81LS97X 



DM81LS98J 
DM71LS98J 
AM81LS98X 



4-162 



Am73/8303B 

Octal Three-State Inverting Bidirectional Transceiver 



DISTINCTIVE CHARACTERISTICS 

• 8-bit bidirectional data flow reduces system package count 

• Three-state inputs/outputs for interfacing with bus-oriented 
systems 

• PNP inputs reduce input loading 

• V CC -1-15V V 0H interfaces with TTL, MOS, and CMOS 

• 48mA, 3 00pF bus drive capability 

• Transmit/Receive and Chip Disable simplify control logic 

• 20 pin ceramic and molded DIP package 

• Low power - 8mA per bidirectional bit 

• Advanced Schottky processing 

• Bus port stays in hi-impedance state during power up/down 

• 100% product assurance screening to MIL-STD-883 
requirements 



GENERAL DESCRIPTION 

The Am73/8303Bs are 8-bit three-state Schottky inverting trans- 
ceivers. They provide bidirectional drive for bus-oriented micro- 
processor and digital communications systems. Straight through 
bidirectional transceivers are featured, with 16mA drive capa- 
bility on the A ports and 48mA bus drive capability on the B 
ports. PNP inputs are incorporated to reduce input loading. 



One input, Transmit/Receive determines the direction of logic 
signals through the bidirectional transceiver. The Chip Disable 
input disables both A and B ports by placing them in a three- 
state condition. 

The output high voltage (V h) is specified at V cc - 1.15V 
minimum to allow interfacing with MOS, CMOS, TTL, ROM, 
RAM, or microprocessors. 




CONNECTION DIAGRAM 
Top View 



V CC B B 1 B 2 B 3 B 4 B 5 B 6 B 7 T/R 

nnnnnnnnnn 



20 19 18 17 16 15 14 13 12 11 



123456789 10 



uuuuuuuuuu 

Aq A, A 2 A 3 A^ Ag Ag A 7 CD GND 



Note: Pin 1 is marked for orientation. 



LOGIC SYMBOL 



1 2 3 4 5 6 7 

u u u u 



A Ai A 2 A3 A4 A5 Ag A7 

D 

Am73/8303B 

Bq B n B 2 B 3 B 4 B 5 B 6 B 7 



TTTTTTTT 

19 18 17 16 15 14 13 12 



V cc = Pin 20 
GND = Pin 10 



4-163 



Am73/8303B 



ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired) 



Storage Temperature 




-65°C to + 150°C 


Supply Voltage 




7.0V 


Input Voltage 




5.5V 


Output Voltage 




5.5V 


Lead Temperature (Soldering. 10 seconds) 





300°C 



ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Noted: 

Am7303B T A = -55°C to +125°C V CC MIN = 4.5V V cc MAX = 5.5V 
Am8303B T A = 0°C to +70°C V CC MIN = 4.75V V CC MAX = 5.25V 

DC ELECTRICAL CHARACTERISTICS over operating temperature range 



Parameters 



Description 



Test Conditions 



Min. 



Typ. 

(Note 1) 



Max. 



Units 





A PORT (A -A 7 ) 






Logical "1" Input Voltage 


CD = 0.8V, T/R = 2.0V 


2.0 






Volts 


VlL 


Logical "0" Input Voltage 


CD = 0.8V, 
T/R = 2.0V 


Am8303B 






0.8 


Volts 


Am7303B 






0.7 


V H 


Logical "1" Output Voltage 


CD = 0.8V, 
T/R = 0.8V 


Ioh = -0.4mA 


v C c- 1 - 15 


Vcc-0-7 




Volts 


l 0H = -3.0mA 


2.7 


3.95 




v OL 


Logical "0" Output Voltage 


CD = 0.8V, 
T/R = 0.8V 


I l = 8mA 




0.3 


0.4 


Volts 


Am8303B, l 0L = 16mA 




0.35 


0.50 


'os 


Output Short Circuit Current 


CD = 0.8V, T/R = 0.8V, V Q = 0V, 
V cc = MAX., Note 2 


-10 


-38 


-75 


mA 


<IH 


Logical "1" Input Current 


CD = 0.8V, T/R = 2.0V, V, = 2.7V 




0.1 


80 


M A 


"l 


Input Current at Maximum Input Voltage 


CD = 2.0V, V cc = MAX., V| = V cc MAX. 






1 


mA 


IlL 


Logical "0" Input Current 


CD = 0.8V, T/R = 2.0V, V, = 0.4V 




-70 


-200 


mA 


v c 


Input Clamp Voltage 


CD = 2.0V, l IN = -12mA 




-0.7 


-1.5 


Volts 


'OD 


Output/Input Three-State Current 


CD - 2.0V 


V = 0.4V 






-200 


^A 


V = 4.0V 






80 




B PORT (B -B 7 


) 


V|H 


Logical "1" Input Voltage 


CD = 0.8V, T/R = 0.8V 


2.0 






Volts 


V|L 


Logical "0" Input Voltage 


CD = 0.8V, T/R = 0.8V 


Am8303B 






0.8 


Volts 


Am7303B 






0.7 


VOH 


Logical "1" Output Voltage 


CD = 0.8V, T/R = 2.0V 


Iqh = -0.4mA 


Vcc-1. 1 5 


Vcc-0.8 




Volts 


I h = "5mA 


2.7 


3.9 




Iqh = -10mA 


2.4 


3.6 




Vol 


Logical "0" Output Voltage 


CD = 0.8V, T/R = 2.0V 


l 0L = 20mA 




0.3 


0.4 


Volts 


l 0L = 48mA 




0.4 


0.5 


!os 


Output Short Circuit Current 


CD = 0.8V, T/R = 2.0V, V = 0V, 
V C c = MAX - Note 2 


-25 


-50 


-150 


mA 


llH 


Logical "1" Input Current 


CD = 0.8V, T/R = 0.8V, V, = 2.7V 




0.1 


80 


/n.A 


I, 


Input Current at Maximum Input Voltage 


CD = 2.0V, V cc = MAX., V, = V cc MAX. 






1 


mA 


hi 


Logical "0" Input Current 


CD = 0.8V, T/R = 0.8V, V, = 0.4V 




-70 


-200 


mA 


v c 


Input Clamp Voltage 


CD = 2.0V, l m = -12mA 




-0.7 


-1.5 


Volts 


l0D 


Output/Input Three-State Current 


CD = 2.0V 


V = 0.4V 






-200 


fiA 


V = 4.0V 






200 




CONTROL INPUTS CD, T/R 


V| H 


Logical "1" Input Voltage 




2.0 






Volts 


V|L 


Logical "0" Input Voltage 








0.8 


Volts 


l|H 


Logical "1" Input Current 


V, = 2.7V 




0.5 


20 


MA 


l| 


Input Current at Maximum Input Voltage 


V cc = MAX., V, = V cc MAX. 






1.0 


mA 


Nl 


Logical "0" Input Current 


V, = 0.4V 


T/R 




-0.1 


-.25 


mA 


CD 




-0.25 


-.5 


v c 


Input Clamp Voltage 


l|N = -12mA 




-0.8 


-1.5 


Volts 




POWER SUPPLY CURRENT 








ice 


Power Supply Current 


CD = 2.0V, V cc = MAX., V, N = 0.4V 




60 


130 


mA 


CD = V, NA = 0.4V, T/R = 2V, V cc = MAX. 




80 


160 



4-164 



Am73/8303B 

AC ELECTRICAL CHARACTERISTICS (V cc = 5.0V, T A = 25°Q 



iyp. 

Parameters Description Test Conditions Mln. (Note 1) Max. Units 





A PORT DATA/MODE SPECIFICATIONS 


'PDHLA 


Propagation Delay to a Logical "0" from 
B Port to A Port 


CD = 0.4V, T/R = 0.4V (Figure 1) 
R-, = 1k, R 2 = 5k, C, = 30pF 




8 




ns 


'PDLHA 


Propagation Delay to a Logical "1" from 
B Port to A Port 


CD = 0.4V, T/R = 0.4V (Figure 1) 
Rl = 1k, R 2 = 5k, C, = 30pF 




7 




ns 


tpLZA 


Propagation Delay from a Logical "0" to 
Three-State from CD to A Port 


B to B 7 = 0.4V, T/R = 0.4V (Figure 3) 
S 3 = 1, R 5 = 1k, C 4 = 15pF 




11 




ns 


tpi 


HZA 


Propagation Delay from a Logical "1" to 
Three-State from CD to A Port 


B to B 7 = 2.4V, T/R = 0.4V (Figure 3) 
S 3 = 0, R 5 = 1k, C 4 = 15pF 




8 




ns 


tp; 


LA 


Propagation Delay from Three-State to 
a Logical "0" from CD to A Port 


B to B 7 = 0.4V, T/R = 0.4V (Figure 3) 
S 3 = 1, R 5 = 1k, C 4 = 30pF 




27 




ns 


tp; 


HA 


Propagation Delay from Three-State to 
a Logical "1" from CD to A Port 


B to B 7 = 2.4V, T/R = 0.4V (Figure 3) 
S 3 = 0, R 5 = 5k, C 4 = 30pF 




19 




ns 




B PORT DATA/MODE SPECIFICATIONS 


'PDHLB 


Propagation Delay to a Logical "0" from 
A Port to B Port 


CD = 0.4V, T/R = 2.4V (Figure 1 ) | 
R, = 100fl, R 2 = 1k, Ci = 300pF 




12 




ns 


R-, = 6670, R 2 = 5k, C, = 45pF 




7 




tp 


3LHB 


Propagation Delay to a Logical "1" from 
A Port to B Port 


CD = 0.4V, T/R = 2.4V (Figure 1) | 
R, = 1000, R 2 = 1k, C, = 300pF 




10 




ns 


R, = 667a R 2 = 5k, C, = 45pF 




7 




*PLZB 


Propagation Delay from a Logical "0" to 
Three-State from CD to B Port 


A to A 7 = 0.4V, T/R = 2.4V (Figure 3) 
S 3 = 1, R 5 = 1k, C 4 = 15pF 




13 




ns 


*PHZB 


Propagation Delay from a Logical "1" to 
Three-State from CD to B Port 


A to A 7 = 2.4V, T/R = 2.4V (Figure 3) 
S 3 = 0, R 5 = 1k, C 4 = 15pF 




8 




ns 


'PZLB 


Propagation Delay from Three-State to 
a Logical "0" from CD to B Port 


A to A 7 = 0.4V, T/R = 2.4V (Figure 3) 
S 3 = 1, R 5 = 100fi, C 4 = 300pF 




32 




ns 


S 3 = 1, R 5 = 66711, C 4 = 45pF 




16 




<PZHB 


Propagation Delay from Three-State to 
a Logical "1" from CD to B Port 


A to A 7 = 2.4V, T/R = 2.4V (Figure 3) 
S 3 = 0, R 5 = 1k, C 4 = 300pF 




26 




ns 


S 3 = 0, R 5 = 667fl, C 4 = 45pF 




14 




TRANSMIT RECEIVE MODE SPECIFICATIONS 


•PHZfl 




Propagation Delay from a Logical "1" to 
Three-State from T/R to A Port 


CD = 0.4V (Figure 2) 

S-| = 1, R 4 = 100fl, C 3 = 300pF 

S 2 = 0, R 3 = 1k, C 2 = 15pF 




7 




ns 


tpLZR 


Propagation Delay from a Logical "0" to 
Three-State from T/R to A Port 


CD = 0.4V (Figure 2) 

S-, = 0, R 4 = 1k, C 3 = 300pF 

S 2 = 1, R 3 = 1k, C 2 = 15pF 




10 




ns 


>PHZT 


Propagation Delay from a Logical "1" to 
Three-State from T/R to B Port 


CD = 0.4V (Figure 2) 

S, = 0, R 4 = 1k, C 3 = 15pF 

S 2 = 1 , R 3 = 5k, C 2 = 30pF 




16 




ns 


•PLZT 


Propagation Delay from a Logical "0" to 
Three-State from T/R to B Port 


CD = 0.4V (Figure 2) 

S, = 1, R 4 = 1k, C 3 = 15pF 

S 2 = 0, R 3 = 1k, C 2 = 30pF 




17 




ns 


'PRL 


Propagation Delay jrom Transmit Mode 
to a Logical "0", T/R to A Port 


'PRL = IPHZT + 'PDHLA 




23 




ns 


tpRH 




Propagation Delay from Transmit Mode 
to a Logical "1", T/R to A Port 


'PRH = 'PLZT + tpDLHA 




28 




ns 


*PTL 


Propagation Delay from Receive Mode 
to a Logical "0", T/R to B Port 


4 PTL = 'PHZR + 'PDHLB 




23 




ns 


<PTH 


Propagation Delay from Receive Mode 
to a Logical "1", T/R to B Port 


'PTH = <PLZR + 'PDLHB 




24 




ns 



Notes: 1 All typical values given are for Vcc = 5 0v and T A = 25°C. 
2. Only one output at a time should be shorted. 



FUNCTIONAL TABLE 



Inputs 


Conditions 


Chip Disable 








1 


Transmit/Receive 





1 


X. 


A Port 


Out 


In 


Hl-Z 


B Port 


In 


Out 


Hl-Z 



4-165 



Am73/8303B 



SWITCHING TIME WAVEFORMS 
AND AC TEST CIRCUITS 



1.5V J r 



OUTPUT 



r 



9 V CC 



INPUT 
O 



DEVICE 
UNDER 
TEST 



OUTPUT 
O 



if 



t r = t f < 1 0ns 
10% to 90% 



Note: C-i includes test fixture capacitance. 



if 



•PLZR 
0.5V 



Figure 1. Propagation Delay from A Port to B Port 
or from B Port to A Port. 



tPLZT 
0.5V 



y ^ po.5- 

t± 




t r = tf < 10ns 
10% to 90% 



Note: C2 and C3 include test fixture capacitance. 
Figure 2. Propagation Delay from T/R to A Port or B Port. 



LIC-505 



PORT 
OUTPUT 



if 



PORT 
OUTPUT 



'=1 r= 

zf 



<PLZ 
0.6V 



'PZH - 




t r = tf < 1 0ns 
10% to 90% 



)v cc 



DEVICE 
UNDER 
TEST 




Vcc 



Note: C4 includes test fixture c 

Port input is in a fixed logical condition. 



Figure 3. Propagation Delay from CD to A Port or B Port. 



4-166 



Am73/8303B 



Metallization and Pad Layout 




§□ 
S3 
S3 

b 



19 B„ 



18 B, 

17 B 2 
16 B 3 



15 B 4 

14 B 5 



12 B 7 



11 T/R 



DIE SIZE 0.066" x 0.086" 



ORDERING INFORMATION 



Package 
Type 



Temperature 
Range 



Order 
Number 



Hermetic DIP 
Hermetic DIP 
Molded DIP 
Dice 



-55°C to +125°C 
0°C to +70°C 
0°C to +70°C 
0°C to +70°C 



DP7303BJ 
DP8303BJ 
DP8303BN 
AM8303BX 



Am73/8304B 

Octal Three-State Bidirectional Transceiver 



DISTINCTIVE CHARACTERISTICS 

• 8-bit bidirectional data flow reduces system package count 

• Three-state inputs/outputs for interfacing with bus-oriented 
systems 

• PNP inputs reduce input loading 

• V CC -1.15V V 0H interfaces with TTL, MOS, and CMOS 

• 48mA, 3 00pF bus drive capability 

• Transmit/Receive and Chip Disable simplify control logic 

• 20 pin ceramic and molded DIP package 

• Low power - 8mA per bidirectional bit 

• Advanced Schottky processing 

• Bus port stays in hi-impedance state during power up/down 

• 100% product assurance screening to MIL-STD-883 
requirements 



GENERAL DESCRIPTION 

The Am73/8304Bs are 8-bit three-state Schottky transceivers. 
They provide bidirectional drive for bus-oriented microproces- 
sor and digital communications systems. Straight through 
bidirectional transceivers are featured, with 16mA drive capa- 
bility on the A ports and 48mA bus drive capability on the B 
ports. PNP inputs are incorporated to reduce input loading. 



One input, Transmit/Receive determines the direction of logic 
signals through the bidirectional transceiver. The Chip Disable 
input disables both A and B ports by placing them in a three- 
state condition. 

The output high voltage (V 0H ) is specified at V CC -1.15V 
minimum to allow interfacing with MOS, CMOS, TTL, ROM, 
RAM, or microprocessors. 



*0 A l 



LOGIC DIAGRAM 



A 2 A3 A 4 A5 Aj A, 



-5- 



A 



A 



A 



A 



A 



TTTTTiTT 



fori 



B B, 



B 3 B 4 



=5 B 6 8, 







CONNECTION DIAGRAM 
Top View 



V CC B B 1 B 2 B3 B 4 H H B7 T/R 

nnnnnnnnnn 

19 18 17 16 15 14 13 12 11 



1 2 3456789 10 



uuuuuuuuuu 

*0 A 1 *2 A 3 A 4 A 5 H A 7 CD GND 



Note: Pin 1 is marked for orientation. 



LOGIC SYMBOL 



1 2 3 4 5 6 7 8 



Ao A, 


A 2 


-3 


«< 


A 5 


A 6 


A? 


CD 














T/H 


/ 












B B, 








B 5 




B 7 


l l 

19 18 


l 

17 


1 

16 


I 

15 


l 

14 


1 

13 


l 

12 

















V CC = Pin 20 
GND = Pin 10 



4-168 



Am73/8304B 




ABSOLUTE MAXIMUM RATINGS (Above which the useful life may be impaired) 




Storage Temperature 


-65°C to +150°C 


Supply Voltage 


7.0V 


Input Voltage 


5.5V 


Output Voltage 


5.5V 


Lead Temperature (Soldering, 10 seconds) 


300°C 







ELECTRICAL CHARACTERISTICS 

The Following Conditions Apply Unless Otherwise Noted: 

Am7304B T A = -55°C to +125°C V CC MIN = 4.5V V CC MAX = 5.5V 
Am8304B T A = 0°C to +70°C V CC MIN = 4.75V V CC MAX = 5.25V 

DC ELECTRICAL CHARACTERISTICS over operating temperature range 



iyp. 

Parameters Description Test Conditions Min. (Notei) Max. Units 





A PORT (A -A 7 ) 


V|H 




Logical "1" Input Voltage 


CD = V, L MAX.,T/F 


= 2.0V 


2.0 






Volts 


V,L 




Logical "0" Input Voltage 


CD = V| U MAX., 
T/R = 2.0V 


Am8304B 






0.8 


Volts 


Am7304B 






0.7 


VOH 




Logical "1 " Output Voltage 


CD = V| L MAX., 
T/R = 8.0V 


Iqh = -0.4mA 


Vcc-1,15 


Vcc-0-7 




Volts 


I h = -3.0mA 


2.7 


3.95 




Vol 




Logical "0" Output Voltage 


CD = V| L MAX., 
T/R = 8.0V 


Iol = 8mA 




0.3 


0.4 


Volts 


Am8304B,l OL = 16mA 




0.35 


0.50 


bs 




Output Short Circuit Current 


CD = V, L MAX., T/R = 0.8V, V = 0V, 
V C c = MAX - N o te 2 


-10 


-38 


-75 


mA 


■|H 




Logical "1" Input Current 


CD = V| L MAX., T/R = 2.0V, V, = 2.7V 




0.1 


80 


/*A 


l| 




Input Current at Maximum Input Voltage 


CD = 2.0V, V cc = MAX., V, = V cc MAX. 






1 


mA 


l|L 




Logical "0" Input Current 


CD = V, L MAX., T/R = 2.0V, V, = 0.4V 




-70 


-200 


fjA 


v c 




Input Clamp Voltage 


CD = 2.0V, l IN = -12mA 




-0.7 


-1.5 


Volts 






Output/Input Three-State Current 


CD = 2.0V 


V = 0.4V 






-200 


ma 


V = 4.0V 






80 




B PORT (B -B 7 ) 


v IH 




Logical "1" Input Voltage 


CD = V| L MAX., T/R = V, L MAX. 


2.0 






Volts 






Logical "0" Input Voltage 


CD = V| U MAX., 
T/R = V, L MAX. 


Am8304B 






0.8 


Volts 


Am7304B 






0.7 


VOH 


L 


Logical "1" Output Voltage 


CD = V, L MAX., T/R = 2.0V 


Iq h = -0.4mA 


V cc -1.15 


V CC "0.8 




Volts 


bH = -5mA 


2.7 


3.9 




Ioh = -10mA 


2.4 


3.6 




Vol 




Logical "0" Output Voltage 


CD = V| L MAX.,T/R = 2.0V 


Iql = 20mA 




0.3 


0.4 


Volts 


Iql = 48mA 




0.4 


0.5 


bs 


Output Short Circuit Current 


CD = V, L MAX., T/R = 2.0V, V = 0V, 
Vcc = MAX., Note 2 


-25 


-50 


-150 


mA 


Iih 


Logical "1" Input Current 


CD = V| L MAX., T/R = V| L MAX., V, = 2.7V 




0.1 


80 


mA 


ii 


Input Current at Maximum Input Voltage 


CD = 2.0V, V cc = MAX., V, = V cc MAX. 






1 


mA 


IlL 


Logical "0" Input Current 


CD = % MAX., T/R = V, L MAX., V, = 0.4V 




-70 


-200 


fiA 


v c 


Input Clamp Voltage 


CD = 2.0V, l IN = -12mA 




-0.7 


-1.5 


Volts 


bD 


Output/Input Three-State Current 


CD = 2.0V 


V = 0.4V 






-200 


fiA 


V = 4.0V 






200 


CONTROL INPUTS CD, T/R 


V,H 


Logical "1" Input Voltage 




2.0 






Volts 


V|L 


Logical "0" Input Voltage 




Am8304B 






0.8 


Volts 


Am7304B 






0.7 


■iH 


Logical "1" Input Current 


V, = 2.7V 




0.5 


20 


MA 


I, 


Input Current at Maximum Input Voltage 


V CC = MAX., V, = V CC MAX. 






1.0 


mA 


IlL 


Logical "0" Input Current 


V, = 0.4V 


T/R 




-0.1 


-.25 


mA 


CD 




-0.25 


-.5 


V C 


Input Clamp Voltage 


l JN = —12mA 




-0.8 


-1.5 


Volts 




POWER SUPPLY CURRENT 


be 




Power Supply Current 


CD = 2.0V, V cc = MAX., V, N = 0.4V 




60 


100 


mA 


CD = V, NA = 0.4V, T/R = 2V, V cc = MAX. 




80 


130 



4-169 



AC ELECTRICAL CHARACTERISTICS (V cc = 5.0V, T A = 25°q 
Parameters Description Test Conditions 



Am73/8304B 



Typ. 

Min. (Note 1) Max. Units 



DATA/MODE SPECIFICATIONS 



l PDHLA 



Propagation Delay to a Logical "0" from 
B Port to A Port 



CD = 0.4V, T/R = 0.4V (Figure 1) 
Rl = 1k, R 2 = 5k, Ci = 30pF 



18 



tpDLHA 



Propagation Delay to a Logical "1" from 
B Port to A Port 



CD = 0.4V, T/R = 0.4V (Figure 1) 
Ri = 1k, R 2 = 5k, C, = 30pF 



13 



<PLZA 



Propagation Delay from a Logical "0" to 
Three-State from CD to A Port 



B to B 7 = 0.4V, T/R - 0.4V (Figure 3) 
S 3 = 1, R 5 = 1k, C 4 = 15pF 



15 



tpHZA 



Propagation Delay from a Logical "1" to 
Three-State from CD to A Port 



B to B 7 = 2.4V, T/R = 0.4V (Figure 3) 
S 3 = 0, R 5 = 1k, C 4 = 15pF 



'pzla 



Propagation Delay from Three-State to 
a Logical "0" from CD to A Port 



B to B 7 = 0.4V, T/R = 0.4V (Figure 3) 
S 3 = 1, R 5 = 1k, C 4 = 30pF 



27 



35 



tpZHA